A conflict-aware automatic routing method and system for analog integrated circuits

Abstract

The application discloses a conflict-aware automatic routing method and system for analog integrated circuits, and relates to the technical field of computers.The method comprises the following steps: constructing a minimum spanning tree based on layout file information of the analog integrated circuit, generating a topology of the analog integrated circuit based on the minimum spanning tree, and obtaining target topology information; performing access point planning processing based on the target topology information; performing initial path planning based on the target topology information and access point planning information, performing line network distribution on the initial path information based on a cross relationship graph, and obtaining initial path information after line network distribution; performing 3D monotonic routing processing on the initial path information after line network distribution; and performing enhanced routing processing based on 3D monotonic routing information by using an A algorithm, and obtaining target routing information of the analog integrated circuit.The application realizes reliable routing in a complex layout environment, and ensures that the routing result meets production process rules.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a collision-aware automatic routing method and system for analog integrated circuits. Background Technology

[0002] For a long time, analog layout routing has relied primarily on manual design by experienced senior engineers. While manual design can meticulously account for various complex physical constraints, its drawbacks are becoming increasingly apparent in today's rapidly evolving chip market. First, development cycles are excessively long, with routing for a single module often taking weeks or even months. Second, differences in the habits of different engineers can lead to uncontrollable performance fluctuations. Finally, manual routing is no longer suitable for the rapid iteration of massive interconnect requirements in modern large-scale sensitive mixed-signal systems. Therefore, driving the automation of routing processes has become an industry goal.

[0003] Despite some progress in automated routing algorithms, existing technologies still exhibit significant limitations when addressing real-world engineering challenges. For instance, template-based methods achieve rapid routing using pre-defined templates based on human experience, but these templates have extremely poor universality. When faced with irregular topologies, they require substantial manpower for reconstruction, failing to achieve universal design. Heuristic rule-based methods attempt to encode human experience into hard rules, but in complex cross-layer routing and multi-signal interference environments, simple heuristic logic struggles to cover all dynamic conflicts, often resulting in routing outcomes that, while conforming to rules, suffer from poor electrical performance. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a collision-aware automatic routing method and system for analog integrated circuits, which realizes reliable routing in complex layout environments and ensures that the routing results comply with production process rules.

[0005] To address the aforementioned technical problems, this invention provides a collision-aware automatic routing method for analog integrated circuits, the method comprising: Obtain the layout file information of the analog integrated circuit, construct a minimum spanning tree based on the layout file information, generate the topology of the analog integrated circuit based on the minimum spanning tree, and obtain the target topology information; Based on the target topology information, access point planning processing is performed to obtain access point planning information; Initial path planning is performed based on the target topology information and access point planning information to obtain initial path information. Then, based on the cross relationship diagram, the initial path information is allocated to obtain the initial path information after the allocation of the network. Perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information; Based on the 3D monotonic wiring information, using A The algorithm performs enhanced routing processing to obtain the target routing information for the analog integrated circuit.

[0006] Optionally, the step of constructing a minimum spanning tree based on the layout file information, and generating the topology of the analog integrated circuit based on the minimum spanning tree to obtain the target topology information includes: Based on the layout file information, extract the rectangular pin information of each device, calculate the horizontal and vertical gaps between the rectangular pin information, and calculate the Manhattan distance between the rectangular pins based on the horizontal and vertical gaps. Based on the Kruskal algorithm, a minimum spanning tree is constructed using the Manhattan distance combined with the disjoint-setup loop detection method; The underlying connections of the analog integrated circuit are determined based on the minimum spanning tree, and the target topology information of the analog integrated circuit is determined based on the underlying connections.

[0007] Optionally, the expression for the horizontal gap is: , in, For horizontal gaps, Let x be the x-coordinate of the lower left corner of the first rectangular pin. Let x be the x-coordinate of the upper right corner of the first rectangular pin. The x-coordinate of the lower left corner of the second rectangular pin is given. The x-coordinate of the upper right corner of the second rectangular pin; The expression for the vertical gap is: , in, For vertical gaps, Let be the y-coordinate of the lower left corner of the first rectangular pin. Let be the y-coordinate of the upper right corner of the first rectangular pin. Let y be the y-coordinate of the lower left corner of the second rectangular pin. The y-coordinate of the upper right corner of the second rectangular pin; The expression for the Manhattan distance is: , Where d is the Manhattan distance. For horizontal gaps, This is the vertical gap.

[0008] Optionally, the step of performing access point planning processing based on the target topology information to obtain access point planning information includes: Based on the target topology information, several main rectangles are determined using a preset rectangle multidimensional selection criterion; Analyze the direction between the main rectangles and determine the offset information based on the direction between the main rectangles; Candidate access points are generated based on the offset information, grid index intervals are determined, and coordinate sequence information of the candidate access points is determined based on the grid index intervals. Access point planning information is determined based on the coordinate sequence information of the candidate access points.

[0009] Optionally, determining the offset information based on the direction between the main rectangles includes: If the analysis shows that the directions between the main rectangles are opposite, then the offset information is determined based on the cross-reference strategy; If the analysis shows that the directions between the main rectangles are in the same direction, then the offset information is determined based on the compactness priority strategy.

[0010] Optionally, the step of performing net allocation on the initial path information based on the cross-relationship graph to obtain the initial path information after net allocation includes: Based on the initial path information, analyze the crossover information of the wire network wiring, and construct a crossover relationship diagram based on the crossover information; Based on the cross relationship diagram, the network cross degree is set, the Manhattan line length of the net is determined, and the network cross degree and the Manhattan line length of the net are normalized to obtain the normalized network cross degree and the normalized Manhattan line length of the net. The priority weight of the net is determined based on the normalized network crossover degree and the normalized net Manhattan line length. Based on the net priority weight, the initial path information is allocated nets to obtain the initial path information after net allocation.

[0011] Optionally, the expression for the network crossover degree is: , in, For network cross-section, Represents the i-th wire mesh. Describes the j-th wire mesh. This represents the k-th wire mesh; The expression for the wire priority weight is: , in, For net priority weights, To normalize the network crossover degree, The weight coefficients for normalized network crossover. To normalize the Manhattan line length, The weighting coefficients for the Manhattan line length of the normalized network.

[0012] Optionally, the step of performing 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information includes: Set a comprehensive cost function, the expression of which is: , in, For the comprehensive cost function, For the cost of the conductor, To cover the cost of turning, For through-hole cost, , , These are the weighting coefficients; Based on the comprehensive cost function, dynamic programming and priority queue mechanism are used to perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information.

[0013] Optionally, the step of utilizing A based on the 3D monotonic wiring information... The algorithm performs enhanced routing processing to obtain the target routing information of the analog integrated circuit, including: For A The algorithm sets up an expansion buffer and a space pruning mechanism to obtain an improved A. Algorithm, to determine the improved A The cost function of the algorithm; Based on the aforementioned 3D monotonic wiring information, an improved A The algorithm and cost function are used to enhance the routing process and obtain the target routing information of the analog integrated circuit.

[0014] In addition, the present invention also provides a collision-aware automatic routing system for analog integrated circuits, the system comprising: Topology generation module: used to obtain the layout file information of the analog integrated circuit, construct a minimum spanning tree based on the layout file information, and generate the topology of the analog integrated circuit based on the minimum spanning tree to obtain the target topology information; Access point planning module: used to perform access point planning processing based on the target topology information to obtain access point planning information; Network allocation module: used to perform initial path planning based on the target topology information and access point planning information to obtain initial path information, and to perform network allocation based on the cross relationship diagram to obtain initial path information after network allocation; Monotonic routing module: Used to perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information; Enhanced routing module: used to utilize A based on the 3D monotonic routing information. The algorithm performs enhanced routing processing to obtain the target routing information for the analog integrated circuit.

[0015] In this embodiment of the invention, layout file information of analog integrated circuits is obtained; a minimum spanning tree is constructed based on the layout file information; topology generation of the analog integrated circuit is performed based on the minimum spanning tree to obtain target topology information; access point planning is performed based on the target topology information; initial path planning is performed based on the target topology information and access point planning information; wire mesh allocation is performed on the initial path information based on the cross relationship graph to obtain initial path information after wire mesh allocation; 3D monotonic routing processing is performed on the initial path information after wire mesh allocation to eliminate the influence of routing conflicts, which can minimize the number of vias and reduce path parasitic resistance and capacitance. Based on the 3D monotonic routing information, A... The algorithm performs enhanced routing processing to obtain target routing information for analog integrated circuits, enabling reliable routing in complex layout environments and ensuring that the routing results comply with manufacturing process rules. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the collision-aware automatic routing method for analog integrated circuits in an embodiment of the present invention. Figure 2 This is a flowchart illustrating a collision-aware automatic routing method for analog integrated circuits according to another embodiment of the present invention. Figure 3 This is a schematic diagram of the structural composition of a collision-aware automatic routing system for analog integrated circuits according to an embodiment of the present invention; Figure 4 This is an example diagram of the disjoint-set data structure loop detection algorithm in an embodiment of the present invention; Figure 5 This is a comparison diagram of the results of 3D monotonic wiring processing and traditional wiring processing in this embodiment of the invention; Figure 6 This is an improvement A in the embodiments of the present invention. A schematic diagram of the algorithm's search mechanism. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1 Please see Figure 1 , Figure 1 This is a flowchart illustrating a collision-aware automatic routing method for analog integrated circuits according to an embodiment of the present invention. The method includes: S11: Obtain the layout file information of the analog integrated circuit, construct a minimum spanning tree based on the layout file information, generate the topology of the analog integrated circuit based on the minimum spanning tree, and obtain the target topology information; In the specific implementation of this invention, the layout file information of the analog integrated circuit is obtained, the rectangular pin information of each device is extracted based on the layout file information, and the horizontal and vertical gaps between the rectangular pin information are calculated. The Manhattan distance between the rectangular pins is calculated based on the horizontal and vertical gaps. The minimum spanning tree is constructed based on the Kruskal algorithm using the Manhattan distance combined with the disjoint-setup loop detection method. The bottom-level connection of the analog integrated circuit is determined based on the minimum spanning tree, and the target topology information of the analog integrated circuit is determined based on the bottom-level connection. This realizes the bottom-level optimization of the wiring topology, enabling the selection of better connection points in the wiring and reducing the total wiring length.

[0020] S12: Perform access point planning processing based on the target topology information to obtain access point planning information; In the specific implementation of this invention, several main rectangles are determined based on the target topology information using a preset rectangular multi-dimensional selection criterion; the direction between the main rectangles is analyzed, and offset information is determined based on the direction between the main rectangles; candidate access points are generated based on the offset information, a grid index interval is determined, and the coordinate sequence information of the candidate access points is determined based on the grid index interval; access point planning information is determined based on the coordinate sequence information of the candidate access points, thus ensuring the physical legality of the access location.

[0021] S13: Perform initial path planning based on the target topology information and access point planning information to obtain initial path information, and perform wire network allocation on the initial path information based on the cross relationship diagram to obtain initial path information after wire network allocation; In the specific implementation of this invention, initial path planning is performed based on the target topology information and access point planning information to obtain initial path information. The crossover information of the network cabling is analyzed based on the initial path information, and a crossover relationship diagram is constructed based on the crossover relationship diagram. The network crossover degree is set based on the crossover relationship diagram, the Manhattan line length of the network is determined, and the network crossover degree and the Manhattan line length are normalized to obtain normalized network crossover degree and normalized Manhattan line length. Network priority weights are determined based on the normalized network crossover degree and normalized Manhattan line length. Network allocation is performed on the initial path information based on the network priority weights to obtain the initial path information after network allocation. This makes the overall structure compact, significantly reduces the number of unnecessary interlayer vias in the cabling path, and reduces parasitic resistance and capacitance on the path.

[0022] S14: Perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information; In the specific implementation of this invention, a comprehensive cost function is set, and based on the comprehensive cost function, dynamic programming and priority queue mechanism are used to perform 3D monotonic routing processing on the initial path information after network allocation to obtain 3D monotonic routing information, thereby reducing the number of path bends and computational burden, and thus optimizing the overall routing efficiency and quality.

[0023] S15: Based on the 3D monotonic wiring information, utilize A The algorithm performs enhanced routing processing to obtain the target routing information for the analog integrated circuit.

[0024] In the specific implementation of this invention, A The algorithm sets up an expansion buffer and a space pruning mechanism to obtain an improved A. Algorithm, to determine the improved A The cost function of the algorithm; based on the 3D monotonic routing information, using the improved A The algorithm and cost function are used to enhance the routing process and obtain the target routing information of the analog integrated circuit, ensuring that the routing results not only comply with the stringent manufacturing process rules, but also have excellent electrical performance.

[0025] In this embodiment of the invention, layout file information of analog integrated circuits is obtained; a minimum spanning tree is constructed based on the layout file information; topology generation of the analog integrated circuit is performed based on the minimum spanning tree to obtain target topology information; access point planning is performed based on the target topology information; initial path planning is performed based on the target topology information and access point planning information; wire mesh allocation is performed on the initial path information based on the cross relationship graph to obtain initial path information after wire mesh allocation; 3D monotonic routing processing is performed on the initial path information after wire mesh allocation to eliminate the influence of routing conflicts, which can minimize the number of vias and reduce path parasitic resistance and capacitance. Based on the 3D monotonic routing information, A... The algorithm performs enhanced routing processing to obtain target routing information for analog integrated circuits, enabling reliable routing in complex layout environments and ensuring that the routing results comply with manufacturing process rules.

[0026] Example 2 Please see Figure 2 , Figure 2 This is a flowchart illustrating a collision-aware automatic routing method for analog integrated circuits according to another embodiment of the present invention, the method comprising: S201: Obtain the layout file information of the analog integrated circuit, extract the rectangular pin information of each device based on the layout file information, calculate the horizontal and vertical gaps between the rectangular pin information, and calculate the Manhattan distance between the rectangular pins based on the horizontal and vertical gaps. In a specific implementation of this invention, the expression for the horizontal gap is: , in, For horizontal gaps, Let x be the x-coordinate of the lower left corner of the first rectangular pin. Let x be the x-coordinate of the upper right corner of the first rectangular pin. The x-coordinate of the lower left corner of the second rectangular pin is given. The x-coordinate of the upper right corner of the second rectangular pin; The expression for the vertical gap is: , in, For vertical gaps, Let be the y-coordinate of the lower left corner of the first rectangular pin. Let be the y-coordinate of the upper right corner of the first rectangular pin. Let y be the y-coordinate of the lower left corner of the second rectangular pin. The y-coordinate of the upper right corner of the second rectangular pin; The expression for the Manhattan distance is: , Where d is the Manhattan distance. For horizontal gaps, This is the vertical gap.

[0027] Specifically, the layout file information of the analog integrated circuit is obtained, including the netlist, layout, and process files of the analog integrated circuit. Based on the layout file information, the rectangular pin information of each device is extracted, and the horizontal and vertical gaps between the rectangular pins are calculated. The expression for the horizontal gap is: , in, For horizontal gaps, Let x be the x-coordinate of the lower left corner of the first rectangular pin. Let x be the x-coordinate of the upper right corner of the first rectangular pin. The x-coordinate of the lower left corner of the second rectangular pin is given. The x-coordinate of the upper right corner of the second rectangular pin; The expression for the vertical gap is: , in, For vertical gaps, Let be the y-coordinate of the lower left corner of the first rectangular pin. Let be the y-coordinate of the upper right corner of the first rectangular pin. Let y be the y-coordinate of the lower left corner of the second rectangular pin. The y-coordinate of the upper right corner of the second rectangular pin.

[0028] The Manhattan distance between the rectangular pins is calculated based on the horizontal and vertical gaps, and the expression for the Manhattan distance is: , Where d is the Manhattan distance. For horizontal gaps, This represents the vertical gap. This calculation method ensures that the minimum spanning tree topology accurately reflects the geometric redundancy of the layout, thereby optimizing the overall routing design.

[0029] S202: Construct a minimum spanning tree based on the Kruskal algorithm using the Manhattan distance combined with the disjoint-setup loop detection method; In the specific implementation of this invention, a minimum spanning tree is constructed based on the Kruskal algorithm using the Manhattan distance combined with the disjoint-set data structure for loop detection. A minimum spanning tree is an acyclic subgraph structure in graph theory that connects all vertices in the graph and has the minimum total edge weight. Here, vertices are rectangular pins, and edges are connections between any two rectangles, with their weights defined by the Manhattan distance.

[0030] The minimum spanning tree is generated using Kruskal's algorithm. The process begins by constructing a weighted edge set. By traversing all pairs of rectangles and calculating the Manhattan distance between each pair, corresponding weighted edges are generated. This distance accurately reflects the spatial relationship between the rectangles, providing a foundation for subsequent optimization. All edges are sorted in ascending order of weight to support a greedy strategy that prioritizes the edge with the smallest weight in constructing the minimum spanning tree. During this process, a disjoint-set data structure is used to efficiently detect cycles, ensuring the minimum spanning tree is cycle-free and reducing the search time complexity to approximately [missing information - likely a time complexity range]. This significantly improves algorithm efficiency.

[0031] Cycle detection steps: In the process of constructing the minimum spanning tree using Kruskal's algorithm, cycle detection is completed through a disjoint-set data structure. 1. Initially, each rectangular node constitutes an independent connected component. 2. For each candidate edge sorted in ascending order of weight, a search operation is performed on its two endpoints to obtain the corresponding root node and determine its connected component. Case 1: If the root nodes of the two endpoints are the same, it means that they are already indirectly connected through edges in the current spanning tree. Adding this edge would form a cycle, so the edge is judged as a cycle edge and discarded. Case 2: If the root nodes of the two endpoints are different, it means that the edge connects two different connected components. Adding this edge will not create a cycle. The algorithm adds this edge to the minimum spanning tree accordingly and merges the two connected components into one through a merge operation. Through the above mechanism based on connected component determination, the algorithm always ensures the acyclicity of the spanning tree during the construction process.

[0032] Examples of disjoint-set loop detection algorithms are as follows: Figure 4As shown, in the initial state, all pin nodes (Pin1–Pin6) form a weighted graph with redundant connections through candidate edges. When constructing the minimum spanning tree, the algorithm processes these candidate edges sequentially in ascending order of edge weight, and at each step, uses a disjoint-set data structure to determine if a cycle will form. Specifically, when processing a candidate edge, it first searches for the currently connected components to which the pin nodes at both ends of the edge belong. For example, in the step shown in the upper right of the diagram, when attempting to add a candidate edge connecting Pin1 and Pin4, the algorithm finds that Pin1 and Pin4 are already indirectly connected through the path Pin1–Pin3–Pin4, meaning they belong to the same connected component. Adding this candidate edge would create a closed loop in the existing connected structure, therefore, the edge is determined to be a cycle edge and discarded (marked with a cross in the diagram). Conversely, for candidate edges shown in the other steps of the diagram, when their two endpoints belong to different connected components, the algorithm adds the edge to the spanning tree and merges the corresponding connected components. By repeating the above judgment process for each candidate edge, the algorithm gradually expands the connected structure while always avoiding the introduction of cycles, thus ensuring that the final connected result is a cycle-free minimum spanning tree. When traversing the sorted edges, if the two vertices of an edge belong to different sets, these sets are merged and the edge is added to the minimum spanning tree; if they belong to the same set, the edge is discarded to avoid cycles. When the number of edges in the minimum spanning tree reaches n-1 (n is the number of rectangles), the algorithm stops through an early termination mechanism to further optimize computational efficiency.

[0033] By constructing an MST (Mean Transformer Set), we can ensure that all rectangular pins are connected with minimal total wiring cost. Compared to traditional methods, this approach better utilizes pin shape information, allowing for the selection of optimal connection points in the wiring and reducing overall wiring length.

[0034] S203: Determine the underlying connections of the analog integrated circuit based on the minimum spanning tree, and determine the target topology information of the analog integrated circuit based on the underlying connections; In the specific implementation of this invention, the bottom-level connections of the analog integrated circuit are determined based on the minimum spanning tree. That is, the minimum spanning tree defines the bottom-level connections by optimizing the weights, and the target topology information of the analog integrated circuit is determined based on the bottom-level connections. Rectangular pins are used as topology vertices on the bottom-level connections, and the edge weights are defined by combining the Manhattan distance between rectangles, so as to achieve bottom-level optimization of the wiring topology.

[0035] S204: Perform access point planning processing based on the target topology information to obtain access point planning information; In a specific implementation of this invention, the step of performing access point planning processing based on the target topology information to obtain access point planning information includes: determining several main rectangles based on the target topology information using a preset rectangle multi-dimensional selection criterion; analyzing the direction between the main rectangles and determining offset information based on the direction between the main rectangles; generating candidate access points based on the offset information, determining grid index intervals, and determining coordinate sequence information of the candidate access points based on the grid index intervals; and determining access point planning information based on the coordinate sequence information of the candidate access points.

[0036] Specifically, based on the target topology information, several main rectangles are determined using a preset multi-dimensional rectangle selection criterion. That is, the main rectangles are selected as reference bases from the complex pin geometry description according to the target topology information. The selection of the main rectangles follows a preset multi-dimensional rectangle selection criterion: the rectangle with the largest area is selected first to provide the largest physical access surface; if the areas are equal, the rectangle that can shorten the path is selected by calculating the minimum Manhattan distance between the candidate rectangles and the target pin.

[0037] Analyze the directions between the main rectangles and determine the offset information based on these directions. Different strategies are required to determine the offset information for different main rectangles. Based on this offset information, candidate access points are generated; that is, physically valid candidate access points are generated according to the offsets. The grid index interval is then determined, and its expression is as follows: , in, This represents the minimum value within the grid index range. The maximum value of the grid index range. The coordinates of the lower left corner of the main rectangle's pins. The coordinates of the bottom right corner of the main rectangle's pins. For line width, For offset information, This represents the grid step size.

[0038] Based on the grid index interval, the coordinate sequence information of the candidate access points is determined. The expression for the coordinate sequence information is: , in, This is the coordinate sequence of the candidate access points along the X-axis. This represents the minimum value within the grid index range. The maximum value of the grid index range. For offset information, The coordinate sequence in the Y-axis direction can be obtained in a similar way, with the grid step size as the coordinate step. The coordinate sequences in the X-axis direction and the Y-axis direction together form the coordinate sequence information of the candidate access point.

[0039] Based on the coordinate sequence information of the candidate access points, access point planning information is determined. The physical coordinates of each generated access point are precisely positioned on the translated grid line, thus completing the access point planning. Simultaneously, for pins distributed across multiple layers, multi-layer access points are selected to avoid densely packed metal layers and reduce the use of vias. The system also uniformly models prohibited wiring areas or obstacles, automatically discarding candidate points falling within these areas to ensure the physical legitimacy of the access location.

[0040] Furthermore, the determination of offset information based on the direction between the main rectangles includes: if the direction between the main rectangles is determined to be opposite, then the offset information is determined based on the cross-reference strategy; if the direction between the main rectangles is determined to be the same, then the offset information is determined based on the compactness priority strategy.

[0041] Specifically, if the directions between the main rectangles are found to be opposite, the offset information is determined based on a cross-reference strategy; if the directions between the main rectangles are found to be the same, the offset information is determined based on a compactness priority strategy. If the two main rectangles are opposite in direction, a cross-reference strategy is adopted, using the vertical rectangle to determine the X-axis offset and the horizontal rectangle to determine the Y-axis offset; if the directions are the same, a compactness priority strategy is adopted, selecting the rectangle with the smaller width or height to determine the offset Δx or Δy of the corresponding axis. The specific offset is calculated based on the relative position of the rectangle pins.

[0042] S205: Perform initial path planning based on the target topology information and access point planning information to obtain initial path information, and perform wire network allocation on the initial path information based on the cross relationship diagram to obtain initial path information after wire network allocation; In a specific implementation of this invention, the step of allocating wireframes based on the cross-connection graph to obtain the initial path information after wireframe allocation includes: analyzing the cross-connection information of the wireframes based on the initial path information, and constructing a cross-connection graph based on the cross-connection information; setting the network cross-connection degree based on the cross-connection graph, determining the Manhattan line length of the wireframes, and normalizing the network cross-connection degree and the Manhattan line length of the wireframes to obtain normalized network cross-connection degree and normalized Manhattan line length of the wireframes; determining the wireframe priority weight based on the normalized network cross-connection degree and normalized Manhattan line length of the wireframes; and allocating wireframes based on the wireframe priority weight to obtain the initial path information after wireframe allocation.

[0043] Furthermore, the expression for the network crossover degree is: , in, For network cross-section, Represents the i-th wire mesh. Describes the j-th wire mesh. This represents the k-th wire mesh; The expression for the wire priority weight is: , in, For net priority weights, To normalize the network crossover degree, The weight coefficients for normalized network crossover. To normalize the Manhattan line length, The weighting coefficients for the Manhattan line length of the normalized network.

[0044] Specifically, initial path planning is performed based on the target topology information and access point planning information to obtain initial path information. That is, the initial cabling path is obtained by connecting the pattern cabling according to the target topology information and access point planning information. Based on the initial path information, the crossover information of the network cabling is analyzed, and a crossover relationship graph is constructed based on the crossover information. The crossover situation of each network pattern cabling scheme is extracted according to the initial path information, and a corresponding crossover relationship graph is constructed accordingly. This graph is an undirected graph, where each node represents a network path, and each edge indicates that the two paths connected to it have a physical intersection on the projection plane.

[0045] Based on the aforementioned cross-connection diagram, a network cross-connection degree is set. This degree quantifies the degree of cross-connection conflict and the routing scale. The expression for the network cross-connection degree is: , in, For network cross-section, Represents the i-th wire mesh. Describes the j-th wire mesh. This represents the k-th wire mesh.

[0046] The Manhattan line length of the network is determined, and the network crossover degree and the Manhattan line length of the network are normalized to obtain normalized network crossover degree and normalized Manhattan line length. The normalization process is to eliminate the dimensional differences between different indicators.

[0047] The network priority weight is determined based on the normalized network crossover degree and the normalized network Manhattan line length. The expression for the network priority weight is as follows: , in, For net priority weights, To normalize the network crossover degree, The weight coefficients for normalized network crossover. To normalize the Manhattan line length, This is the weighting factor for the Manhattan line length of the normalized network. The weighting factor is used to balance the impact of crossover conflict and cabling scale.

[0048] Based on the net priority weights, nets are allocated to the initial path information to obtain the initial path information after net allocation. The nets in the initial path are then sorted in descending order according to the calculated priority weights, ensuring that high-priority nets located in conflict core areas or with large cabling scales can preferentially obtain high-quality lower-level cabling resources. According to the sorted net set, for each unallocated layer net, the lowest unoccupied layer number in its restricted layer set is selected for allocation, and the sets of all neighboring nets that cross-conflict with it are updated, thereby avoiding the risk of inter-layer short circuits. The final layer allocation result is output, i.e., the initial path information after net allocation. Prioritizing the planning of lower-level resources for high-conflict nets makes the overall structure compact and significantly reduces the number of unnecessary inter-layer vias. This optimization directly reduces parasitic resistance and capacitance on the path, ensures signal integrity, and reserves cabling space for subsequent higher-layer metals.

[0049] S206: Perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information; In a specific implementation of this invention, the step of performing 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information includes: setting a comprehensive cost function, the expression of which is: , in, For the comprehensive cost function, For the cost of the conductor, To cover the cost of turning, For through-hole cost, , , These are the weighting coefficients; Based on the comprehensive cost function, dynamic programming and priority queue mechanism are used to perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information.

[0050] Specifically, a comprehensive cost function is set, and the expression of the comprehensive cost function is as follows: , in, For the comprehensive cost function, For the cost of the conductor, To cover the cost of turning, For through-hole cost, , , The weighting coefficients are used to optimize the smoothness of the path by introducing turning costs; at the same time, by setting reasonable cross-layer via costs, a balance is achieved between reducing signal delay and manufacturing complexity, thereby encouraging the continuity of inter-layer switching paths.

[0051] Based on the comprehensive cost function, dynamic programming and a priority queue mechanism are used to perform 3D monotonic routing on the initial path information after net allocation to obtain 3D monotonic routing information. Combining dynamic programming and the priority queue mechanism, the optimal path is searched within the 3D mesh. During the search process, a priority queue driven by the comprehensive cost function is maintained to store candidate nodes to be expanded in real time. The specific search logic is as follows: State space initialization: A 3D tensor is constructed to store the minimum cost to reach each point, and a direction matrix is ​​used to record the predecessor node and movement type of the optimal path. Cost function driving: Whenever the node with the minimum cost is extracted from the queue, the algorithm strictly follows the monotonicity constraint of the path (i.e., the movement direction must face the quadrant of the destination), calculating the potential cost of expanding from the current node to the x, y, and z dimensions. Turning penalty and via optimization: To improve routing regularity, the algorithm introduces a turning penalty term in the state transition equation. If the current movement direction is inconsistent with the previous vector direction (e.g., changing from horizontal routing within a layer to inter-layer switching vias), an additional weight is added to the cost function. This mechanism forces the search algorithm to prioritize straight paths while maintaining monotonicity, effectively suppressing unnecessary detours. Backtracking and Restoration: When the search reaches the endpoint coordinates, the vector information recorded in the direction matrix is ​​used to iteratively backtrack from the endpoint to the starting point, ultimately generating a monotonic path with the shortest physical path and optimal signal quality in three-dimensional space. This method can more effectively satisfy design rule check constraints in congested areas, improving routing regularity and signal integrity. By combining dynamic programming and a priority queue mechanism, the algorithm can efficiently search for the optimal path from the starting point to the endpoint in three-dimensional space. Simultaneously, using the direction matrix to record path selection facilitates final path backtracking and restoration, significantly reducing the number of path detours and computational burden, thereby optimizing overall routing efficiency and quality.

[0052] The comparison diagram of the results of 3D monotonic routing processing and traditional routing processing in this embodiment of the invention is shown below. Figure 5 As shown in (a) and (c), traditional routing methods often result in multiple unnecessary bends in the path and a scattered distribution of vias due to the lack of an effective constraint mechanism. In contrast, the routing methods of the present invention, as shown in (b) and (d), result in a significantly more regular routing path and a significantly reduced number of vias, verifying the effectiveness of the method in optimizing routing quality.

[0053] S207: Regarding A The algorithm sets up an expansion buffer and a space pruning mechanism to obtain an improved A. Algorithm, to determine the improved A The cost function of the algorithm; In the specific implementation of this invention, A The algorithm sets up an expansion buffer and a space pruning mechanism to obtain an improved A. Algorithm, buffer modeling strategy. The expanded buffer strategy transforms complex design rule constraints into efficient rectangular overlap detection. Specifically, for any laid-out wire or via object... Its corresponding expansion buffer is defined as: , in, As an expansion buffer, Preset line width The minimum spacing is set. This strategy models the minimum via spacing within its own net. By pre-calculating this buffer, the algorithm detects overlaps between new wiring rectangles or vias and the expanded buffer during path search, thus quickly identifying potential physical conflicts and achieving real-time conflict avoidance.

[0054] The spatial pruning mechanism first constructs a diagonally expanded bounding box defined by the start and end points, and imposes a high cost penalty on nodes outside the box to reduce the invalid search area. If no feasible solution is found within the initial box, the system adaptively increases the expansion parameters for iterative searching, thereby achieving an optimal balance between computational efficiency and search completeness.

[0055] Determine the improvement A The cost function of the algorithm is expressed as follows:

[0056] in, Let g(n) be the cost function, representing the cumulative path cost from the starting point to the current node, and h(n) represent the path cost from the current node to the destination. It's the cost of turning a corner. A fast violation detection is achieved through a buffer expansion strategy. Used to limit the search range to accelerate convergence. It's the price of adding through-holes. These are the weighting coefficients.

[0057] S208: Based on the aforementioned 3D monotonic wiring information, utilize improved A The algorithm and cost function are used to enhance the routing process and obtain the target routing information of the analog integrated circuit.

[0058] In the specific implementation of this invention, based on the 3D monotonic wiring information, an improved A method is used. The algorithm and cost function are used to enhance routing processing, obtain the target routing information of the analog integrated circuit, and then improve the A... The algorithm and cost function further search the 3D monotonic routing information to obtain the final routing information. Enhanced routing processing, as a post-routing enhancement search module, is mainly used to handle remaining connections in local high-density areas and irregular topologies to ensure routing integrity. Improvement A The search mechanism of the algorithm is as follows Figure 6 As shown, this method explicitly integrates various physical design constraints, such as path turning, design rule checking, spatial pruning, and user guidance, into A. The algorithm significantly improves the reliability of pathfinding in complex map environments.

[0059] In this embodiment of the invention, layout file information of analog integrated circuits is obtained; a minimum spanning tree is constructed based on the layout file information; topology generation of the analog integrated circuit is performed based on the minimum spanning tree to obtain target topology information; access point planning is performed based on the target topology information; initial path planning is performed based on the target topology information and access point planning information; wire mesh allocation is performed on the initial path information based on the cross relationship graph to obtain initial path information after wire mesh allocation; 3D monotonic routing processing is performed on the initial path information after wire mesh allocation to eliminate the influence of routing conflicts, which can minimize the number of vias and reduce path parasitic resistance and capacitance. Based on the 3D monotonic routing information, A... The algorithm performs enhanced routing processing to obtain target routing information for analog integrated circuits, enabling reliable routing in complex layout environments and ensuring that the routing results comply with manufacturing process rules.

[0060] Example 3 Please see Figure 3 , Figure 3 This is a schematic diagram of the structural composition of a collision-aware automatic routing system for analog integrated circuits according to an embodiment of the present invention. The system includes: Topology generation module 31: used to obtain layout file information of analog integrated circuits, construct a minimum spanning tree based on the layout file information, generate the topology of analog integrated circuits based on the minimum spanning tree, and obtain target topology information; Access point planning module 32: used to perform access point planning processing based on the target topology information to obtain access point planning information; Network allocation module 33: used to perform initial path planning based on the target topology information and access point planning information to obtain initial path information, and to perform network allocation on the initial path information based on the cross relationship diagram to obtain initial path information after network allocation; Monotonic routing module 34: Used to perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information; Enhanced wiring module 35: used to utilize A based on the 3D monotonic wiring information The algorithm performs enhanced routing processing to obtain the target routing information for the analog integrated circuit.

[0061] In the specific implementation of this invention, the specific implementation methods of the system items can be referred to the implementation methods of the above-mentioned method items, and will not be repeated here.

[0062] In this embodiment of the invention, layout file information of analog integrated circuits is obtained; a minimum spanning tree is constructed based on the layout file information; topology generation of the analog integrated circuit is performed based on the minimum spanning tree to obtain target topology information; access point planning is performed based on the target topology information; initial path planning is performed based on the target topology information and access point planning information; wire mesh allocation is performed on the initial path information based on the cross relationship graph to obtain initial path information after wire mesh allocation; 3D monotonic routing processing is performed on the initial path information after wire mesh allocation to eliminate the influence of routing conflicts, which can minimize the number of vias and reduce path parasitic resistance and capacitance. Based on the 3D monotonic routing information, A... The algorithm performs enhanced routing processing to obtain target routing information for analog integrated circuits, enabling reliable routing in complex layout environments and ensuring that the routing results comply with manufacturing process rules.

[0063] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0064] Furthermore, the above provides a detailed description of a collision-aware automatic routing method and system for analog integrated circuits provided by the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A collision-aware automatic routing method for analog integrated circuits, characterized in that, The method includes: Obtain the layout file information of the analog integrated circuit, construct a minimum spanning tree based on the layout file information, generate the topology of the analog integrated circuit based on the minimum spanning tree, and obtain the target topology information; Based on the target topology information, access point planning processing is performed to obtain access point planning information; Initial path planning is performed based on the target topology information and access point planning information to obtain initial path information. Then, based on the cross relationship diagram, the initial path information is allocated to obtain the initial path information after the allocation of the network. Perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information; Based on the 3D monotonic wiring information, using A The algorithm performs enhanced routing processing to obtain the target routing information for the analog integrated circuit.

2. The collision-aware automatic routing method for analog integrated circuits according to claim 1, characterized in that, The step of constructing a minimum spanning tree based on the layout file information, and generating the topology of the analog integrated circuit based on the minimum spanning tree to obtain the target topology information includes: Based on the layout file information, extract the rectangular pin information of each device, calculate the horizontal and vertical gaps between the rectangular pin information, and calculate the Manhattan distance between the rectangular pins based on the horizontal and vertical gaps. Based on the Kruskal algorithm, a minimum spanning tree is constructed using the Manhattan distance combined with the disjoint-setup loop detection method; The underlying connections of the analog integrated circuit are determined based on the minimum spanning tree, and the target topology information of the analog integrated circuit is determined based on the underlying connections.

3. The collision-aware automatic routing method for analog integrated circuits according to claim 2, characterized in that, The expression for the horizontal gap is: ， in, For horizontal gaps, Let x be the x-coordinate of the lower left corner of the first rectangular pin. Let x be the x-coordinate of the upper right corner of the first rectangular pin. The x-coordinate of the lower left corner of the second rectangular pin is given. The x-coordinate of the upper right corner of the second rectangular pin; The expression for the vertical gap is: ， in, For vertical gaps, Let be the y-coordinate of the lower left corner of the first rectangular pin. Let be the y-coordinate of the upper right corner of the first rectangular pin. Let y be the y-coordinate of the lower left corner of the second rectangular pin. The y-coordinate of the upper right corner of the second rectangular pin; The expression for the Manhattan distance is: ， Where d is the Manhattan distance. For horizontal gaps, This is the vertical gap.

4. The collision-aware automatic routing method for analog integrated circuits according to claim 1, characterized in that, The access point planning process based on the target topology information to obtain access point planning information includes: Based on the target topology information, several main rectangles are determined using a preset rectangle multidimensional selection criterion; Analyze the direction between the main rectangles and determine the offset information based on the direction between the main rectangles; Candidate access points are generated based on the offset information, grid index intervals are determined, and coordinate sequence information of the candidate access points is determined based on the grid index intervals. Access point planning information is determined based on the coordinate sequence information of the candidate access points.

5. The collision-aware automatic routing method for analog integrated circuits according to claim 4, characterized in that, The offset information determined based on the direction between the main rectangles includes: If the analysis shows that the directions between the main rectangles are opposite, then the offset information is determined based on the cross-reference strategy; If the analysis shows that the directions between the main rectangles are in the same direction, then the offset information is determined based on the compactness priority strategy.

6. The collision-aware automatic routing method for analog integrated circuits according to claim 1, characterized in that, The step of performing net allocation on the initial path information based on the cross-relationship graph to obtain the initial path information after net allocation includes: Based on the initial path information, analyze the crossover information of the wire network wiring, and construct a crossover relationship diagram based on the crossover information; Based on the cross relationship diagram, the network cross degree is set, the Manhattan line length of the net is determined, and the network cross degree and the Manhattan line length of the net are normalized to obtain the normalized network cross degree and the normalized Manhattan line length of the net. The priority weight of the net is determined based on the normalized network crossover degree and the normalized net Manhattan line length. Based on the net priority weight, the initial path information is allocated nets to obtain the initial path information after net allocation.

7. The collision-aware automatic routing method for analog integrated circuits according to claim 6, characterized in that, The expression for the network crossover degree is: ， in, For network cross-section, Represents the i-th wire mesh. Describes the j-th wire mesh. This represents the k-th wire mesh; The expression for the wire priority weight is: ， in, For net priority weights, To normalize the network crossover degree, The weight coefficients for normalized network crossover. To normalize the Manhattan line length, The weighting coefficients for the Manhattan line length of the normalized network.

8. The collision-aware automatic routing method for analog integrated circuits according to claim 1, characterized in that, The initial path information after net allocation is processed using 3D monotonic routing to obtain 3D monotonic routing information, including: Set a comprehensive cost function, the expression of which is: ， in, For the comprehensive cost function, For the cost of the conductor, To cover the cost of turning, For through-hole cost, , , These are the weighting coefficients; Based on the comprehensive cost function, dynamic programming and priority queue mechanism are used to perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information.

9. The collision-aware automatic routing method for analog integrated circuits according to claim 1, characterized in that, The method based on the 3D monotonic wiring information utilizes A The algorithm performs enhanced routing processing to obtain the target routing information of the analog integrated circuit, including: For A The algorithm sets up an expansion buffer and a space pruning mechanism to obtain an improved A. Algorithm, to determine the improved A The cost function of the algorithm; Based on the aforementioned 3D monotonic wiring information, an improved A The algorithm and cost function are used to enhance the routing process and obtain the target routing information of the analog integrated circuit.

10. A collision-aware automatic routing system for analog integrated circuits, characterized in that, The system includes: Topology generation module: used to obtain the layout file information of the analog integrated circuit, construct a minimum spanning tree based on the layout file information, and generate the topology of the analog integrated circuit based on the minimum spanning tree to obtain the target topology information; Access point planning module: used to perform access point planning processing based on the target topology information to obtain access point planning information; Network allocation module: used to perform initial path planning based on the target topology information and access point planning information to obtain initial path information, and to perform network allocation based on the cross relationship diagram to obtain initial path information after network allocation; Monotonic routing module: Used to perform 3D monotonic routing processing on the initial path information after net allocation to obtain 3D monotonic routing information; Enhanced routing module: used to utilize A based on the 3D monotonic routing information. The algorithm performs enhanced routing processing to obtain the target routing information for the analog integrated circuit.

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