A data processing method of NAND flash memory
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN QUANHUIDA TECH CO LTD
- Filing Date
- 2026-03-09
- Publication Date
- 2026-06-09
Smart Images
Figure CN122177192A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of 3D flash memory technology, and particularly relates to a data processing method for NAND flash memory. Background Technology
[0002] In current enterprise-level storage system applications, vertical stacking architecture increases storage density by increasing the number of physical layers. The conventional approach is to use a preset read voltage to sense the physical pages and initiate a read retry mechanism when the original bit error rate exceeds the error correction threshold, attempting to recover data by adjusting the voltage offset in steps.
[0003] However, the deep-hole etching process for vertical channels has physical limitations, resulting in a geometric gradient in the physical aperture along the depth direction. This aperture difference causes objective deviations in the capacitance coupling ratio and transconductance characteristics of different memory cell layers. As the number of vertically stacked layers continues to increase, the morphological non-uniformity caused by deep-hole etching and the aging stress accumulated by erase-write cycles become deeply coupled. Because the tunneling oxide layer in the small aperture region experiences a higher local electric field intensity, the generation rate of interface state traps is significantly faster than in the large aperture region, causing the threshold voltage drift trajectory of different cell layers to exhibit nonlinear divergent characteristics. In addition to hardware morphological limitations, the compensation control method also has shortcomings, for example, as disclosed in publication number CN. Chinese invention patent application 115171760A discloses a method for sensing the block-level threshold voltage distribution of 3D NAND flash memory based on a marker layer. The scheme records the marker layer offline, which is close to the distribution of the entire block, simplifies the online sensing process and optimizes the read reference voltage. Although it reduces management overhead, it is still essentially a static mapping. Under dynamic conditions, the aging rate of small aperture regions is mismatched with that of large aperture regions. The non-uniformity of aging increment caused by geometric deformation cannot be covered by the marker layer sampling. When the device enters the middle and late stages of its life cycle, the level threshold voltage drift trajectory exhibits nonlinear divergence due to local electric field distortion. The marker layer fails, making it difficult to accurately align the drift trajectory of memory cells at each physical location.
[0004] Therefore, the technical problem to be solved by this invention is how to establish a dynamic compensation mechanism that can sense the local topographic distribution and couple spatial deformation and aging stress, so as to achieve accurate alignment of the threshold voltage drift trajectory of storage units in different physical locations. Summary of the Invention
[0005] This invention provides a data processing method for NAND flash memory, comprising the following steps: Step S1: Obtain the hierarchical index of the target word line and the erase / write cycle count value of the physical block to which the target word line belongs, wherein the hierarchical index is the physical position number of the target word line in the vertical stacking channel; Step S2: Extract the number of programming pulse cycles consumed when incremental step programming is performed on the top reference word line and the bottom reference word line during the initial lifetime stage of the physical block. The top reference word line and the bottom reference word line have a preset hierarchical interval along the vertical stacking channel direction. Step S3: Calculate the difference between the number of programming pulse cycles of the top reference word line and the number of programming pulse cycles of the bottom reference word line, and determine the deep hole geometry deformation deviation of the physical block based on the difference; Step S4: Extract the intrinsic electric field offset coefficient corresponding to the level index from the pre-stored level bias compensation table. The level bias compensation table records the threshold voltage deviation value caused by deep hole etching morphology corresponding to different level indices. Step S5: Correct the intrinsic electric field offset coefficient using the deep hole geometric deformation deviation to obtain the target electric field correction component, and generate the target word line read bias voltage based on the target electric field correction component and the erase / write cycle count value.
[0006] Preferably, step S3, which involves determining the deep hole geometric deformation deviation of the physical block, includes: calculating the arithmetic difference between the number of programming pulse cycles of the top reference word line and the number of programming pulse cycles of the bottom reference word line; comparing the arithmetic difference with the reference pulse difference stored in the memory to determine the geometric deviation ratio of the physical block relative to the standard deep hole morphology; and retrieving the corresponding value from the mapping database based on the geometric deviation ratio as the deep hole geometric deformation deviation.
[0007] Preferably, the step of establishing the hierarchical bias compensation table in step S4 includes: obtaining the tunneling oxide layer thickness of different levels of memory cells in the three-dimensional stacked structure under preset etching process parameters; establishing the electric field intensity mapping logic between the tunneling oxide layer thickness and the hierarchical index; and generating the intrinsic electric field offset coefficient corresponding to each hierarchical index based on the electric field intensity mapping logic.
[0008] Preferably, the logic for calculating the bias voltage in step S5 follows the following formula: ,in, For the generated read bias voltage, The preset base reading bias voltage is α, the intrinsic electric field offset coefficient is γ, the deep hole geometric deformation deviation is γ, and the preset aging offset slope constant is ω. This is the erase / write cycle count value.
[0009] Preferably, the top reference word line is located on the drain side of the physical block, and the bottom reference word line is located on the source side of the physical block.
[0010] Preferably, the process of generating the read bias voltage further includes: acquiring real-time temperature data of the current environment of the physical block; matching the corresponding temperature correction compensation factor based on the real-time temperature data; and using the temperature correction compensation factor to linearly correct the read bias voltage.
[0011] Preferably, the following subsequent steps are included: performing a sensing operation on the target word line using the read bias voltage, and statistically analyzing the original bit error rate generated by the sensing data; determining whether the original bit error rate is greater than a preset judgment threshold of 0.001; if the original bit error rate is greater than 0.001, calculating the deviation gradient between the original bit error rate and the preset judgment threshold, and updating the weighting factor of the deep hole geometric deformation deviation based on the deviation gradient.
[0012] Preferably, bit line grouping compensation is performed when calculating the read bias voltage, including: dividing the memory cell connected to the target word line into multiple bit line groups; calculating the physical offset distance of each bit line group relative to the central axis of the physical block, and determining the bit line offset compensation parameters; and fine-tuning the read bias voltage using the bit line offset compensation parameters.
[0013] Preferably, incremental step programming includes: performing charge injection using a pulse sequence with increasing amplitude when programming the memory cell; and performing programming verification after each pulse until the threshold voltage of the memory cell reaches a preset verification voltage.
[0014] Preferably, the read bias voltage is used as the starting read voltage and is loaded into the read retry sequence of the flash memory controller.
[0015] Compared with existing technologies, the NAND flash memory data processing method of the present invention has the following advantages: 1. In NAND flash memory data processing, establish the correlation between the physical index of the word line level of the storage cell and the local electric field intensity of the tunnel oxide layer, and transform the global erase / write cycle count into the local equivalent fatigue parameter corresponding to the specific level. This enables accurate compensation for the difference in aging rate of storage cells at different physical locations in the vertical channel, and eliminates the threshold voltage evolution deviation caused by the deep hole etching morphology.
[0016] 2. By using the difference in the number of pulse cycles during the programming process at the preset word line level as a probe to sense the actual aperture shrinkage rate of the physical block, the process dispersion generated during the manufacturing process is transformed into a quantifiable local topography scaling parameter, so that the generated read bias voltage can adaptively match the intrinsic geometric characteristics of each physical block, thereby improving the universality and accuracy of compensation for physical blocks at different physical locations.
[0017] 3. By leveraging the synergistic effect of the vertical spatial deformation physical mapping model and the electric field distortion coefficient, geometric deformation characteristics are introduced as an endogenous variable determining the trap generation rate into the aging response path. This avoids underfitting of read voltage compensation in memory cells located at extreme aperture positions during the later stages of the device's lifecycle, thus maintaining the physical sensing accuracy and data access latency stability of the memory array under high-concurrency read scenarios. Attached Figure Description
[0018] Figure 1 This is a data processing flowchart of the vertical aperture sensing and aging co-compensation of the present invention; Figure 2 This is a feature extraction and calibration logic block diagram for the geometric deformation deviation of the deep hole in the physical block according to the present invention. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.
[0020] It should be noted that all directional and positional terms used in this invention, such as: up, down, left, right, front, back, vertical, horizontal, inner, outer, top, bottom, transverse, longitudinal, center, etc., are only used to explain the relative positional relationship and connection between components in a specific state (as shown in the accompanying drawings). They are only for the convenience of describing this invention and do not require that this invention be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention. In addition, the descriptions of "first," "second," etc., in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated.
[0021] In the description of this invention, unless otherwise explicitly specified and limited, the terms installation, connection, and linking should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.
[0022] In the description of this specification, references to the terms "an embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example, and the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0023] A data processing method for NAND flash memory includes the following steps: Step S1: Obtain the hierarchical index of the target word line and the erase / write cycle count value of the physical block to which the target word line belongs, wherein the hierarchical index is the physical position number of the target word line in the vertical stacking channel; Step S2: Extract the number of programming pulse cycles consumed when incremental step programming is performed on the top reference word line and the bottom reference word line during the initial lifetime stage of the physical block. The top reference word line and the bottom reference word line have a preset hierarchical interval along the vertical stacking channel direction. Step S3: Calculate the difference between the number of programming pulse cycles of the top reference word line and the number of programming pulse cycles of the bottom reference word line, and determine the deep hole geometry deformation deviation of the physical block based on the difference; Step S4: Extract the intrinsic electric field offset coefficient corresponding to the level index from the pre-stored level bias compensation table. The level bias compensation table records the threshold voltage deviation value caused by deep hole etching morphology corresponding to different level indices. Step S5: Correct the intrinsic electric field offset coefficient using the deep hole geometric deformation deviation to obtain the target electric field correction component, and generate the target word line read bias voltage based on the target electric field correction component and the erase / write cycle count value.
[0024] Preferably, step S3, which involves determining the deep hole geometric deformation deviation of the physical block, includes: calculating the arithmetic difference between the number of programming pulse cycles of the top reference word line and the number of programming pulse cycles of the bottom reference word line; comparing the arithmetic difference with the reference pulse difference stored in the memory to determine the geometric deviation ratio of the physical block relative to the standard deep hole morphology; and retrieving the corresponding value from the mapping database based on the geometric deviation ratio as the deep hole geometric deformation deviation.
[0025] Preferably, the step of establishing the hierarchical bias compensation table in step S4 includes: obtaining the tunneling oxide layer thickness of different levels of memory cells in the three-dimensional stacked structure under preset etching process parameters; establishing the electric field intensity mapping logic between the tunneling oxide layer thickness and the hierarchical index; and generating the intrinsic electric field offset coefficient corresponding to each hierarchical index based on the electric field intensity mapping logic.
[0026] Preferably, the logic for calculating the bias voltage in step S5 follows the following formula: ,in, For the generated read bias voltage, The preset base reading bias voltage is α, the intrinsic electric field offset coefficient is γ, the deep hole geometric deformation deviation is γ, and the preset aging offset slope constant is ω. This is the erase / write cycle count value.
[0027] Preferably, the top reference word line is located on the drain side of the physical block, and the bottom reference word line is located on the source side of the physical block.
[0028] Preferably, the process of generating the read bias voltage further includes: acquiring real-time temperature data of the current environment of the physical block; matching the corresponding temperature correction compensation factor based on the real-time temperature data; and using the temperature correction compensation factor to linearly correct the read bias voltage.
[0029] Preferably, the following subsequent steps are included: performing a sensing operation on the target word line using the read bias voltage, and statistically analyzing the original bit error rate generated by the sensing data; determining whether the original bit error rate is greater than a preset judgment threshold of 0.001; if the original bit error rate is greater than 0.001, calculating the deviation gradient between the original bit error rate and the preset judgment threshold, and updating the weighting factor of the deep hole geometric deformation deviation based on the deviation gradient.
[0030] Preferably, bit line grouping compensation is performed when calculating the read bias voltage, including: dividing the memory cell connected to the target word line into multiple bit line groups; calculating the physical offset distance of each bit line group relative to the central axis of the physical block, and determining the bit line offset compensation parameters; and fine-tuning the read bias voltage using the bit line offset compensation parameters.
[0031] Preferably, incremental step programming includes: performing charge injection using a pulse sequence with increasing amplitude when programming the memory cell; and performing programming verification after each pulse until the threshold voltage of the memory cell reaches a preset verification voltage.
[0032] Preferably, the read bias voltage is used as the starting read voltage and is loaded into the read retry sequence of the flash memory controller.
[0033] Example 1: A data processing method for NAND flash memory is applied to a vertical NAND architecture solid-state drive array that supports mixed read and write operations. The vertical deep hole etching process causes the physical aperture to exhibit a geometric gradient scaling along the vertical channel depth direction. The curvature radius of the bottom storage cell is smaller than that of the top cell. The tunnel oxide layer of the bottom storage cell is subjected to a local electric field strength higher than that of the top cell, resulting in a higher interface state trap generation rate than that of the top cell. The spatial structural deformation and time aging stress coupling cause the threshold voltage drift trajectory of different levels of word lines in the physical block to exhibit divergent characteristics. The controller parses the received data read command, obtains the level index of the target word line and the erase / write cycle count value of the physical block to which it belongs. At the same time, the controller retrieves the timing record to extract the difference in the number of programming pulse cycles consumed when the physical block performs incremental step programming for the top reference word line and the bottom reference word line in the initial life stage. Based on this difference, the deep hole geometric deformation deviation of the physical block is calculated and determined.
[0034] The controller extracts the intrinsic electric field offset coefficient corresponding to the hierarchical index from the pre-stored hierarchical bias compensation table, corrects this intrinsic electric field offset coefficient using the deep hole geometric deformation deviation, calculates the target electric field correction component, and then generates the read bias voltage of the target word line based on the target electric field correction component and the erase / write cycle count value. The generation logic is based on the formula. Execution, in which For the generated read bias voltage, The preset base reading bias voltage is α, the intrinsic electric field offset coefficient is γ, the deep hole geometric deformation deviation is γ, and the preset aging offset slope constant is ω. To erase and write the cycle count value, the controller applies a generated read bias voltage to the target word line to perform a sensing operation. It calculates the original bit error rate generated by the sensing data and determines whether the original bit error rate falls back to a preset judgment threshold of less than 0.001. If the original bit error rate is detected to be in the out-of-limit range of 0.001 to 0.003, the controller triggers a gradient compensation program to calculate the difference between the original bit error rate and the threshold. It then finely adjusts the weight factor of the deep hole geometric deformation deviation upwards by a ratio of 0.02 weight increment for every 0.0005 error offset until the original bit error rate of the next sensing operation converges to below 0.001. The control logic, by coupling the deep hole geometric deformation deviation with the intrinsic electric field offset coefficient, transforms the temporal charge loss heterogeneity caused by three-dimensional spatial physical deformation into a one-dimensional local equivalent fatigue parameter compensation, thus offsetting the local threshold drift deviation caused by the physical aperture distribution.
[0035] Example 2: This example constructs a TLC flash memory chip test platform with a 128-layer vertical stacking architecture to verify the deep hole geometric deformation compensation mechanism. The test platform is equipped with a high and low temperature alternating test chamber with a temperature control accuracy of 0.5℃ and a signal acquisition module with a sampling frequency of 400MHz. The original threshold voltage distribution data collected comes from the physical probing of real silicon wafers under accelerated aging conditions. To simulate the signal-to-noise ratio degradation trend of enterprise-level solid-state drives under extreme conditions, the system actively adds random telegraph noise with an amplitude of 15mV and threshold broadening disturbance induced by cross-temperature retention stress to the physical probing link. The setting of the read voltage step value in the test platform needs to achieve a balance between sensing resolution and data processing latency. When the erase / write cycle count value of the physical block to which the target word line belongs approaches the end of its life, the threshold distribution intersection area of the storage cell expands. In order to maintain the hard decision decoding success rate of low-density parity check code, the control module drives the read voltage step value to approach the lower limit of the resolution supported by the hardware. The system selects 10mV as the preferred read voltage step parameter.
[0036] The experimental procedure selected three physical block groups with erase / write cycle counts of 1000, 3000, and 5000 to establish wear intensity evolution gradients. For each evolution gradient, comparative sample group 1, comparative sample group 2, and the present invention sample group were configured. Comparative sample group 1 generates the read voltage based solely on a fixed intrinsic electric field offset coefficient. Comparative sample group 2 outputs an overcompensated bias voltage using extreme deep hole geometric deformation deviations that deviate from a preset range. The present invention sample group extracts the number of programming pulse cycles consumed when the physical block performs incremental step programming for the top and bottom reference word lines during the initial lifetime stage. The timing log of the test platform shows that the top reference word line consumed 14 programming pulses and the bottom reference word line consumed 21 programming pulses. The system calculates the difference between the two and determines the deep hole geometric deformation deviation as 1.25. Under this wear evolution, the system extracts the electrical state of the target word line of the sample group of the present invention before and after being interfered with by random telegraph noise. The signal without processing by the method of the present invention shows a raw bit error rate of 0.008 after 3000 erase and write cycles. The system uses the deep hole geometric deformation deviation of 1.25 to correct the initial intrinsic electric field offset coefficient to obtain the target electric field correction component.
[0037] Based on the target electric field correction component and the erase / write cycle count, a read bias voltage is generated for the target word line. The system applies this read bias voltage to the target word line, causing the original bit error rate of the sample group of this invention to converge to 0.0012 under 3000 erase / write cycles. This data evolution shows nonlinear response characteristics. When the erase / write cycle count value jumps from 1000 to 3000, the original bit error rate of the first comparison sample group nonlinearly surges from 0.002 to 0.009, confirming that the static curing parameters fail during the aging stage due to the inability to perceive the amplification of local electric field distortion caused by aperture shrinkage. When the second comparison sample group applies an extreme deep aperture geometric deformation deviation of 2.5, its original bit error rate deteriorates under all erase / write cycle gradients and exceeds the hardware error correction limit of 0.015. This indicates that the overcompensation operation deviating from the physical aperture scaling ratio drives the read window to move out of the core area of the unit threshold distribution, resulting in reverse misreading. The experimental data supports the deep aperture geometric deformation... The deviation is maintained within the range of 0.8 to 1.5, forming the preferred working window. Comprehensive test indicators confirm that the correction calculation of the intrinsic electric field offset coefficient and the deep hole geometric deformation deviation has a synergistic effect in dealing with the vertical physical deformation of the 3D flash memory. The comparison sample without dynamic adjustment of the deep hole geometric deformation deviation only maintains sensing performance in the low wear stage. The sample of this invention calculates the deep hole geometric deformation deviation based on the programming pulse difference and corrects the intrinsic electric field offset coefficient. The generated read bias voltage dynamically matches the composite nonlinear drift trajectory of 3D spatial distortion and time wear. Under the high-intensity background disturbance condition of 5000 erase and write cycles, the read delay of the bottom target word line is still stably maintained within 85μs. This data processing method constructs a deterministic mathematical mapping between the physical shape deviation and the read voltage compensation of the target word line level index, verifying the engineering feasibility of using the bottom etching scattering parameters to suppress array aging distortion.
[0038] Example 3: During the factory initialization phase, the 3D flash array executes the hierarchical bias compensation table construction and deep hole geometric deformation deviation calibration process. The test equipment sends test commands to the physical blocks mounted on the wafer-level test platform and selects a preset set of sampling physical blocks. For each word line in the sampling physical block set, an incremental programming pulse sequence with an initial programming voltage of 14.0V and a step value of 0.2V is applied. The test equipment continuously monitors the total number of pulse cycles consumed when the threshold voltage of the memory cell connected to each word line crosses the verification level. The control unit summarizes the total number of pulse cycles of all sampled memory cells under the same level index and calculates the arithmetic mean. The arithmetic mean of the pulse cycles corresponding to the word line at the physical midpoint of the vertical stacking channel is extracted as the reference value. The control unit divides the arithmetic mean of the pulse cycles corresponding to each level index by the reference value to generate a set of dimensionless ratios characterizing the relative proportion of the local electric field strength. The controller uses the elements in the set of dimensionless ratios as intrinsic electric field offset coefficients and establishes an association with their corresponding level indexes. The associated data is written into the system reserved area of the flash array to form a hierarchical bias compensation table.
[0039] When calibrating the deep-hole geometric deformation deviation of a specific physical block, the controller addresses the first valid word line with the highest physical position within the target physical block as the top reference word line and the last valid word line with the lowest physical position as the bottom reference word line. The programming state machine inside the main control chip synchronously applies incremental step programming sequences to the top and bottom reference word lines and records the actual number of programming pulse cycles consumed to reach the target verification level for each. The arithmetic logic unit receives the number of programming pulse cycles and calculates the arithmetic difference between the number of programming pulse cycles for the top and bottom reference word lines. The arithmetic logic unit retrieves the reference pulse difference value generated by a standard deep-hole physical block under the same test conditions and stores it in memory, according to the formula... Calculate the geometric deviation ratio of the physical block relative to the standard deep hole morphology, where The geometric deviation ratio, The arithmetic difference of the actual number of programming pulse cycles for the target physical block. The system pre-stores a reference pulse difference value; the controller uses this geometric deviation ratio as an index parameter to input into the system's pre-set mapping database to perform a matching search, retrieves the corresponding discrete value, and extracts and outputs it as the deep hole geometric deformation deviation of the physical block; the system stores the extracted deep hole geometric deformation deviation as a calibration parameter for generating the read bias voltage in the subsequent lifecycle in static random access memory. This processing architecture converts the etching residence time distribution differences in the wafer-level manufacturing process into a numerical matrix for direct addressing operations by the underlying logic, suppresses parameter drift caused by the hardware physical aperture distribution on the dynamic adjustment of the read bias voltage, establishes a mapping correspondence between the three-dimensional spatial electric field distortion parameter and the morphological attributes of the specific physical block, and determines the deep hole geometric deformation deviation γ based on the channel curvature and tunneling electric field correlation model, selects a standard process node reference physical block, and measures the reference pulse difference value. The physical block under test obtains the arithmetic difference of the actual number of programming pulse loops through a programmed state machine. Calculate the geometric deviation ratio According to the linear transformation function Determine the deviation amount, the proportionality coefficient k, and the offset constant b through the threshold voltage of samples with different aperture sizes. The drift slope was obtained by least squares fitting. During the production testing phase, [the following will be implemented]. The correspondence between γ and γ is stored in a non-volatile memory lookup table in 0.05-step increments. The controller then... The closest γ value is retrieved for calculation.
[0040] Example 4: During the wafer packaging stage, the 3D flash memory array performs an offline calibration process based on algorithm benchmark construction. The test equipment applies accelerated erase and write stress to the sampled physical block and simultaneously injects high-temperature stress to induce interface charge trapping effect. When the erase and write cycle count value reaches the preset node, the device extracts the intrinsic threshold voltage offset of the word line corresponding to each level index. The control unit calculates the correlation characteristics between the local electric field distortion coefficient and the intrinsic threshold voltage offset. The arithmetic unit extracts the aging offset slope constant and uses the least squares method to fit it into a continuous polynomial and solidify it into the system read-only area. This offline calibration procedure converts the insulation layer degradation law into a constant matrix for the underlying control logic to call, so that the calculation of the read bias voltage is based on the objective physical aging state of the batch silicon wafers.
[0041] When the storage device is first deployed on the business server, a pre-debugging procedure for the basic read bias voltage is triggered. Before taking on the business load, the main control unit scans the reserved verification page of the storage space and obtains the current ambient temperature parameter. The error correction engine compares the initial bit error rate returned by the reserved verification page under the default state with the arithmetic deviation of the set tolerance. When it is determined that the arithmetic deviation is greater than the safety threshold, the main control unit adjusts the basic read bias voltage according to the ambient temperature parameter in a predetermined linear proportion until the initial bit error rate converges to the minimum error correction load range set by the underlying algorithm. The system locks the adjusted voltage value as the basic read bias voltage input for subsequent compensation formula calculations. This procedure suppresses the initial level drift caused by the temperature difference of the deployment environment and establishes the physical calculation starting point of the multi-dimensional parameter composite adjustment mechanism.
[0042] Example 5: During the wafer engineering calibration phase, the 3D flash memory array initiates a nonlinear trap generation response function coefficient construction procedure. The test system extracts a physical block sample set covering the entire hierarchical index from the wafer-level test platform. Periodic erase and write stresses spanning from the initial stage to the end of the design life are applied to this sample set. The test equipment interrupts the stress application at the preset erase and write cycle count frequency and collects the intrinsic threshold drift data of each word line level. The arithmetic logic unit receives the intrinsic threshold drift data and the corresponding local equivalent fatigue integral parameter and fits the curve, calculating and determining that the two follow a quadratic polynomial evolution law and according to the formula... Construct a nonlinear trap to generate a response function, where Let X be the output dynamic threshold drift, and let X be the input local equivalent fatigue integral parameter. This is the first-order aging drift coefficient. As the second-order accelerated decay coefficient, the main control chip stores the calculated first-order aging drift coefficient and second-order accelerated decay coefficient as constants in the system read-only memory, which can be directly addressed and called by the online read bias compensation logic.
[0043] After the solid-state drive is deployed in the business environment, the controller monitors the dynamic threshold drift output based on the response function generated by the nonlinear trap in real time. The control module compares the dynamic threshold drift with the preset limit compensation voltage threshold in the system register. When the absolute value of the calculated dynamic threshold drift is greater than the limit compensation voltage threshold, the arithmetic logic unit outputs an over-limit flag and triggers a hardware-level interrupt signal. The read scheduler receives the interrupt signal and blocks the downward path of the target read bias voltage. The system marks the physical page where the target word line is located as a high-risk state and activates the underlying data reset and relocation instruction. This boundary judgment procedure uses the dynamic threshold drift during operation as a physical medium degradation indicator, and blocks the sensing path and resets the data flow before the level offset exceeds the hardware compensation limit.
[0044] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit of this application and the scope of protection of this invention, and all of these forms are within the protection scope of this application.
Claims
1. A data processing method for NAND flash memory, characterized in that, Includes the following steps: Step S1: Obtain the hierarchical index of the target word line and the erase / write cycle count value of the physical block to which the target word line belongs, wherein the hierarchical index is the physical position number of the target word line in the vertical stacking channel; Step S2: Extract the number of programming pulse cycles consumed when incremental step programming is performed on the top reference word line and the bottom reference word line during the initial lifetime stage of the physical block. The top reference word line and the bottom reference word line have a preset hierarchical interval along the vertical stacking channel direction. Step S3: Calculate the difference between the number of programming pulse cycles of the top reference word line and the number of programming pulse cycles of the bottom reference word line, and determine the deep hole geometry deformation deviation of the physical block based on the difference; Step S4: Extract the intrinsic electric field offset coefficient corresponding to the level index from the pre-stored level bias compensation table. The level bias compensation table records the threshold voltage deviation value caused by deep hole etching morphology corresponding to different level indices. Step S5: Correct the intrinsic electric field offset coefficient using the deep hole geometric deformation deviation to obtain the target electric field correction component, and generate the target word line read bias voltage based on the target electric field correction component and the erase / write cycle count value.
2. The data processing method for NAND flash memory according to claim 1, characterized in that, The step of determining the deep hole geometric deformation deviation of the physical block in step S3 includes: calculating the arithmetic difference between the number of programming pulse cycles of the top reference word line and the number of programming pulse cycles of the bottom reference word line; comparing the arithmetic difference with the reference pulse difference pre-stored in the memory to determine the geometric deviation ratio of the physical block relative to the standard deep hole morphology; and retrieving the corresponding value from the mapping database according to the geometric deviation ratio as the deep hole geometric deformation deviation.
3. The data processing method for NAND flash memory according to claim 1, characterized in that, The steps for establishing the hierarchical bias compensation table in step S4 include: obtaining the tunneling oxide layer thickness of different levels of memory cells in the three-dimensional stacked structure under preset etching process parameters; establishing the electric field intensity mapping logic between the tunneling oxide layer thickness and the hierarchical index; and generating the intrinsic electric field offset coefficient corresponding to each hierarchical index based on the electric field intensity mapping logic.
4. The data processing method for NAND flash memory according to claim 1, characterized in that, The logic for calculating the bias voltage in step S5 follows the following formula: ,in, For the generated read bias voltage, The preset base reading bias voltage is α, the intrinsic electric field offset coefficient is γ, the deep hole geometric deformation deviation is γ, and the preset aging offset slope constant is ω. This is the erase / write cycle count value.
5. The data processing method for NAND flash memory according to claim 1, characterized in that, The top reference word line is located on the drain side of the physical block, and the bottom reference word line is located on the source side of the physical block.
6. The data processing method for NAND flash memory according to claim 1, characterized in that, The process of generating the read bias voltage also includes: acquiring real-time temperature data of the current environment of the physical block; matching the corresponding temperature correction compensation factor based on the real-time temperature data; and using the temperature correction compensation factor to linearly correct the read bias voltage.
7. The data processing method for NAND flash memory according to claim 1, characterized in that, The following follow-up steps are included: performing a sensing operation on the target word line using the read bias voltage, and calculating the raw bit error rate generated by the sensing data; determining whether the raw bit error rate is greater than a preset judgment threshold of 0.
001. If the original bit error rate is greater than 0.001, the deviation gradient between the original bit error rate and the preset judgment threshold is calculated, and the weight factor of the deep hole geometric deformation deviation is updated according to the deviation gradient.
8. The data processing method for NAND flash memory according to claim 1, characterized in that, When calculating the read bias voltage, bit line grouping compensation is performed, including: dividing the memory cell connected to the target word line into multiple bit line groups; calculating the physical offset distance of each bit line group relative to the physical block center axis, and determining the bit line offset compensation parameters; and using the bit line offset compensation parameters to fine-tune the read bias voltage.
9. A data processing method for NAND flash memory according to claim 1, characterized in that, Incremental step programming includes: performing charge injection using a pulse sequence with increasing amplitude when programming the memory cell; performing programming verification after each pulse until the threshold voltage of the memory cell reaches a preset verification voltage.
10. A data processing method for NAND flash memory according to claim 1, characterized in that, The read bias voltage, used as the starting read voltage, is loaded into the read retry sequence of the flash controller.