Static random access memory retention static noise margin measurement method, device, medium, terminal and program product

Abstract

The application provides a static random access memory static noise margin measurement method, device, medium, terminal and program product, the method comprises the following steps: preprocessing the original data of the obtained wafer acceptance test, obtaining the forward Q point voltage and the forward QB point voltage with corresponding relationship and the reverse QB point voltage and the reverse Q point voltage with corresponding relationship; based on the preset ratio, the forward Q point voltage and the reverse QB point voltage are respectively processed by interpolation, and the corresponding forward QB point voltage and reverse Q point voltage are calculated based on the interpolation function; two Bezier curves are respectively created in the same coordinate system, and the intersection of the two is calculated; the maximum square in the two closed regions is respectively scanned by using the diagonal line algorithm of 45°, and the corresponding left static noise margin value and right static noise margin value are calculated. The application can automatically, efficiently and accurately measure the static noise margin value, and improve the precision and efficiency of the SRAM stability test.

Description

Technical Field

[0001] This application relates to the field of static storage technology, and in particular to a method, apparatus, medium, terminal and program product for measuring static noise tolerance of static random access memory. Background Technology

[0002] Static Random Access Memory (SRAM) is a critical embedded storage module in integrated circuits, and its stability directly affects the performance and reliability of the entire chip. During SRAM design verification and production testing, Hold Static Noise Margin (HSNM) is an important indicator for evaluating the noise immunity of memory cells in the hold state.

[0003] Currently, simulation software or general-purpose plotting tools are commonly used to process and graphically analyze the raw test data obtained from Wafer Acceptance Test (WAT), plotting the voltage transfer characteristic curves of SRAM cells. A maximum possible square is constructed within the plot, and the side lengths of the left and right sides of this square are defined as the SRAM HSNML Value (left hold static noise margin) and the SRAM HSNMR Value (right hold static noise margin), respectively, thereby quantifying the stability performance of the memory cell under different hold conditions. This analysis provides important guidance for optimizing SRAM cell design and improving product yield and reliability.

[0004] However, existing simulation software or general plotting tools require manually importing massive amounts of test data, plotting voltage transfer curves point by point, and then manually searching for and plotting the largest inscribed square in the closed region of the curve. This process is time-consuming and laborious, with low plotting efficiency. Furthermore, the determination of the largest inscribed square relies on the engineer's experience, making it difficult to ensure the accuracy of the final SRAM HSNML Value and SRAM HSNMR Value.

[0005] Therefore, it is necessary to provide a method, apparatus, medium, terminal, and program product for measuring the static noise tolerance of static random access memory to solve the above-mentioned problems existing in the prior art. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method, apparatus, medium, terminal and program product for measuring the static noise tolerance of static random access memory, so as to solve the technical problems of low drawing efficiency and low accuracy in obtaining static noise tolerance values ​​in the prior art.

[0007] To achieve the above and other related objectives, a first aspect of this application provides a method for measuring the static noise tolerance of a static random access memory (SRAM), comprising: acquiring raw data from wafer acceptance testing; preprocessing the acquired raw data to obtain corresponding forward Q-point voltages and forward QB-point voltages, as well as corresponding reverse QB-point voltages and reverse Q-point voltages, for each test site; interpolating the forward Q-point voltage and reverse QB-point voltage for each test site based on a preset multiplier; and calculating the corresponding forward Q-point voltage based on the interpolated forward Q-point voltage and reverse QB-point voltage using an interpolation function. The voltage at point B and the reverse voltage at point Q are used to create a first Bézier curve and a second Bézier curve in the same coordinate system based on the forward voltage at point Q and the forward voltage at point QB, and the reverse voltage at point QB and the reverse voltage at point QB, respectively. The intersection of the first Bézier curve and the second Bézier curve is calculated. Using the 45° diagonal algorithm, the largest square in the first closed region and the second closed region of each test point is obtained by scanning based on the intersection of the first Bézier curve and the second Bézier curve. The side lengths of the first and second largest squares are calculated to obtain the corresponding left hold static noise margin and right hold static noise margin values.

[0008] In some embodiments of the first aspect of this application, the step of interpolating the forward Q-point voltage and reverse QB-point voltage of each test site based on a preset multiplier, and calculating the corresponding forward QB-point voltage and reverse Q-point voltage based on the interpolated forward Q-point voltage and reverse QB-point voltage using an interpolation function, specifically includes: generating equally spaced forward Q-point voltages and reverse QB-point voltages for each test site based on a predefined linspace function; constructing a first interpolation function and a second interpolation function based on the preprocessed forward Q-point voltages and forward QB-point voltages with corresponding relationships, and the corresponding reverse QB-point voltages and reverse Q-point voltages using the interp1d function interpolation method; calculating the corresponding forward QB-point voltage based on the generated equally spaced forward Q-point voltages using the first interpolation function, and calculating the corresponding reverse Q-point voltage based on the generated equally spaced reverse QB-point voltages using the second interpolation function.

[0009] In some embodiments of the first aspect of this application, both the first interpolation function and the second interpolation function are cubic spline interpolation functions.

[0010] In some embodiments of the first aspect of this application, the method of using the 45° diagonal algorithm to scan the first closed region and the second closed region of each test point based on the intersection of the first Bézier curve and the second Bézier curve to obtain the largest square within each region, and calculating the side length of the first and second largest squares to obtain the corresponding left-preserving static noise tolerance value and right-preserving static noise tolerance value, specifically includes: generating an offset sequence along the 45° diagonal direction from the intersection of the first and second Bézier curves based on the predefined np.diff and np.cumsum functions; detecting the intersection of the 45° diagonal with the first and second Bézier curves in the first and second closed regions based on the predefined np.sign function, and calculating the diagonal length; updating the maximum diagonal length in the first and second closed regions in real time, and calculating the side length of the first and second largest squares based on the updated maximum diagonal length to obtain the corresponding left-preserving static noise tolerance value and right-preserving static noise tolerance value.

[0011] In some embodiments of the first aspect of this application, the specific process of preprocessing the acquired raw data includes: extracting test data of each test site of any test bond in any wafer under the same test voltage from the raw data; organizing the test data of each test site into forward scan data and reverse scan data corresponding to the data point; the forward scan data includes forward Q-point voltage and forward QB-point voltage with corresponding relationship; the reverse scan data includes reverse QB-point voltage and reverse Q-point voltage with corresponding relationship; converting the long data format forward Q-point voltage, forward QB-point voltage, reverse QB-point voltage and reverse Q-point voltage into wide data format forward Q-point voltage, forward QB-point voltage, reverse QB-point voltage and reverse Q-point voltage, and saving them in sequence.

[0012] In some embodiments of the first aspect of this application, the intersect method of the Curve object in the bezier library is called to calculate the intersection point of the first Bézier curve and the second Bézier curve, and the coordinates of the intersection point are obtained.

[0013] To achieve the above and other related objectives, a second aspect of this application provides a static noise tolerance measurement device for a static random access memory, comprising:

[0014] The data preprocessing module is used to acquire the raw data of the wafer acceptance test and preprocess the acquired raw data to obtain the corresponding forward Q point voltage and forward QB point voltage, as well as the corresponding reverse QB point voltage and reverse Q point voltage for each test site.

[0015] The interpolation module is used to interpolate the forward Q-point voltage and reverse QB-point voltage of each test site based on a preset multiplier, and to calculate the corresponding forward QB-point voltage and reverse Q-point voltage based on the interpolation function and the forward Q-point voltage and reverse QB-point voltage obtained by the interpolation process.

[0016] The curve construction module is used to create a first Bézier curve and a second Bézier curve in the same coordinate system based on the forward Q-point voltage and the forward QB-point voltage, and the reverse QB-point voltage and the reverse Q-point voltage, respectively, and to calculate the intersection point of the first Bézier curve and the second Bézier curve.

[0017] The static noise tolerance calculation module is used to scan the first closed region and the second closed region of each test site according to the intersection of the first Bézier curve and the second Bézier curve using the 45° diagonal algorithm, and calculate the side length of the first maximum square and the side length of the second maximum square to obtain the corresponding left static noise tolerance value and right static noise tolerance value.

[0018] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method.

[0019] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code that, when executed on a computer, causes the computer to implement the method.

[0020] To achieve the above and other related objectives, a fifth aspect of this application provides a computer device / apparatus / system / electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the method.

[0021] As described above, the static noise tolerance measurement method, apparatus, medium, terminal, and program product of this application for static random access memory have the following beneficial effects:

[0022] First, the raw data from the acquired wafer acceptance test is preprocessed to obtain the corresponding forward Q-point voltage and forward QB-point voltage, as well as the corresponding reverse QB-point voltage and reverse Q-point voltage for each test site. Then, based on a preset multiplier, the forward Q-point voltage and reverse QB-point voltage for each test site are interpolated, and the corresponding forward QB-point voltage and reverse Q-point voltage are calculated based on the interpolated forward Q-point voltage and reverse QB-point voltage using the interpolation function. Finally, based on the forward Q-point voltage and forward QB-point voltage, and the reverse QB-point voltage and reverse Q-point voltage, respectively... A first and second Bézier curve are created in a coordinate system, and the intersection of the first and second Bézier curves is calculated. Finally, using the 45° diagonal algorithm, the first closed region and the largest square within the second closed region of each test point are scanned according to the intersection of the first and second Bézier curves, and the side lengths of the first and second largest squares are calculated, which are the corresponding left hold static noise tolerance values ​​and right hold static noise tolerance values. This method can automatically, efficiently, and accurately measure hold static noise tolerance values, improving the accuracy and efficiency of SRAM stability testing. Attached Figure Description

[0023] Figure 1 The diagram shown is a flowchart illustrating a method for maintaining static noise tolerance measurement of a static random access memory according to an embodiment of this application.

[0024] Figure 2 The diagram shown illustrates the working principle of a static noise tolerance measurement method for a static random access memory in one embodiment of this application.

[0025] Figure 3 This is a schematic diagram showing some of the raw data from a wafer acceptance test in one embodiment of this application.

[0026] Figure 4 The diagram shown is a schematic diagram of partially wide data format data obtained after preprocessing the original data in one embodiment of this application.

[0027] Figure 5 The diagram shows a portion of the HSNML and HSNMR values ​​obtained by the static noise tolerance measurement method for a static random access memory in one embodiment of this application.

[0028] Figure 6 The diagram shown is a block diagram of a static noise tolerance measurement device for a static random access memory according to an embodiment of this application.

[0029] Figure 7 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application. Detailed Implementation

[0030] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0031] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" do not necessarily imply that they are different.

[0032] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0033] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0034] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0035] <1> Static Random Access Memory (SRAM) is a type of random access memory that retains its data as long as it is powered on, but loses it when the power is off. Its working principle is as follows: when writing data, a specific memory cell is selected by a row and column address decoder, and then the data is written; when reading data, the same decoder is used to select the memory cell, and then the data is read.

[0036] <2> Static Noise Margin (SNM): This is a key parameter for measuring the stability of a memory cell. SNM refers to the minimum DC noise voltage at which data flips within a memory cell. In the optimized design of memory cells, a larger SNM value indicates that the memory cell can withstand a larger DC noise voltage and that data flipping is more difficult. It represents the maximum DC noise level that a memory node can withstand. By analyzing the SNM value, the stability of SRAM can be evaluated.

[0037] <3> Hold Static Noise Margin (HSNM): This refers to the maximum tolerance that an SRAM memory cell can withstand without state flipping due to DC (static) noise interference occurring on the internal node while holding data.

[0038] <4> The linspace function is a MATLAB function used to generate equally spaced numerical values. It can generate a set of linearly equally spaced points within a specified range.

[0039] <5> The interp1d function interpolation method is a one-dimensional interpolation method provided by the SciPy library in Python. It is often used to construct continuous functions based on discrete data points to predict the values ​​of unknown points. It supports a variety of interpolation strategies, such as linear interpolation and cubic spline interpolation, and is suitable for scientific computing and data analysis.

[0040] <6> A Bezier curve is a mathematical parametric curve that generates a smooth curve using control points. It is mainly used in the field of two-dimensional graphic design. The curve is defined by four control points (start point, end point, and two intermediate points). The curvature can be adjusted by moving the control endpoints. It is commonly achieved using the pen tool in vector drawing software, such as Photoshop and CorelDraw.

[0041] <7> The `np.diff` function is a difference function in the NumPy library used to calculate the discrete differences between elements in an array. This function is mainly used for numerical data analysis, especially when processing time series data, where the difference operation can help identify the trend of data changes.

[0042] <8> The `np.cumsum` function is a function in the NumPy library used to calculate the cumulative sum of array elements. This function can calculate the cumulative value along a specified axis. If no axis is specified, the array is flattened before calculation by default.

[0043] <9> The `np.sign` function is a sign function in the NumPy library. It is a utility for getting the sign (positive or negative) of a number. This function returns an array with the same shape as the input array, containing the sign of each element: 1 for positive numbers, -1 for negative numbers, and 0 for zero.

[0044] To facilitate understanding of the embodiments of this application, in conjunction with Figure 1 and Figure 2 Detailed explanation. Figure 1 A flowchart illustrating a method for maintaining static noise tolerance measurement of a static random access memory according to an embodiment of the present invention is shown. Figure 2 This illustration shows a schematic diagram illustrating the working principle of a method for measuring the static noise tolerance of a static random access memory (SRAM) according to an embodiment of the present invention. The method for measuring the static noise tolerance of a SRAM in this embodiment includes the following steps:

[0045] Step S11: Obtain the raw data of the wafer acceptance test, and preprocess the obtained raw data to obtain the corresponding forward Q-point voltage and forward QB-point voltage, as well as the corresponding reverse QB-point voltage and reverse Q-point voltage for each test site.

[0046] By preprocessing the raw data from the acquired wafer acceptance tests, the original long data format is converted into a wide data format suitable for subsequent processing steps. This facilitates subsequent curve fitting and the calculation of static noise tolerance measurements. It should be understood that the long data format means that each measurement value of each observation object occupies one row, expanding vertically; the wide data format means that each observation object occupies one row, with different variable values ​​distributed across multiple columns, expanding horizontally.

[0047] In some embodiments of this application, the specific process of preprocessing the acquired raw data includes: extracting test data of each test site of any test bond in any wafer under the same test voltage from the raw data; organizing the test data of each test site into forward scan data and reverse scan data corresponding to the data points; the forward scan data includes forward Q-point voltage and forward QB-point voltage with corresponding relationships; the reverse scan data includes reverse QB-point voltage and reverse Q-point voltage with corresponding relationships; converting the long data format forward Q-point voltage, forward QB-point voltage, reverse QB-point voltage and reverse Q-point voltage into wide data format forward Q-point voltage, forward QB-point voltage, reverse QB-point voltage and reverse Q-point voltage, and saving them in sequence.

[0048] like Figure 3 and Figure 4 As shown, the original data contains the following information: a series of Q-point voltages and QB-point voltages obtained at each test site of a specific wafer number within a certain batch (lot) under the specified measurement conditions. First, the test data of each test site at the same test voltage is extracted from the original data file for any test key on any wafer, such as the test data for site1, site2, site3, site4, and site5. Then, the test data for each test site is organized into forward and reverse scan data corresponding to the data point, meaning each test site has two sets of data. Finally, the long data format forward Q-point voltage and forward QB-point voltage, as well as the reverse QB-point voltage and reverse Q-point voltage for each test site, are converted into a wide data format forward Q-point voltage (V). Q1 ), forward QB point voltage (V) QB1 ), reverse QB point voltage (V) QB2 ) and reverse Q-point voltage (V Q2 ),Right now Figure 4 The data format for each test site shown is as follows: site (number) V Q1 site (number) V QB1 site (number) V QB2 site (number) V Q2 The data is saved sequentially to a new file, with each column containing the corresponding specific values ​​as rows. This facilitates subsequent curve fitting and calculations to preserve static noise tolerance measurements. Figure 4 The demonstration imports and processes wide data formats; the specific processing steps are described below. It should be understood that the Q-point (storage node) is a data storage node within an SRAM memory cell; the QB-point (complementary storage node) is the complementary node to the Q-point and is always at the opposite voltage level to the Q-point.

[0049] Step S12: Based on the preset magnification, interpolate the forward Q-point voltage and reverse QB-point voltage of each test site, and calculate the corresponding forward QB-point voltage and reverse Q-point voltage based on the interpolation function and the forward Q-point voltage and reverse QB-point voltage obtained by the interpolation process.

[0050] By performing curve fitting interpolation on the forward Q-point voltage, forward QB-point voltage, reverse QB-point voltage, and reverse Q-point voltage, a smooth fitting curve coordinate point set (x1, y1) and (x2, y2) is obtained, which makes the interpolated curve provide a smooth transition between the original data points, and the fitted curve is smoother.

[0051] In some embodiments of this application, the process of interpolating the forward Q-point voltage and reverse QB-point voltage of each test site based on a preset multiplier, and calculating the corresponding forward QB-point voltage and reverse Q-point voltage based on the interpolated forward Q-point voltage and reverse QB-point voltage using an interpolation function, specifically includes: generating equally spaced forward Q-point voltages and reverse QB-point voltages for each test site based on a predefined linspace function; constructing a first interpolation function and a second interpolation function based on the preprocessed forward Q-point voltages and forward QB-point voltages with corresponding relationships, and the corresponding reverse QB-point voltages and reverse Q-point voltages using the interp1d function interpolation method; calculating the corresponding forward QB-point voltage based on the generated equally spaced forward Q-point voltages using the first interpolation function, and calculating the corresponding reverse Q-point voltage based on the generated equally spaced reverse QB-point voltages using the second interpolation function.

[0052] Specifically, the linspace function is used to measure the positive Q-point voltage (V) at each test site. Q1 value) and reverse QB point voltage value (V QB2The system generates equidistant sampling points with a preset multiplier, namely the forward Q-point voltage value (x1) and the reverse QB-point voltage value (x2). The interpolation function is used to interpolate the forward and reverse scan data for each test site, obtaining a first interpolation function f1 and a second interpolation function f2. Specifically, the first interpolation function f1 is constructed based on existing corresponding forward Q-point and forward QB-point voltages, and the second interpolation function f2 is constructed based on existing corresponding reverse QB-point and reverse Q-point voltages. The first interpolation function f1 is used to calculate the corresponding forward QB-point voltage (y1) for x1, and the second interpolation function f2 is used to calculate the corresponding reverse Q-point voltage (y2) for x2, thus obtaining the smooth fitting curve coordinate point set (x1, y1) and (x2, y2). It should be noted that the preset multiplier can be any specified suitable value, such as 100, 1000, etc.

[0053] In some embodiments of this application, both the first interpolation function and the second interpolation function are cubic spline interpolation functions. Using cubic spline interpolation ensures that the fitted curve is smooth and continuous, conforming to the continuous physical characteristics of SRAM, and avoiding false transitions caused by linear interpolation.

[0054] Step S13: Create a first Bézier curve and a second Bézier curve in the same coordinate system based on the forward Q-point voltage and the forward QB-point voltage, and the reverse QB-point voltage and the reverse Q-point voltage, respectively, and calculate the intersection point of the first Bézier curve and the second Bézier curve.

[0055] By creating a first and a second Bézier curve in the same coordinate system, a smooth butterfly-shaped curve is constructed. The intersection point of the two fitted curves is accurately obtained using the Bézier curve intersection algorithm, which provides boundary points for finding the largest inscribed square and facilitates the calculation of the left and right static noise tolerance values.

[0056] In some embodiments of this application, the intersect method of the Curve object in the bezier library is called to calculate the intersection point of the first Bézier curve and the second Bézier curve, and the coordinates of the intersection point are obtained.

[0057] Specifically, the `Curve` function from the `bezier` library is used to create Bézier curve objects for the coordinate point sets (x1, y1) and (x2, y2) obtained in step S12, respectively, and the resulting fitted curves are drawn, namely the first and second Bézier curves, which together form a butterfly-shaped smooth curve. It should be noted that since the Bézier curves need to be created in the same coordinate system, (x2, y2) needs to be transformed first to ensure that the horizontal axis represents the voltage at point Q and the vertical axis represents the voltage at point QB. Then, the `intersect` method of the `Curve` object in the `bezier` library is used to calculate the intersection point of the first and second Bézier curves, and the coordinates of this intersection point are obtained. For example, the intersection point located in the upper left region and the intersection point located in the lower right region are calculated, and the coordinates of these two intersection points are obtained. This means that the drawn graph contains a first closed region (located on the left) and a second closed region (located on the right).

[0058] Step S14: Using the 45° diagonal algorithm, scan the first closed region and the second closed region of each test point according to the intersection of the first Bézier curve and the second Bézier curve to obtain the largest square in each region. Calculate the side length of the first and second largest squares to obtain the corresponding left-preserving static noise tolerance value and right-preserving static noise tolerance value.

[0059] By using the 45° diagonal algorithm, the largest inscribed squares within the first and second closed regions are found. The side lengths of these two largest squares are then calculated, yielding the left-preserving static noise margin (HSNML value) and the right-preserving static noise margin (HSNMR value).

[0060] In some embodiments of this application, the method of using the 45° diagonal algorithm to scan the first closed region and the second closed region of each test point based on the intersection of the first Bézier curve and the second Bézier curve to obtain the largest square within each region, and calculating the side lengths of the first and second largest squares to obtain the corresponding left-preserving static noise tolerance and right-preserving static noise tolerance values, specifically includes: generating an offset sequence along the 45° diagonal direction from the intersection of the first and second Bézier curves based on the predefined np.diff and np.cumsum functions; detecting the intersections of the 45° diagonal with the first and second Bézier curves in the first and second closed regions based on the predefined np.sign function, and calculating the diagonal length; updating the maximum diagonal lengths in the first and second closed regions in real time, and calculating the side lengths of the first and second largest squares based on the updated maximum diagonal lengths to obtain the corresponding left-preserving static noise tolerance and right-preserving static noise tolerance values.

[0061] Specifically, an offset sequence is generated based on the predefined `np.diff` and `np.cumsum` functions to ensure the scanning offset distance of the 45° diagonal starting from the intersection of the first and second Bézier curves. The sign change of the `np.sign` function is used to detect the intersection positions of the 45° diagonal with the two Bézier curves in the left and right closed regions. The coordinates of the intersection points are stored, and the diagonal length is calculated. The maximum diagonal length records on the left and right curves are updated in real time, and the maximum square side lengths on the left and right curves are calculated from the maximum diagonal lengths. Specifically, the first maximum square side length on the left and the second maximum square side length on the right are calculated using the Pythagorean theorem. The first maximum square side length is the SRAM HSNML value, and the second maximum square side length is the SRAM HSNMR value. Thus, the SRAM HSNML and SRAM HSNMR values ​​for each test site are calculated, as follows: Figure 5 The output results show that the SRAM HSNM values ​​measured for each die are saved to an Excel spreadsheet file, enabling automated, accurate, and fast calculation of SRAM HSNM values. This method is promoted as a standard in practical work and improves the efficiency of static noise tolerance measurement.

[0062] Figure 6 This is a schematic block diagram of a static noise tolerance measurement device for a static random access memory provided in an embodiment of this application. Figure 6 As shown, the static noise tolerance measurement device 600 for static random access memory includes:

[0063] The data preprocessing module 601 is used to acquire the raw data of the wafer acceptance test and preprocess the acquired raw data to obtain the corresponding forward Q point voltage and forward QB point voltage and the corresponding reverse QB point voltage and reverse Q point voltage at each test site.

[0064] The interpolation processing module 602 is used to perform interpolation processing on the forward Q-point voltage and reverse QB-point voltage of each test site based on a preset multiplier, and to calculate the corresponding forward QB-point voltage and reverse Q-point voltage based on the interpolation function and the forward Q-point voltage and reverse QB-point voltage obtained by the interpolation processing.

[0065] The curve construction module 603 is used to create a first Bézier curve and a second Bézier curve in the same coordinate system based on the forward Q-point voltage and the forward QB-point voltage, and the reverse QB-point voltage and the reverse Q-point voltage, respectively, and to calculate the intersection point of the first Bézier curve and the second Bézier curve.

[0066] The static noise tolerance calculation module 604 is used to scan the first closed region and the second closed region of each test point according to the intersection of the first Bézier curve and the second Bézier curve using the 45° diagonal algorithm, and calculate the side length of the first maximum square and the side length of the second maximum square to obtain the corresponding left static noise tolerance value and right static noise tolerance value.

[0067] It should be understood that the specific process of each module performing the above-mentioned steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0068] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0069] Figure 7 This is a schematic block diagram of the electronic terminal provided in an embodiment of this application. Figure 7As shown, the electronic terminal 700 includes at least one processor 701, a memory 702, at least one network interface 703, and a user interface 705. The various components in the electronic terminal 700 are coupled together via a bus system 704. It is understood that the bus system 704 is used to implement communication between these components. In addition to a data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 7 The general will label all buses as bus systems.

[0070] The user interface 705 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0071] It is understood that memory 702 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0072] In this embodiment of the invention, the memory 702 is used to store various types of data to support the operation of the electronic terminal 700. Examples of this data include: any executable program for operation on the electronic terminal 700, such as operating system 7021 and application program 7022; operating system 7021 includes various system programs, such as framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. Application program 7022 may include various applications, such as media player, browser, etc., for implementing various application services. The methods provided in this embodiment of the invention can be included in application program 7022.

[0073] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by processor 701. Processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 701 or by instructions in software form. The processor 701 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 701 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 701 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0074] In an exemplary embodiment, the electronic terminal 700 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0075] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute... Figures 1 to 5 The method of any of the embodiments shown.

[0076] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when executed on a computer, causes the computer to perform... Figures 1 to 5 The method of any of the embodiments shown.

[0077] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0078] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0079] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0080] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0081] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0082] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0083] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0084] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0085] In summary, to address the problems of low efficiency and low accuracy in plotting static noise tolerance values ​​using existing technologies, this application provides a method, apparatus, medium, terminal, and program product for measuring static noise tolerance of static random access memory (SRAM). First, the raw data from the wafer acceptance test is preprocessed to obtain corresponding forward Q-point voltages and forward QB-point voltages, as well as corresponding reverse QB-point voltages and reverse Q-point voltages for each test site. Then, based on a preset multiplier, the forward Q-point voltage and reverse QB-point voltage for each test site are interpolated. Finally, based on the interpolation function, the corresponding forward QB-point voltage and reverse QB-point voltage are calculated. The process involves several steps: First, based on the forward Q-point voltage and the forward QB-point voltage, and the reverse QB-point voltage and the reverse Q-point voltage, a first Bézier curve and a second Bézier curve are created in the same coordinate system, and the intersection of the first and second Bézier curves is calculated. Finally, using a 45° diagonal algorithm, the first closed region and the largest square within the second closed region of each test point are scanned based on the intersection of the first and second Bézier curves. The side lengths of the first and second largest squares are then calculated, which correspond to the left hold static noise tolerance and the right hold static noise tolerance. This method enables automatic, efficient, and accurate measurement of hold static noise tolerance, improving the accuracy and efficiency of SRAM stability testing. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0086] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for measuring the static noise tolerance of a static random access memory, characterized in that, include: The raw data of wafer acceptance test is obtained and the raw data is preprocessed to obtain the corresponding forward Q point voltage and forward QB point voltage, as well as the corresponding reverse QB point voltage and reverse Q point voltage for each test site. Based on a preset multiplier, the forward Q-point voltage and reverse QB-point voltage of each test site are interpolated, and the corresponding forward QB-point voltage and reverse Q-point voltage are calculated based on the interpolation function and the forward Q-point voltage and reverse QB-point voltage obtained by the interpolation. Based on the forward Q-point voltage and the forward QB-point voltage, and the reverse QB-point voltage and the reverse Q-point voltage, respectively, create a first Bézier curve and a second Bézier curve in the same coordinate system, and calculate the intersection point of the first Bézier curve and the second Bézier curve. Using the 45° diagonal algorithm, the first closed region and the largest square within the second closed region of each test site are scanned based on the intersection of the first and second Bézier curves. The side lengths of the first and second largest squares are then calculated to obtain the corresponding left-hold static noise tolerance and right-hold static noise tolerance values.

2. The method for measuring the static noise tolerance of a static random access memory according to claim 1, characterized in that, The process involves interpolating the forward Q-point voltage and reverse QB-point voltage at each test site based on a preset multiplier, and then calculating the corresponding forward QB-point voltage and reverse Q-point voltage based on the interpolated forward Q-point voltage and reverse QB-point voltage using the interpolation function. The specific steps include: Based on the predefined linspace function, equally spaced positive Q-point voltages and reverse QB-point voltages are generated for the positive Q-point voltage and reverse QB-point voltage at each test site. Based on the interp1d function interpolation method, the first interpolation function and the second interpolation function are constructed respectively based on the preprocessed positive Q-point voltage and positive QB-point voltage with corresponding relationship and the inverse QB-point voltage and inverse Q-point voltage with corresponding relationship. The corresponding positive QB point voltage is calculated based on the generated equally spaced positive Q point voltages using the first interpolation function, and the corresponding reverse Q point voltage is calculated based on the generated equally spaced reverse QB point voltages using the second interpolation function.

3. The method for measuring the static noise tolerance of a static random access memory according to claim 2, characterized in that, Both the first interpolation function and the second interpolation function are cubic spline interpolation functions.

4. The method for measuring the static noise tolerance of a static random access memory according to claim 1, characterized in that, The method of using a 45° diagonal algorithm to scan the first and second closed regions of each test site based on the intersection of the first and second Bézier curves to obtain the largest square within each region, and calculating the side lengths of the first and second largest squares to obtain the corresponding left-hold static noise tolerance and right-hold static noise tolerance values, specifically includes: Based on the predefined np.diff and np.cumsum functions, an offset sequence is generated from the intersection of the first and second Bézier curves along a 45° diagonal direction; The predefined np.sign function is used to detect the intersection points of the 45° diagonal with the first Bézier curve and the second Bézier curve in the first closed region and the second closed region, respectively, and the length of the diagonal is calculated. The maximum diagonal lengths within the first and second closed regions are updated in real time, and the side lengths of the first and second maximum squares are calculated based on the updated maximum diagonal lengths to obtain the corresponding left-hold static noise tolerance and right-hold static noise tolerance values.

5. The method for measuring the static noise tolerance of a static random access memory according to claim 1, characterized in that, The specific process of preprocessing the acquired raw data includes: Extract the test data of each test site of any test bond in any wafer under the same test voltage from the raw data; The test data for each test site are organized into forward scan data and reverse scan data corresponding to the data points; the forward scan data includes forward Q-point voltage and forward QB-point voltage with corresponding relationships; the reverse scan data includes reverse QB-point voltage and reverse Q-point voltage with corresponding relationships. Convert the long data format of positive Q-point voltage, positive QB-point voltage, reverse QB-point voltage, and reverse Q-point voltage into wide data format of positive Q-point voltage, positive QB-point voltage, reverse QB-point voltage, and reverse Q-point voltage, and save them in sequence.

6. The method for measuring the static noise tolerance of a static random access memory according to claim 1, characterized in that, The `intersect` method of the `Curve` object in the `bezier` library is called to calculate the intersection point of the first and second Bézier curves and obtain the coordinates of the intersection point.

7. A device for measuring the static noise tolerance of a static random access memory, characterized in that, include: The data preprocessing module is used to acquire the raw data of the wafer acceptance test and preprocess the acquired raw data to obtain the corresponding forward Q point voltage and forward QB point voltage, as well as the corresponding reverse QB point voltage and reverse Q point voltage for each test site. The interpolation module is used to interpolate the forward Q-point voltage and reverse QB-point voltage of each test site based on a preset multiplier, and to calculate the corresponding forward QB-point voltage and reverse Q-point voltage based on the interpolation function and the forward Q-point voltage and reverse QB-point voltage obtained by the interpolation process. The curve construction module is used to create a first Bézier curve and a second Bézier curve in the same coordinate system based on the forward Q-point voltage and the forward QB-point voltage, and the reverse QB-point voltage and the reverse Q-point voltage, respectively, and to calculate the intersection point of the first Bézier curve and the second Bézier curve. The static noise tolerance calculation module is used to scan the first closed region and the second closed region of each test site according to the intersection of the first Bézier curve and the second Bézier curve using the 45° diagonal algorithm, and calculate the side length of the first maximum square and the side length of the second maximum square to obtain the corresponding left static noise tolerance value and right static noise tolerance value.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a computer, causes the computer to implement the method as described in any one of claims 1 to 6.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method as described in any one of claims 1 to 6.

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