A battery-powered atomic clock level high-precision distributed synchronous trigger system and method for an FRC fusion device

Abstract

The application discloses a battery-powered atomic clock level high-precision distributed synchronous trigger system and method for an FRC fusion device. The system takes a central atomic clock as a global time base, distributes PPS and 10MHz reference clocks to each distributed trigger board through an optical fiber network and an equal-length star-shaped backboard. The FPGA of the board is frequency-multiplied through a phase-locked loop and combined with a phase offset technology to realize 3.3ns pulse resolution and <=30ns system synchronization accuracy. The system adopts a commercial power / battery dual-mode floating ground isolation power supply and a full-fiber interface design to eliminate high-voltage interference. The system can send a pre-trigger signal to a data acquisition system, invert the plasma shape based on a magnetic probe and automatically correct the timing parameters to form a closed-loop iterative optimization. A single machine box can be expanded to 320 trigger channels to meet the needs of large-scale FRC devices.

Description

Technical Field

[0001] This invention relates to the fields of magnetic inertial confinement fusion control and electronic engineering technology, specifically to a battery-powered atomic clock-level high-precision distributed synchronous triggering system and method for FRC fusion devices. Background Technology

[0002] In field-inverse configuration (FRC) magnetic inertial confinement fusion experiments, the generation, acceleration, and compression of FRC plasma depend on a specific magnetic field configuration generated by hundreds of magnet coils surrounding the device. These magnet coils are driven by independent pulsed power supplies and must discharge sequentially with nanosecond-level precision according to a preset timing sequence in order to propel the plasma along the expected trajectory and maintain stability.

[0003] Existing technologies face the following challenges: 1. Insufficient timing control precision: The FRC process is extremely fast (microsecond level), requiring extremely high timing control precision. Excessive triggering errors in each power supply can lead to magnetic field distortion, causing plasma instability or even collisions with the walls, resulting in serious equipment damage. Existing industrial-grade PLCs or ordinary triggers cannot meet the nanosecond-level resolution requirements.

[0004] 2. High-voltage interference and ground loop risk: FRC discharge generates extremely high transient voltages and strong electromagnetic interference. If traditional triggering systems use mains power or cable connections, they are prone to forming ground loops, introducing high-voltage spikes that can damage the control circuit or cause false triggering.

[0005] 3. Difficulty in system scalability: As the device is upgraded, the number of channels needs to be expanded to thousands. Traditional centralized triggering wiring is complex, and long-distance transmission can lead to uncontrollable signal delays.

[0006] 4. Lack of closed-loop optimization mechanism: Existing triggering systems are usually "open-loop", that is, they only output according to the set time and cannot automatically adjust the timing of the next shot according to the actual plasma configuration of the previous shot experiment.

[0007] Therefore, there is an urgent need for a synchronous triggering solution that can overcome the above-mentioned defects and provide FRC fusion devices with high precision, high safety, easy expansion and intelligent feedback capabilities. Summary of the Invention

[0008] The present invention aims to solve the problems of low timing control accuracy, poor anti-interference ability, difficulty in ensuring synchronization, and inability to dynamically adjust timing based on experimental results in large-scale pulse power supply in FRC devices.

[0009] To achieve the above objectives, the present invention provides a battery-powered atomic clock-level high-precision distributed synchronization triggering system for FRC fusion devices, comprising: A central atomic clock is used to provide PPS second pulses and a 10MHz reference signal as a global time base; Multiple distributed trigger chassis are located in different positions of the device. Each trigger chassis is equipped with a trigger backplane and at least one trigger board. The fiber optic network connects the central atomic clock to the backplane of each trigger chassis, and is used to distribute the PPS second pulse and 10MHz reference signal to each trigger chassis. The trigger backplane is used to distribute the received clock signal to each trigger board through star-shaped equal-length wiring; The trigger board is implemented based on an FPGA. The FPGA uses a phase-locked loop to multiply the 10MHz reference clock and combines a counter and phase offset technology to generate trigger pulse edges with a resolution of 3.3ns. The synchronization error between all trigger signals in the distributed trigger chassis is ≤30ns.

[0010] Furthermore, the system also includes an isolated power supply module that switches between mains power and battery power: in standby mode, the system is powered by mains power and charges the battery pack; before the experiment begins, the mains power input is physically cut off, and the system automatically switches to pure battery power supply mode, so that the system is completely electrically isolated from the power grid and the ground.

[0011] Furthermore, the operating logic of the isolated power supply module with dual-mode switching between mains power and battery power includes: Idle phase: The relay is closed, and the battery pack is powered by the mains. Preparation phase: After receiving the instruction from the host computer, the relay disconnects the mains power input, and the system automatically switches to pure battery power and enters a fully isolated floating ground state; Triggering phase: The system executes timing output tasks under battery power; Recovery phase: After the mission is completed, the relay closes again, restoring mains power supply.

[0012] Furthermore, all external interfaces of the system are fiber optic interfaces, including control signal interfaces, synchronization signal interfaces, and trigger pulse output interfaces; the output optical trigger signal directly drives the optical receiver of the pulse power supply, realizing physical isolation between high-voltage and low-voltage electricity.

[0013] Furthermore, the system also works in collaboration with the data acquisition system as the main control unit: before triggering the pulse power supply, the system sends a pre-trigger signal to the data acquisition system through optical fiber to start the acquisition; after the data acquisition system acquires the magnetic probe or magnetic flux loop signal, the host computer inverts the plasma configuration and calculates the corrected timing parameters based on the configuration deviation, and updates them to the triggering system to form a closed-loop optimization.

[0014] Furthermore, the trigger backplane of a single trigger chassis integrates 10 board slots, a single trigger board provides 32 fiber optic output interfaces, and a single trigger chassis can provide 320 trigger signals when fully loaded; multiple trigger chassis are cascaded to the central atomic clock through a fiber optic network to expand the number of channels.

[0015] The present invention also provides a high-precision distributed synchronization triggering method for the above-mentioned system, comprising the following steps: S1. Using an atomic clock as the sole time base, the PPS second pulse and 10MHz reference signal are distributed to the backplane of each distributed trigger chassis via an optical fiber network, and then distributed from the backplane to each trigger board. S2. Inside the FPGA of the trigger board, a phase-locked loop is used to multiply the 10MHz reference clock, and a trigger pulse with a resolution of 3.3ns is generated through a high-speed counter and phase offset technology; S3. Before the experiment is triggered, physically disconnect the mains power supply and switch to pure battery power supply mode to put the system in a floating ground isolation state; S4. Send a pre-trigger signal to the data acquisition system via optical fiber to start the acquisition window; S5. Output optical trigger pulses to each pulse power supply through optical fiber according to a preset timing sequence; S6. After the data acquisition system acquires the magnetic probe or magnetic flux loop signal, the host computer inverts the plasma configuration and compares it with the target configuration to calculate the timing correction for the next shot. S7. The corrected timing parameters are reissued to the triggering system to form a closed-loop adaptive optimization.

[0016] Furthermore, the specific steps for generating a 3.3ns resolution trigger pulse using the FPGA include: multiplying a 10MHz reference frequency to over 300MHz as a counting clock, using a counter to achieve a coarse delay, and then fine-tuning the edge of the trigger pulse in 3.3ns steps using phase shifting technology.

[0017] Furthermore, in the pure battery power mode, the system immediately disconnects the mains relay after receiving the experimental preparation command, and maintains battery power until the entire discharge sequence is completed. After completion, it automatically switches back to mains power and charges the battery.

[0018] Furthermore, the host computer inverts the plasma configuration based on the magnetic probe and / or flux loop signals acquired by the data acquisition system, compares the actual configuration parameters obtained by inversion with the preset target configuration, calculates the delay correction amount of each trigger channel, and automatically sends it to the FPGA register of the trigger system.

[0019] The beneficial effects of this invention are as follows: 1. Extremely high timing control capability: 3.3ns resolution and ≤30ns system synchronization accuracy ensure the perfect generation of FRC magnetic field configuration and greatly improve the success rate of experiments.

[0020] 2. Ultimate safety: The combination of battery power and full fiber optic interface fundamentally eliminates the risks of high voltage backlash and electromagnetic interference, protecting expensive control equipment.

[0021] 3. Flexible scalability: The distributed architecture based on backplane and fiber optics can be easily expanded to thousands of channels to adapt to the control needs of different locations of FRC devices.

[0022] 4. Intelligent experimental iteration: By combining data acquisition and magnetic inversion feedback, the experimental parameters are automatically optimized iteratively. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the triggering system architecture in an embodiment of the present invention.

[0024] Figure 2 This is a flowchart of the method for triggering the system in an embodiment of the present invention.

[0025] Reference numerals: 1. Central atomic clock; 2. Fiber optic network; 3. Trigger backplane; 4. Trigger board; 5. Distributed trigger chassis. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. Those skilled in the art should understand that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0027] Example 1

[0028] This embodiment provides a battery-powered atomic clock-level high-precision distributed synchronous triggering system for FRC fusion devices.

[0029] Reference Figure 1 (Some repeated content has been omitted) This system mainly includes: a central atomic clock 1, multiple distributed trigger chassis 5, and a full fiber optic network 2 connecting the above components.

[0030] Central Atomic Clock 1: Serving as the globally unique time base for the entire system, it generates and provides a highly stable, low-drift PPS (pulse per second) and a 10MHz reference signal. This signal is the reference for time synchronization and pulse generation in all trigger chassis.

[0031] Distributed Trigger Chassis 5: Based on the spatial layout of the FRC device, multiple trigger chassis are distributed among the various control cabinets surrounding the device. Each trigger chassis integrates a trigger backplane and multiple trigger boards.

[0032] Trigger Backplane 3: Each trigger chassis contains a passive or active backplane. The backplane receives optical signals from the central atomic clock via a fiber optic input interface and converts them into PPS and a 10MHz clock signal in the electrical domain. Subsequently, the backplane distributes these two clock signals simultaneously and with high precision to all card slots on the backplane using a star-shaped equal-length wiring configuration. The star-shaped equal-length design ensures that the transmission delay of the clock signals reaching each slot is essentially the same, laying the foundation for synchronization between the cards within the chassis.

[0033] Trigger Board 4: Each trigger board can be inserted into a slot on the backplane. At the heart of the board is a high-performance FPGA (Field-Programmable Gate Array). Each trigger board provides 32 fiber optic output interfaces for independently controlling 32 pulse power supplies. In a typical chassis configuration, a single backplane can integrate 10 board slots, thus a single trigger chassis can provide 320 trigger signals at full load.

[0034] Fiber Optic Network 2: All clock signals, control commands, and trigger pulses are transmitted via fiber optic media. The central atomic clock is connected to the backplane of each distributed trigger chassis via fiber optic cables. Each trigger chassis has 10 integrated card slots on its backplane, with each trigger card providing 32 fiber optic output interfaces, thus a single chassis can provide 320 trigger signals at full load. As the scale of the FRC device increases, multiple trigger chassis can be cascaded to the same central atomic clock via a fiber optic network. The number of chassis can be increased indefinitely according to actual control channel requirements, easily covering the control points of thousands of magnet coils around the device, while each new chassis maintains nanosecond-level synchronization accuracy with the atomic clock.

[0035] To achieve nanosecond-level fine control of the FRC magnetic field configuration, this system implements a 3.3ns resolution trigger pulse edge adjustment function within the FPGA of the trigger board. The specific implementation steps are as follows: The dedicated clock management unit inside the FPGA, specifically a digital phase-locked loop (PLL), receives a 10MHz reference clock from the backplane. The PLL performs high-rate multiplication on this reference clock to generate a high-speed synchronous clock with a frequency of over 300MHz. This high-speed clock serves as the reference counting clock for all subsequent sequential logic, and its period determines the basic step size of the system's coarse delay.

[0036] In addition, a high-precision counter is implemented internally within the FPGA. Upon receiving the synchronization start signal, the counter begins counting at a high-speed clock frequency (e.g., 300MHz, corresponding to a period of approximately 3.3ns). By comparing a preset delay parameter with the current count value, coarse-grained positioning of the trigger pulse output timing can be achieved.

[0037] To further improve resolution, the FPGA utilizes its internal output phase offset technology. Within one clock cycle before and after the coarse delay counter reaches its preset value, the phase of the output signal is finely adjusted to achieve sub-clock-cycle-level fine-tuning of the rising or falling edge of the trigger pulse. Combined with a frequency multiplier clock of 300MHz or higher, this technology ultimately enables the system to continuously adjust the output timing of the trigger pulse in 3.3ns steps.

[0038] Through the aforementioned three-level distribution architecture of "atomic clock-fiber optic cable-backplane", combined with the equal-length wiring design of the backplane and the synchronization logic calibration inside the FPGA, the synchronization error between thousands of trigger signals in the entire distributed system is strictly controlled within 30ns.

[0039] Example 2

[0040] Based on Example 1, this embodiment further defines the isolated power supply and safety interface design of the system to solve the risks of high voltage interference and ground loop during FRC discharge.

[0041] 1. Dual-mode isolated power supply with AC / battery switching

[0042] Each distributed trigger chassis integrates an intelligent power management module, which is responsible for managing the switching between AC power and battery power. Its working logic can be described in the following four consecutive stages: Idle Phase: During non-experimental periods, the power management module controls the relay to close, connecting the AC 220V mains input. At this time, the system is in a low-power standby state, with the mains power supply providing power to the control circuits inside the chassis (such as the backplane, FPGA, etc.). Simultaneously, the built-in charging circuit automatically charges the battery pack with constant current / constant voltage until the battery is fully charged.

[0043] Preparation Phase: After the host computer issues the experimental preparation command, the power management module first confirms that the system status is normal, and then immediately disconnects the relay at the AC 220V input terminal. At this time, the AC 220V power supply is physically cut off. Simultaneously with or within a very short time after the relay disconnects, the power management module seamlessly switches to the battery power supply path. From this point on, the system is completely powered by the battery pack, entering a "true floating ground" state, meaning that complete DC isolation is achieved between the system's signal ground and the grid's protective ground.

[0044] Triggering Phase: In battery-powered floating state, the system receives a trigger command from the host computer and executes a high-precision trigger pulse output task according to a preset timing sequence. During this process, since it is completely disconnected from the power grid, the ground potential rise caused by FRC discharge or any interference transmitted through the ground wire cannot affect the control system.

[0045] Recovery Phase: After a complete discharge sequence is executed and the on-site environment is confirmed to be safe, the power management module receives a command from the host computer to reclose the AC 220V power relay, restoring AC 220V power supply. The system switches back to AC power mode and immediately begins recharging the battery power consumed in this experiment, preparing for the next experiment.

[0046] 2. All-fiber intrinsic security interface

[0047] To achieve complete electrical isolation, all external electrical interfaces of this system have been replaced with fiber optic interfaces. Specifically, this includes: Synchronization signal interface: PPS and 10MHz synchronization signals are transmitted via optical fiber between the central atomic clock and the backplane of the trigger chassis, as well as between chassis.

[0048] Communication control interface: The communication links between the host computer and each trigger chassis, such as parameter transmission and status feedback, also adopt fiber optic connections.

[0049] Trigger Output Interface: Each trigger board has 32 outputs, all of which are fiber optic interfaces. The output optical trigger pulse signal is directly connected to the optical receiver module inside the pulse power supply. The optical receiver module converts the optical signal into an electrical signal, which then drives the final stage power circuit.

[0050] Through the above design, all signal paths in the control system are transmitted optically, with no direct electrical connections via copper wires. This fundamentally cuts off the path for high-voltage components to interfere with or damage low-voltage control components through conduction, achieving "intrinsic safety."

[0051] Example 3

[0052] Based on the above system, this embodiment provides a high-precision distributed synchronization triggering method, including the following steps: S1. Clock Distribution: Using an atomic clock as the sole time base, the PPS second pulse and 10MHz reference signal are distributed to the backplane of each distributed trigger chassis via a fiber optic network, and then distributed to each trigger board via star-shaped equal-length wiring from the backplane.

[0053] S2. High-precision pulse generation: Inside the FPGA of the trigger board, a phase-locked loop is used to multiply the 10MHz reference clock, and a trigger pulse with a resolution of 3.3ns is generated through a high-speed counter and phase offset technology.

[0054] S3. Battery isolation power supply switching: Before the experiment is triggered, the mains power supply is physically disconnected and switched to pure battery power supply mode, so that the system is in a floating ground isolation state.

[0055] S4. Acquisition Pre-trigger: Send a pre-trigger signal to the data acquisition system via optical fiber to start the acquisition window.

[0056] S5. Power Trigger: Outputs optical trigger pulses to each pulse power supply via optical fiber according to a preset timing sequence.

[0057] S6. Inversion and Deviation Calculation: After the data acquisition system acquires the magnetic probe or magnetic flux loop signal, the host computer inverts the plasma configuration and compares it with the target configuration to calculate the timing correction for the next shot.

[0058] S7. Closed-loop update: The corrected timing parameters are reissued to the triggering system to form a closed-loop adaptive optimization.

[0059] In step S2, the specific steps for generating a 3.3ns resolution trigger pulse inside the FPGA of the trigger board are as follows: The phase-locked loop (PLL) inside the S21.FPGA receives a 10MHz reference clock from the backplane and multiplies it to over 300MHz. This high-frequency clock serves as the reference clock for subsequent counting and timing control, with a period of approximately 3.3ns.

[0060] The S22.FPGA internally incorporates a high-speed counter that counts at a frequency of 300MHz or higher after frequency multiplication. Coarse-grained delay control of the trigger pulse is achieved by comparing a preset delay parameter with the current count value.

[0061] S23. Based on coarse delay counting, the phase shifting technology inside the FPGA is further utilized to perform fine adjustment of the output edge of the trigger pulse at the sub-clock cycle level. By adjusting the phase of the output signal, delay fine-tuning with a step size of 3.3ns can be achieved.

[0062] S24. By combining coarse delay with phase fine-tuning, a trigger pulse edge with a resolution of 3.3ns is finally generated, realizing high-precision trigger control of the pulse power supply.

[0063] In step S6, the specific method by which the host computer inverts the plasma configuration is as follows: S61. The data acquisition system acquires the measurement signals of the magnetic probe and / or flux loop during the experiment.

[0064] S62. Based on these signals, the host computer calculates the actual plasma configuration parameters of this discharge using an inversion algorithm.

[0065] S63. Compare the actual configuration parameters obtained by inversion with the preset target configuration parameters point by point, and analyze the direction and magnitude of the deviation.

[0066] S64. Based on the deviation, automatically calculate the delay correction amount required for each trigger channel in the next experiment.

[0067] S65. The calculated delay correction (or the corrected complete timing parameters) is automatically sent to the FPGA register of the triggering system to overwrite the original configuration and wait for the next experiment to be executed.

[0068] The beneficial effects of this invention are as follows: 1. Extremely high timing control capability: 3.3ns resolution and ≤30ns system synchronization accuracy ensure the perfect generation of FRC magnetic field configuration and greatly improve the success rate of experiments.

[0069] 2. Ultimate safety: The combination of battery power and full fiber optic interface fundamentally eliminates the risks of high voltage backlash and electromagnetic interference, protecting expensive control equipment.

[0070] 3. Flexible scalability: The distributed architecture based on backplane and fiber optics can be easily expanded to thousands of channels to adapt to the control needs of different locations of FRC devices.

[0071] 4. Intelligent experimental iteration: By combining data acquisition and magnetic inversion feedback, the experimental parameters are automatically optimized iteratively.

[0072] The embodiments described above are merely further illustrations of the present invention and are not intended to limit the present invention in any other way. The present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding modifications and changes based on the present invention, but all such modifications and changes should fall within the protection scope of the present invention.

Claims

1. A battery-powered atomic clock-level high-precision distributed synchronous triggering system for an FRC fusion device, characterized in that, include: A central atomic clock is used to provide PPS second pulses and a 10MHz reference signal as a global time base; Multiple distributed trigger chassis are located in different positions of the device. Each trigger chassis is equipped with a trigger backplane and at least one trigger board. An optical fiber network connects the central atomic clock to the backplane of each trigger chassis, and is used to distribute the PPS second pulse and 10MHz reference signal to each trigger chassis. The trigger backplane is used to distribute the received clock signal to each trigger board through star-shaped equal-length wiring; The trigger board is implemented based on an FPGA. The FPGA uses a phase-locked loop to multiply the 10MHz reference clock and combines a counter and phase offset technology to generate a trigger pulse edge with a resolution of 3.3ns. The synchronization error between all trigger signals of the distributed trigger chassis is ≤30ns.

2. The system according to claim 1, characterized in that, It also includes an isolated power supply module that switches between mains power and battery power: in standby mode, the system is powered by mains power and charges the battery pack; before the experiment begins, the mains power input is physically cut off, and the system automatically switches to pure battery power supply mode, so that the system is completely electrically isolated from the power grid and the ground.

3. The system according to claim 2, characterized in that, The operating logic of the isolated power supply module with dual-mode switching between mains power and battery power includes: Idle phase: The relay closes, power is supplied from the mains and the battery pack is charged; Preparation phase: After receiving the instruction from the host computer, the relay disconnects the mains power input, and the system automatically switches to pure battery power and enters a fully isolated floating ground state; Triggering phase: The system executes timing output tasks under battery power; Recovery phase: After the mission is completed, the relay closes again, restoring mains power supply.

4. The system according to claim 1, characterized in that, All external interfaces of the system are fiber optic interfaces, including control signal interfaces, synchronization signal interfaces, and trigger pulse output interfaces; the output optical trigger signal directly drives the optical receiver of the pulse power supply, realizing physical isolation between high voltage and low voltage.

5. The system according to claim 1, characterized in that, The system also works in conjunction with the data acquisition system as a main control unit: before triggering the pulse power supply, the system sends a pre-trigger signal to the data acquisition system through an optical fiber to start the acquisition; after the data acquisition system acquires the magnetic probe or magnetic flux loop signal, the host computer inverts the plasma configuration and calculates the corrected timing parameters based on the configuration deviation, and updates them to the triggering system to form a closed-loop optimization.

6. The system according to claim 1, characterized in that, A single trigger chassis integrates 10 board slots on the trigger backplane, and a single trigger board provides 32 fiber optic output interfaces. A single trigger chassis can provide 320 trigger signals when fully loaded. Multiple trigger chassis are cascaded to the central atomic clock via a fiber optic network to expand the number of channels.

7. A high-precision distributed synchronization triggering method based on the system according to any one of claims 1 to 6, characterized in that, Includes the following steps: S1. Using an atomic clock as the sole time base, the PPS second pulse and 10MHz reference signal are distributed to the backplane of each distributed trigger chassis via an optical fiber network, and then distributed from the backplane to each trigger board. S2. Inside the FPGA of the trigger board, a phase-locked loop is used to multiply the 10MHz reference clock, and a trigger pulse with a resolution of 3.3ns is generated through a high-speed counter and phase offset technology; S3. Before the experiment is triggered, physically disconnect the mains power supply and switch to pure battery power supply mode to put the system in a floating ground isolation state; S4. Send a pre-trigger signal to the data acquisition system via optical fiber to start the acquisition window; S5. Output optical trigger pulses to each pulse power supply through optical fiber according to a preset timing sequence; S6. After the data acquisition system acquires the magnetic probe or magnetic flux loop signal, the host computer inverts the plasma configuration and compares it with the target configuration to calculate the timing correction for the next shot. S7. The corrected timing parameters are reissued to the triggering system to form a closed-loop adaptive optimization.

8. The method according to claim 7, characterized in that, The specific steps for the FPGA to generate a 3.3ns resolution trigger pulse include: multiplying a 10MHz reference frequency to over 300MHz as a counting clock, using a counter to achieve a coarse delay, and then fine-tuning the edge of the trigger pulse in 3.3ns steps using phase offset technology.

9. The method according to claim 7, characterized in that, In the mode of switching to pure battery power, the system immediately disconnects the mains relay after receiving the experimental preparation command, maintains battery power until the entire discharge sequence is completed, and automatically switches back to mains power and charges the battery after completion.

10. The method according to claim 7, characterized in that, The host computer inverts the plasma configuration based on the magnetic probe and / or magnetic flux loop signals acquired by the data acquisition system, compares the actual configuration parameters obtained by inversion with the preset target configuration, calculates the delay correction amount of each trigger channel, and automatically sends it to the FPGA register of the trigger system.

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