Power conversion system

Abstract

A power conversion system (1) comprising a power converter (2) having three-phase modules (22), each module connected in direct current to two input nodes (211, 212) and in three-phase alternating current to a single respective output node (213). Each phase module (22) comprises controllable switches (23) and a flying capacitor (223). A control system (3) sends logic control signals to the switches (23) generated for the phase modules (22) from three-phase modulation signals (V m ). The phase modulation signals (V m ) are generated using DPWM techniques, adding generated unipolar signals to three sinusoidal phase signals (V sin ) so that the phase modulation signals (V m ) reach saturation at higher or lower end values in different intervals. In each interval, the modulation signal (V f ) to be saturated is selected to minimize the combination of circulating currents (I 223 ) in the flying capacitors (223) of the three-phase modules (22).

Description

Technical Field

[0001] This invention was developed in the field of power converters, particularly for connecting photovoltaic (PV) or battery energy storage (BESS) systems to a three-phase power grid. More specifically, this invention relates to a DPWM (Discontinuous Pulse Width Modulation) control technique to minimize stress in the converter capacitors. Background Technology

[0002] In photovoltaic or BESS power generation applications, the power converter must be connected to the DC bus via DC power on the photovoltaic panel or battery side and connected to a three-phase system such as the power grid.

[0003] A known example of a converter that represents a good compromise between multiple switches and capacitors is represented by a flying capacitor multilevel topology (or flying capacitor), specifically with three output voltage levels.

[0004] PWM (Pulse Width Modulation) control technology is a known technique in the art for power converter switches, applicable to various types of converters, including the one described herein. The switch then receives a logic control signal given by a square wave pulse sequence, in which logic high and logic low states alternate. These logic states correspond to the switch being open and closed.

[0005] The width of these pulses determines how long current will pass through or not through the switch, and during this period a certain voltage level is obtained at the output. The pulse width is determined by comparing a carrier signal with a specific switching period (e.g., a sawtooth wave or a triangular wave) with a sinusoidal modulated signal with a specific fundamental period that is longer than the switching period.

[0006] As is well known, due to this technique, although the output voltage is a sequence of a finite set of discrete voltage levels (e.g., three voltage levels: maximum, minimum, and zero), by applying appropriate filters and / or considering the average value of the output signal over appropriate time, the output voltage approximates the sinusoidal waveform of the modulated signal.

[0007] As a development of PWM technology, a technique called DPWM or discontinuous PWM is also known.

[0008] DPWM technology is commonly used to reduce switching losses in switches. Specifically, a region is chosen where the loss is assumed to be at its maximum during the fundamental period, for example, where the output phase voltage will approach the peak of the sine wave. Within such a region, the sinusoidal modulation signal is saturated, i.e., flattened to a constant value, which is either the maximum or minimum value. In this region, the modulation signal no longer intersects with the carrier wave; therefore, the switch controlled by the comparator remains in its on or off state for the entire duration of this region. This reduces switching losses.

[0009] In a three-phase system, it is preferable not to change the modulation of a single phase, as this would result in changes to the three-phase currents and thus alter the system's operation. Conversely, it is known that if the change required for saturation is introduced into all three phases as a component of the same polarity, the three-phase currents do not change relative to the purely sinusoidal case. Therefore, in each interval where saturation occurs in one of the three-phase modulation signals, the modulation signals of the other two phases will also deviate from a sinusoidal waveform, although they will not reach saturation.

[0010] To maximize the duration of these cycles, the saturation interval is 60°, so that each phase saturates twice at both the maximum and minimum values ​​within the fundamental cycle (360°).

[0011] US 7391181 shows an example of DPWM control, where the saturation range can be changed according to the power factor.

[0012] Problems in the technical background

[0013] In a three-level flying capacitor topology, the most expensive component is typically the flying capacitor itself. The capacitor's dimensions must be designed to ensure that the RMS current circulating within it does not exceed a specific voltage ripple value. Therefore, minimizing the RMS current flowing through the capacitor is desirable. Summary of the Invention

[0014] The purpose of this invention is to address the problems in the known art by limiting the current in the capacitors of power converters (especially flying capacitors), thereby allowing for less stringent dimensional designs.

[0015] This and other objectives are achieved by an electric power conversion system according to any one of the appended claims.

[0016] The present invention provides a converter with three-phase modules, each module being provided with a flying capacitor.

[0017] The control system employs DPWM technology to generate logic control signals for the converter switches, while utilizing a homopolar component. This component is obtained by minimizing the combination of circulating currents in the flying capacitors (preferably minimizing the sum of the squares of these currents or minimizing their root mean square sum). The homopolar component causes one of the three-phase modulation signals to saturate within each interval, thus making it a flat-top modulation signal within that interval.

[0018] Then, within each interval, the optimal flat-top modulation signal is selected from the three-phase modulation signals, such as realizing the proposed minimized signal within the interval.

[0019] This creates saturation regions, which can typically be offset relative to the peak values ​​of the voltage and sinusoidal current, and can have different durations. Therefore, the final modulated signal differs significantly from the modulated signal obtained from existing DPWM techniques, but the goal remains the same: to reduce switching losses. The choice of saturation regions, and which phase of the modulated signal should be saturated each time, is typically based on the phase shift between the voltage and current.

[0020] The applicant specifically pointed out that the most critical situation occurs when the reference phase duty cycle is close to 0.5, i.e., when the output phase voltage is close to 0. Therefore, the control strategy tends to primarily avoid or temporarily limit the occurrence of a phase modulation signal duty cycle close to 0.5 while simultaneously having a high phase current.

[0021] Advantageously, by minimizing the circulating current in the capacitor within each interval, the thermal effects of the current in the flying capacitor can be reduced, even when current intensity and phase shift are most critical, thus significantly reducing the size design of the flying capacitor. Attached Figure Description

[0022] To better understand the following detailed description, some embodiments of the invention are illustrated in the accompanying drawings, wherein:

[0023] - Figure 1 A power conversion system according to an embodiment of the present invention is illustrated schematically.

[0024] - Figure 2 schematically shown Figure 1 The phase module of the converter in the power conversion system, and the dedicated control system.

[0025] - Figure 3 The following is a time-varying graph showing an example of the circulating current of the phase module's switch and the flying capacitor during the switching cycle.

[0026] - Figure 4 The figure shows the time curves of two sets of theoretically modulated signals for three phases, assuming either always maximum saturation or always minimum saturation.

[0027] - Figure 5 The graph shows the phase coefficient, phase current, and circulating current in the flying capacitor as a function of the reference phase duty cycle, with a power factor of 1.

[0028] - Figure 6 The following graphs show the time curves of the sinusoidal phase signal, phase current, and phase modulation signal when the power factor is 1.

[0029] - Figure 7 and Figure 8This shows the corresponding case where the power factor is equal to 0. Figure 5 and Figure 6 The time curve, and

[0030] - Figure 9 and Figure 10 The diagram shows the corresponding value when the power factor is 0.7. Figure 5 and Figure 6 The time curve graph. Detailed Implementation

[0031] The power conversion system generally indicated by number 1 includes a power converter 2 and a control system 3 for controlling the operation of the converter 2 (only in...). Figure 2 (This is shown as a single phase).

[0032] The power converter 2 includes two input nodes 211 and 212, which are a positive node 211 and a negative node 212. Input nodes 211 and 212 can be connected to a DC bus. The DC bus is preferably connected to a photovoltaic (PV) system (not shown) and / or an energy storage system (not shown), such as a battery energy storage system (BESS). The DC bus can optionally be connected to a bus capacitor, which is different from the bus capacitor described below as a flying capacitor.

[0033] The two input nodes 211 and 212 are configured to be opposite to each other and their modulus is equal to the reference voltage value V. dc The system operates using two voltages. Therefore, the total voltage between the positive input node 211 and the negative input node 212 is the reference voltage 2V. dc Twice that. The DC bus may or may not have a grounding point, for example, between the two halves of the bus capacitor at zero potential.

[0034] The power converter 2 also includes three output nodes 213, which can be connected to the three corresponding AC phase conductors of the three-phase system. For simplicity, it will be assumed below that the AC current exchanged between the converter 2 and the three-phase system is direct-sequence, substantially sinusoidal, and has a constant amplitude. Therefore, on a predetermined fundamental period, the three currents will be 120° out of phase with each other. However, it should be noted that the control system 3, which will be described, can also be adapted during current transients without significant changes to operation, where the current is not precisely sinusoidal, thus achieving substantially the same advantageous effect.

[0035] The converter 2 includes a three-phase module 22, one of each phase conductor in the three-phase system. All three-phase modules 22 are connected to two input nodes 211, 212. In addition, each phase module 22 is connected to one and only one corresponding output node 213, which is different from the output nodes 213 connected to the other phase modules 22.

[0036] Each phase module 22 includes multiple controllable switches 23 that connect input nodes 211, 212 and output node 213. The controllable switches 23 are, in particular, transistors configured to operate in two states: an on (or off) state and an off (or open) state. Each switch 23 is configured to switch between these two on states based on appropriately received control signals.

[0037] As is common in many converters 2, it is also desirable for each switch 23 to be provided with a freewheeling diode in parallel. Furthermore, each of the described switches 23 can actually be identified by several switches 23 connected in series with each other, which share the same current.

[0038] In a preferred embodiment, the converter 2 is a converter of the type called a flying capacitor converter. In such an embodiment, each phase module 22 includes a pair of bridge arms 221, each bridge arm connecting between the output node 213 connected to the phase module 22 and a corresponding individual input node 211, 212. Thus, a positive bridge arm 221 is provided between the output node 213 and the positive input node 211, and a negative bridge arm 221 is provided between the output node 213 and the negative input node 212.

[0039] Each bridge arm 221 includes two switches 23 connected in series at an intermediate node 222 (although they do not necessarily share the same current, as will be clear below). Specifically, each bridge arm 221 of each phase module 22 includes an internal switch 231 connected between the output node 213 and the intermediate node 222, and an external switch 232 connected between the input nodes 211, 212 connected to the bridge arm 221 (which may be a positive input node 211 or a negative input node 212) and the intermediate node 222.

[0040] Then, phase module 22 includes a flying capacitor 223 connected to controllable switch 23. In a preferred embodiment, flying capacitor 223 is connected between intermediate nodes 222 of the two bridge arms 221. Preferably, flying capacitor 223 is not connected to any other node besides intermediate node 222, so that all current circulating in flying capacitor 223 is always simultaneously input and / or drawn from the two intermediate nodes 222.

[0041] Flying capacitor 223 is configured to be equal to the reference voltage V dc The operation is performed using a voltage that is half the voltage between the positive input node 211 and the negative input node 212. As will be clear from below, based on the on-state of the different switches 23 of the phase module 22, the intermediate nodes 222 at the ends of the flying capacitor 223 can be at different voltage levels at different times.

[0042] The primary task of the control system 3 is to control the switches 23 of the converter 2, causing them to momentarily adopt combinations of on states in order to generate a predetermined voltage at the output node 213. In a preferred embodiment, the control system 3 is configured to control the switches 23 of each phase module 22 according to four combinations of states, such that the voltage of the relevant output node 213 can present three different levels.

[0043] These states will be referenced Figure 3 The discussion focuses on the first four graphs, which represent the current circulating in switch 23 of phase module 22 during the switching cycle, or similarly represent the control logic signal of switch 23 at the moment when a positive but not maximum output phase voltage is desired. Figure 3 The first four graphs specifically represent the current I of the external switch 232 of the positive bridge arm 221. 232 The current I of the internal switch 231 of the positive bridge arm 221 231 The current I of the internal switch 231 of the negative bridge arm 221 231 and the current I of the external switch 232 of the negative bridge arm 221. 232 .

[0044] In the first state combination of the phase module, both switches 23 of the positive bridge arm 221 are on, while both switches 23 of the negative bridge arm are off. Figure 3 In this combination, the timing of the overlap of the periods of the conduction states Ton in the first two curves is used to represent the combination. In the first state combination, the voltage at the output node 213 of phase module 22 is equal to the voltage at the positive input node 211, i.e., the reference voltage V. dc .

[0045] In the second state combination of the phase module, the two switches 23 of the positive bridge arm 221 are off, and the two switches 23 of the negative bridge arm are on. This combination is symmetrical to the previous combination and does not... Figure 3 As shown, a positive average voltage is desired. In the second state combination, the voltage at the output node 213 of phase module 22 is equal to the voltage at the negative input node 212, i.e., equal to the reference voltage -V. dc on the contrary.

[0046] In the third and fourth state combinations, the internal switches 231 and external switches 232 of the two different bridge arms 221 are turned on (exclusively). For example, in the third combination, the internal switch 231 of the positive bridge arm 221 and the external switch 232 of the negative bridge arm 221 (second and fourth curves) are turned on, while in the fourth combination, the internal switch 231 of the negative bridge arm 221 and the external switch 232 of the positive bridge arm 221 (first and third curves) are turned on. In either combination, the remaining two switches 23 are turned off. In the third and fourth state combinations, the voltage at the output node 213 of the phase module 22 is zero, which is the absolute difference between the voltage of one of the input nodes 211 and 212 and the voltage of the flying capacitor 223.

[0047] Figure 3 The fifth and last graphs represent the circulating current I in the flying capacitor 223. 223 And it is the result of a combination of the first four curves. Importantly, in the first and third state combinations, the circulating current I in the flying capacitor 223... 223 It is zero. Therefore, when the output phase voltage equals the reference voltage V... dc Or its opposite -V dc At that time, the flying capacitor 223 is not affected by any current.

[0048] Conversely, in the third and fourth state combinations, the circulating current I in the flying capacitor 223 223 Equal to phase current I 213 The voltage can be positive or negative. Therefore, when the output phase voltage is zero, the flying capacitor 223 is subjected to a voltage equal to the phase current I. 213 The stress is proportional to the intensity (if zero voltage occurs in the phase current I). 213 When it is also zero, the stress can also be essentially zero.

[0049] Typically, during the switching cycle, the circulating current I in the flying capacitor 223 of phase module 22... 223 The average root mean square value is determined by the phase current I of the phase coefficient C. 213 The product is given, and the phase coefficient C depends on the alternation of four state combinations as detailed below.

[0050] In order to control switch 23, control system 3 is configured to generate a set of logic control signals and send them to switch 23 of phase module 22, such as to determine the switching of switch 23 between open and closed states.

[0051] If PWM and DPWM control are known, based on the three corresponding phase modulation signals V m Generate a set of logic control signals for phase module 22, for example, for use with the corresponding carrier signal V. c Compare them.

[0052] As is well known, carrier signal V c It is a periodic signal with a predetermined switching period (usually triangular or sawtooth-shaped). Conversely, the modulated signal V m Preferably, it is a periodic signal (e.g., a sine wave) with a specific fundamental period, which is greater than the switching period.

[0053] Conversely, having the same Figure 3 The logic control signal for the current waveform of the first four curves is a signal with two discrete levels, one level determining the closed state of switch 23 and the other level determining the open state.

[0054] As is well known, according to the corresponding phase modulation signal V m Each switch 23 of phase module 22 will remain in the on state and off state respectively during the on state period Ton and the off state period Toff within the switching cycle. For each switch 23, the time relationship between the on state period and the switching cycle is also called the duty cycle.

[0055] Then, the control system 3 is configured to control the switching 23 of each phase module 22 by alternating different combinations of on-state states, so that, with respect to the average value of the switching cycle, the corresponding output phase voltage result is similar to the modulation signal V. m The duty cycle of the switch 23 in the positive bridge arm 221 (which shares the same individual duty cycle among them) will also be referred to as the reference phase duty cycle D, while the duty cycle of the switch 23 in the negative bridge arm 221 (which also shares the same individual duty cycle) is equal to the complement of the reference phase duty cycle D, i.e., 1-D. It should be noted that the reference phase duty cycle D varies linearly with the phase output voltage, from 0 at the minimum value to 1 at the maximum value.

[0056] In a preferred example known per se, a single modulation signal V is used. m This generates logic control signals for different switches 23 of the same phase module 22. For the internal and external switches 231, 232 of one of the bridge arms 221 (e.g., the positive bridge arm 221), the same modulation V is used. m The comparison is made with two different carriers, which are offset from each other, for example, during the switching half-cycle, or whose signs are opposite. For the switch 23 of the other bridge arm 221, it is not necessary to compare the carrier and the modulation signal V. m A new comparison can be made between them, but logic control signals complementary to the logic control signals already generated for the first bridge arm 221 can be used, particularly a pair of complementary logic control signals for the two external switches 232 and a pair of complementary logic control signals for the two internal switches 231, such as those from... Figure 3 As can be seen from the first four graphs.

[0057] It should be noted that the modulated signal V m The upper and lower values ​​are variable, corresponding to maintaining the first and second state combinations throughout the entire switching cycle, and thus corresponding to the maximum or minimum output phase voltage.

[0058] In fact, when the modulating signal V m When the modulated signal V remains equal to the upper or lower value within a certain interval (referencing a duty cycle D equal to 1 or 0, i.e., the first and second duty cycles), the modulation signal V remains equal to the upper or lower value within that interval. m With carrier V c (carrier V) c (They also vary between the same terminal values) There will be no intersection, so the switch 23 controlled in this way will not switch.

[0059] On the other hand, when the modulating signal V m When the duty cycle is zero (reference duty cycle D equals 0.5, i.e. center duty cycle), only the third and fourth state combinations will alternate, and the output phase voltage will be constant and 0.

[0060] When the modulation signal V m In the intermediate state between zero and one of the terminal values, for a positively modulated signal (such as...) Figure 3 As shown in the graph, the first state combination alternates with the third and fourth state combinations; while for negative modulation signals, the second state combination alternates with the third and fourth state combinations. These alternations are based on the following time conditions:

[0061] - Output phase voltage and modulation V m Maintain a proportional relationship, and

[0062] - The third and fourth state combinations remain in equal time between them so as not to change the charging state of the flying capacitor 223.

[0063] As can be seen from the above discussion, when the duty cycle is equal to 0 or 1 (output phase voltage is V), dc or -V dc When the duty cycle is 0.5 (output phase voltage is 0), the combination of the third and fourth states (i.e., the state with the greatest stress on the flying capacitor 223 of phase module 22) will be avoided; while when the duty cycle is 0.5 (output phase voltage is 0), the combination of the third and fourth states will be maintained (alternating between one state and another state).

[0064] exist Figure 5 , Figure 7 and Figure 9 In the curve diagram, refer to the aforementioned phase coefficient C (i.e., the circulating current I in the flying capacitor 223 relative to phase module 22). 223 The root mean square value and the phase current I 213The ratios within the switching cycle illustrate these cases. The phase coefficient C essentially represents the phase current I in the flying capacitor 223 during the commutation cycle, relative to the switching cycle. 213 The cycle time. Therefore, for a unit phase current I... 213 The phase coefficient C also represents the stress condition of the flying capacitor 223.

[0065] The phase coefficient C is a predetermined function of the reference phase duty cycle D, or equivalently, a predetermined function of the phase modulation signal. When the reference phase duty cycle D is 0.5, this function reaches its maximum value (equal to 1), corresponding to the phase modulation signal and zero output phase voltage; while when the reference phase duty cycle D is 0 or 1, this function reaches its minimum value (equal to 0), corresponding to the maximum or minimum modulation signal and output phase voltage.

[0066] For the intermediate values ​​of the duty cycle and / or the phase modulation signal and / or the output phase voltage, the phase coefficient C varies linearly between the three indicated points, so the closer to the reference duty cycle D of 0.5, the larger the phase coefficient C becomes.

[0067] Control system 3 is configured to generate a three-phase modulation signal V using DPWM technology. m Specifically, a three-phase modulation signal V is generated. m The starting point consists of three sinusoidal phase signals V sin They are composed of waves that are 120° apart, have a period equal to the fundamental period, and have equal amplitudes. Figure 6 , Figure 8 and Figure 10 The three sinusoidal signals V shown sin They are then distinguished using three phases. Without DPWM technology, these sinusoidal V... sin The signal could have been used as a modulated waveform.

[0068] Each phase modulation signal V m Both involve applying a specific signal of the same polarity to the corresponding V-phase sinusoidal signal. sin The signal of the same polarity is shared for the three-phase module 22. Therefore, for all phase modules 22, at each time, the phase modulation signal V... m With sinusoidal phase signal V sin The differences between them are all equal. Furthermore, the three-phase modulated signal V... m The positive sequence components correspond to three sinusoidal phase signals V. sin .

[0069] Figure 6 , Figure 8 , Figure 9 The phase modulation signal V is shown in the figure. m Three examples, each corresponding to a sinusoidal signal V. sinWith phase current I 213 The three different phase shifts, specifically corresponding to power factors of 1, 0, and 0.7, mean that even with the same sinusoidal signal V, the power factor remains constant. sin Signals of the same polarity will also have different time shapes.

[0070] As is well known, the same polarity components of voltage cannot generate current in a three-phase system. Therefore, the same polarity signal is introduced into the phase modulation signal V. m The phase will not change relative to the use of a sinusoidal signal V. sin The phase current I obtained as the modulation signal 213 .

[0071] For different intervals of a fundamental periodic sequence, there are usually at least six distinct intervals (or in some cases multiples of six intervals, for example...). Figure 8 and Figure 10 The sequence is divided into twelve intervals, and signals of the same polarity typically have different time shapes in different intervals. Specifically, in each interval of the sequence, signals of the same polarity are generated such that three saturated V... m The optimal V in phase modulation signal f Upon reaching saturation, it becomes a flat-top modulated signal with a constant value throughout the entire interval. This constant value can be equal to either the upper or lower value, i.e., one of the values ​​that does not switch during the interval.

[0072] Therefore, within this interval, signals of the same polarity are not constant, but rather equal to a constant value and a sinusoidal signal V. sin The difference between them. Within this interval, the same polarity signal is also applied to the sinusoidal signals V of the other two phases. sin Above, the corresponding phase modulation signals V of these sinusoidal signals m Saturation has not been reached. Therefore, in each interval, all three modulation signals V m All are relative to the corresponding phase sinusoidal signal V sin It was translated.

[0073] In each interval, the optimal flat-top modulation signal V f That is, the phase modulation signal V that has reached saturation. m It is based on the standard explained in more detail below from the three-phase modulated signal V m Selected from among them. Specifically, for each interval, in the three V... m Consider alternatives to candidate flat-top modulation signals in phase modulation signals.

[0074] It is important to emphasize that, within each interval, one of the three flat-top modulation signal candidates must always be discarded. This specifically corresponds to the phase sinusoidal signal V. sinThe candidate flat-top modulated signal, during this interval, the phase sinusoidal signal is located at the position of the other two phase sinusoidal signals V. sin Between. In fact, if a particular phase reaches saturation, one of the other phases will have a phase modulation signal V exceeding the upper or lower end value. m .

[0075] For a single phase exceeding the threshold, even if the electronic components of control system 3 are capable of achieving this, the output phase voltage will no longer be related to the phase modulation signal V. m This is proportional, and therefore the positive sequence component of the output phase voltage will be altered, and an unacceptable reverse sequence voltage will be introduced.

[0076] Therefore, during this interval, the optimal flat-top modulation signal V f The only possible choice is the one corresponding to the maximum phase sinusoidal signal V. sin The signal that saturates at the upper end, or the signal corresponding to the minimum phase sinusoidal signal V. sin (Signal that saturates at the lower end value).

[0077] In other words, within each interval, it is necessary to choose whether to saturate at the upper value or at the lower value (in both cases, the phase that reaches saturation becomes the only phase that can reach the saturation of interest during that interval). Figure 4 By illustrating the first theoretical modulation signal V for the three phases mth1 The set (assuming saturation is always chosen at the upper limit) and the second theoretical modulation signal V for the three phases. mth2 The set (assuming saturation is always chosen at the lower end value) is used to illustrate this choice. In each interval, the three-phase modulated signal V... m The corresponding first or second theoretical modulation signal V mth1 V mth2 set.

[0078] Among these flat-top modulation signal candidates, the optimal choice is to make the circulating current I in the flying capacitor 223 of the three-phase module 22 within the considered interval. 223 The choice of minimizing the combination of these signals is preferably given by the sum of their squares, or equivalently by their root mean square values. Therefore, the optimal flat-top modulated signal V... f The choice of allows for the calculation of the same polarity signal required for saturation, as well as all three-phase modulated signals V. m The instantaneous value.

[0079] Preferably, in order to select the optimal flat-top modulation signal V f During the interval of each possible alternative candidate flat-top modulation signal, calculate the circulating current I in the flying capacitor 223 of the three-phase module 22. 223 .

[0080] In particular, in order to calculate the circulating current I in intervals with different possible alternative choices 223 For each alternative option, control system 3 determines the reference phase duty cycle D for all three phases. Then, for each phase, the circulating current I in the flying capacitor 223 of each phase module 22 is calculated. 223 According to the phase current I 213 And the corresponding reference phase duty cycle D. More specifically, the phase coefficient C is determined according to the predetermined function of the reference phase duty cycle D described above, and by multiplying the phase coefficient C by the phase current I. 213 To determine the circulating current I of phase module 22 223 The product is in Figure 5 , Figure 7 and Figure 9 It is displayed graphically.

[0081] In this way, for each possible alternative choice of the flat-top modulation signal candidate, the circulating current I in the three flying capacitors 223 of the phase module 22 is obtained. 223 .

[0082] Preferably, as expected, the circulating current I in the flying capacitor 223 of the three-phase module 22 is minimized. 223 The combination lies in selecting these circulating currents I 223 The candidate flat-top modulation signal with the smallest sum of squares or root mean square value is taken as the optimal flat-top modulation signal V. f .

[0083] Using this control strategy, in each interval of the sequence, the optimal flat-top modulation signal V is used. f The switches 23 of the associated phase module 22 remain in their respective on or off states throughout the entire interval, and are synchronized with the optimal flat-top modulation signal V. f The circulating current I in the flying capacitor 223 of the associated phase module 22 223 It remains zero throughout the entire interval.

[0084] However, it should be noted that the most positive effect of the proposed control is usually not on obtaining the optimal flat-top modulation signal V. f It does not affect the phase of the signal, but rather the acquisition of the intermediate phase modulation signal V. m (or equivalently, phase V) sin The influence of the phase of a sinusoidal signal. In fact, this phase has the largest phase coefficient C. Therefore, in many cases (such as from...), it has an effect on the phase of the signal. Figure 7 and Figure 9 (As recognized in the text), circulating current I 223 It is also high, namely the phase coefficient C and the phase current I. 213The product of the two. Therefore, shifting the modulation signal of this phase to the appropriate end without reaching saturation significantly reduces its phase coefficient C and its circulating current I. 223 .

[0085] In other cases (such as) Figure 5 As shown), the phase with intermediate modulation may not be the most critical because, although the phase coefficient value of phase C is high, the phase current I of that phase is low. 213 It may be lower.

[0086] Note that in three-phase module 22, there may also be modules that are negatively affected because they are neither phases with intermediate modulation signals nor phases with modulation signals modulated to saturation. This phase is typically oriented towards a phase coefficient closer to 1.

[0087] However, the optimal flat-top modulation signal V is chosen to minimize the sum of the root mean square values ​​of the circulating currents in the three phases. f Furthermore, considering that there are several intervals in the fundamental period, and in some of these intervals, from the viewpoint of different phases, the current situation of the phase is basically the same throughout the fundamental period, thus reducing the average stress of each flying capacitor 223 and potentially reducing their size.

[0088] As already mentioned, within the fundamental period, the interval sequence typically comprises at least six intervals. In practice, for a positively saturated phase, the pattern presented in one interval is correspondingly repeated in other intervals of the other two phases, and also correspondingly repeated in another interval with negative saturation. Therefore, the duration of these intervals typically does not exceed 60° of the fundamental period.

[0089] Therefore, in some embodiments, a fixed duration of 60° can be used, optionally with a predetermined end to the interval. Thus, although the phase current I... 213 The intensity and phase may change, but the duration will not.

[0090] However, in the preferred embodiment, the duration of each interval is neither a priori fixed nor is its end point or number of intervals fixed. Instead, the control system 3 is configured to determine the circulating current I in the flying capacitor 223 of the three-phase module 22. 223 For the new optimal flat-top modulation signal V f In contrast, it is lower than the current optimal flat-top modulation signal V. f When (preferably lower than at least a predefined increment value), by using the current optimal flat-top modulation signal V f Switching to the new optimal flat-top modulation signal V f This is used to determine the end of the current interval and the beginning of the new interval in the sequence.

[0091] More specifically, the control system 3 can be configured to repeatedly screen possible alternatives to candidate flat-top modulation signals at a frequency determined by a computation time less than the fundamental period and typically less than that of each interval (e.g., equal to the switching period). Then, each interval of the sequence is identified through a series of consecutive computation times, where the optimal flat-top modulation signal V... f The choice remains unchanged, and when different optimal flat-top modulation signals V are calculated... f The event will end at that time.

[0092] The optional introduction of the aforementioned increment value avoids the optimal flat-top modulation signal V f The risk of overly frequent changes led to the introduction of hysteresis functions in the control.

[0093] from Figure 6 , Figure 8 and Figure 10 As can be seen from the graph, depending on the power factor, the control-induced intervals sometimes align with the peak current and / or voltage of the relevant phase, and sometimes they do not. Furthermore, it should be recognized that there can be six intervals, each with a duration corresponding to 60°, but there can also be more, and the durations are often different from each other. For example, when accumulated within the fundamental period, the maximum saturation interval for each phase can accumulate to 60°, and the same applies to the minimum saturation interval.

[0094] Obviously, those skilled in the art will be able to make many equivalent modifications to the above variations without departing from the scope of protection defined by the appended claims.

Claims

1. A power conversion system (1), comprising: - Power converter (2), which includes: - Two input nodes (211, 212) can be connected to the direct current (DC) bus. - Three output nodes (213) of the three corresponding AC phase conductors that can be connected to a three-phase system (1), and - Three-phase modules (22), each three-phase module is connected to two input nodes (211, 212) and to a single corresponding output node (213), wherein each phase module (22) includes multiple controllable switches (23) and flying capacitors (223) connected to the controllable switches (23), and -Control system (3), which is configured according to three corresponding phase modulation signals (V m The system generates and sends a set of logic control signals to the switch (23) of the phase module (22) to switch the switch (23) between an open state and a closed state. The control system (3) is configured as follows: - The three-phase modulation signal (V) is generated using DPWM (Discontinuous Pulse Width Modulation) technology. m ), to three sinusoidal phase signals (V) with a fundamental period sin Add a common polarity signal for the three-phase module (22). - Generate the same polarity signal such that, for the interval sequence within the fundamental period, in each interval, from the three-phase modulation signal (V m The optimal flat-top modulation signal (V) selected from ) f It presents a constant value equal to either the higher or lower end of the value. The control system (3) is characterized in that it is configured as follows: -in the three-phase modulation signal (V m In the sequence, the optimal flat-top modulation signal (V) is selected for each interval. f ), so that the circulating current (I) in the flying capacitor (223) of the three-phase module (22) is 223 Minimize the predetermined combination of ) within the interval. Among them, the circulating current (I) in the flying capacitor (223) of the three-phase module (22) 223 The predetermined combination is the circulating current (I) 223 The sum of squares or root mean square value of ). For each interval, the control system (3) is configured to select the optimal flat-top modulation signal (V). f When: - Calculate the circulating current (I) in the flying capacitor (223) of the three-phase module (22) during the interval. 223 ), offering multiple alternatives to the flat-top modulated signal candidate. -Calculate the circulating current (I) in the flying capacitor (223) of the three-phase module (22) for the interval. 223 The predetermined combination of ) and - Select one of the flat-top modulation signal candidates whose predetermined combination calculated for the interval is the smallest as the optimal flat-top modulation signal (V). f ).

2. The system (1) according to claim 1, wherein the control system (3) is configured to calculate the circulating current (I) in the flying capacitor (223). 223 When ), for each flat-top modulated signal candidate, use: - For each phase, the reference phase duty cycle (D) is determined relative to the interval and relative to the flat-top modulation signal candidate, and - For each phase module (22), calculate based on the phase current (I 213 The circulating current (I) in the flying capacitor (223) and the corresponding reference phase duty cycle (D) of the flying capacitor (223) 223 ).

3. The system (1) according to claim 2, wherein the circulating current (Iflying current in the flying capacitor (223) is calculated for each phase module (22). 223 )include: - The phase coefficient (C) is determined according to a predetermined function of the reference phase duty cycle (D), preferably the predetermined function is largest for the reference phase duty cycle (D) corresponding to zero output phase voltage, specifically equal to a reference phase duty cycle (D) of 0.5, and - By multiplying the phase coefficient (C) by the phase current (I) 213 ) to determine the circulating current (I) of the phase module (22). 223 ).

4. The system (1) according to claim 2 or 3, wherein each phase module (22) is configured to generate a maximum output phase voltage, preferably equal to 1, for a first terminal reference phase duty cycle (D); generate a minimum output phase voltage, preferably equal to 0, for a second terminal reference phase duty cycle (D); and generate a zero output phase voltage, preferably equal to 0.5, for a center reference phase duty cycle (D).

5. The system (1) according to any one of claims 1 to 4, wherein: - Each phase module (22) includes a pair of bridge arms (221), each bridge arm connecting the output node (213) of the phase module (22) and a corresponding individual input node (211, 212), each bridge arm (221) including two controllable switches (23) connected in series with each other at an intermediate node (222), and - For each phase module (22), the flying capacitor (223) is connected between the intermediate nodes (222) of the two bridge arms (221).

6. The system (1) according to claim 5, wherein: - Each bridge arm (221) of each phase module (22) includes an internal switch (231) connected to the corresponding output node (213) and an external switch (232) connected to the corresponding input node (211, 212). - For each phase module (22), the logic control signal set includes individual signals for all the switches (23) of the two bridge arms (221), which include an on-state period and an off-state period. - The conduction cycle of each external switch (232) and the conduction cycle of the internal switches (231) of the two bridge arms (221) overlap, such that when the internal switches (231) and external switches (232) of two different bridge arms (221) are simultaneously in the conduction state, the flying capacitor (223) is subjected to a circulating current (I0). 223 The impact of ).

7. The system (1) according to any one of claims 1 to 6, wherein in each interval of the sequence, the optimal flat-top modulation signal (V) is used. f The switch (23) of the phase module (22) associated with the ) remains in its own on or off state throughout the entire duration of the interval, and is associated with the optimal flat-top modulation signal (V f The circulating current (I) in the flying capacitor (223) of the associated phase module (22) 223 The value is zero throughout the entire duration of the interval.

8. The system (1) according to any one of claims 1 to 7, wherein the control system (3) is configured to determine the circulating current (I) in the flying capacitor (223) of the three-phase module (22). 223 For the new optimal flat-top modulation signal (V) f The value is less than the actual optimal flat-top modulation signal (V). f When determining the end of the current interval of the sequence and the beginning of a new interval, the new interval has a current interval from the actual optimal flat-top modulation signal (V). f To the new optimal flat-top modulation signal (V) f The transformation of ).

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