A thin film bulk acoustic resonator without sacrifice layer filling and a method of manufacturing the same

Abstract

The application provides a thin film bulk acoustic resonator without sacrifice layer filling and a preparation method thereof. A micro-hole array is prepared on a substrate through a photoetching and deep etching process. Then, a conformal covering structure is formed on the inner wall of the micro-hole and the surface of the substrate by using a chemical vapor deposition technology. Next, the deposition and patterning of a bottom electrode, a piezoelectric layer, a top electrode and a passivation layer are sequentially completed on the substrate with the protective layer wall, so as to construct a complete resonant stack structure. Finally, the selective etching characteristics (the horizontal etching rate is significantly faster than the vertical etching rate) of TMAH and other anisotropic wet etchants are used to horizontally drill the substrate through the micro-hole channel, so as to form a complete air gap cavity under the resonant stack structure, and meanwhile, a longitudinal support structure is reserved.

Description

Technical Field

[0001] This application relates to the field of MEMS device technology, and more specifically, to a thin-film bulk acoustic resonator that does not require sacrificial layer filling and its fabrication method. Background Technology

[0002] Bulk acoustic wave resonators (BAWs) and their radio frequency filters play a crucial role in modern wireless communication systems. A full-band smartphone typically integrates 70–100 or more radio frequency filters. These devices are not only used in large quantities, but are also key components that determine the communication quality and transmission rate of the terminal.

[0003] Currently, the mainstream thin-film bulk acoustic resonator (FBAR) technologies are mainly divided into two categories: solid-state assembled resonator (SMR) structures and air-gap FBAR structures. The SMR structure achieves effective acoustic wave isolation by fabricating an acoustic reflection layer between the substrate and the bottom electrode, composed of alternating stacks of high and low acoustic impedance materials. However, this structure has inherent technical limitations that are difficult to overcome: firstly, the device's operating bandwidth is limited by the acoustic impedance ratio of the reflection layer material pairs, making it difficult to meet the application requirements of broadband communication scenarios; secondly, some acoustic wave energy penetrates into the substrate, causing energy loss and making it difficult to achieve the ideal device quality factor (Q value); thirdly, the fabrication process of the multilayer reflection structure is complex, and stress control is difficult, resulting in high device production costs.

[0004] Air-gap FBAR structures commonly employ a sacrificial layer process to fabricate the acoustic reflection cavity. However, this approach also faces significant technical bottlenecks: forming a smooth deposition interface on the sacrificial layer surface to ensure the quality of the subsequent piezoelectric layer requires an additional chemical mechanical polishing process. This not only increases process complexity and production costs but also easily introduces defects and contaminants into the substrate surface, affecting device performance stability. Furthermore, commonly used sacrificial layer materials (such as amorphous silicon, polycrystalline silicon, and silicon oxide) have poor high-temperature resistance and cannot withstand high-temperature processing environments. This severely limits the processing temperature when depositing piezoelectric films on top of the sacrificial layer structure, resulting in the piezoelectric film's crystal quality, preferred orientation, and piezoelectric performance failing to reach their optimal state, ultimately restricting the potential for improving the overall device performance.

[0005] In addition, both the SMR structure and the traditional air gap FBAR structure have obvious defects in their heat dissipation path. That is, the heat generated during the operation of the device is mainly conducted outward through the top electrode via the air gap or reflective layer, resulting in low heat dissipation efficiency, which severely limits the power capacity of the device and makes it difficult to meet the application requirements of high power RF front end. Summary of the Invention

[0006] The purpose of this application is to provide a thin-film bulk acoustic resonator without sacrificial layer filling and its fabrication method, so as to solve the problems of high process complexity, high production cost, difficulty in achieving optimal crystal quality, preferred orientation and piezoelectric performance of piezoelectric thin films, and limited device power capacity due to poor heat dissipation path in air gap type FBAR structure thin-film bulk acoustic resonators.

[0007] This application provides a method for fabricating a thin-film bulk acoustic resonator without sacrificial layer filling, comprising: An array of micropores is etched on the substrate surface; A protective layer material is deposited on the front side of the substrate to conformally cover the inner wall of the micropores and the substrate surface. Then, holes are etched and drilled at the location of the micropores to form a protective layer wall. Polycrystalline silicon is deposited on the front side of the substrate and then planarized by CMP; silicon dioxide is deposited on the front side of the substrate to form a temperature compensation layer. A seed layer is deposited on the front side of the substrate; electrode material is deposited on the seed layer and patterned to obtain the bottom electrode; A piezoelectric material is deposited on the front side of the substrate and patterned to form a piezoelectric layer; Electrode material is deposited on the piezoelectric layer and patterned to obtain the top electrode; Etch the piezoelectric layer to expose the second region of the bottom electrode and the third region of the seed layer; A passivation material is deposited on the front side of the substrate and patterned to expose the first region of the top electrode, thus obtaining a passivation layer. The third region of the seed layer is etched down to below the protective layer wall, forming a deep hole; Metallic materials are deposited in the first and second regions to form metal pads; Anisotropic wet etching is performed through deep holes to laterally etch the substrate and form an air gap cavity.

[0008] In the above technical solution, a micro-hole array is prepared on the substrate by photolithography and deep etching processes; then, chemical vapor deposition is used to form a conformal protective layer wall structure on the inner wall of the micro-holes and the surface of the substrate; next, on the substrate with the protective layer wall, the bottom electrode, piezoelectric layer, top electrode and passivation layer are deposited and patterned in sequence to construct a complete resonant stack structure; finally, by utilizing the selective etching characteristics of anisotropic wet etchants such as TMAH (the lateral etching rate is significantly faster than the longitudinal etching rate), the substrate is laterally etched through the micro-hole channels to form a complete air gap cavity under the resonant stack structure, while retaining the longitudinal support structure.

[0009] This embodiment provides a thin-film bulk acoustic resonator and its fabrication method that does not require a sacrificial layer. By adopting a process path of first constructing a complete resonant stack and then using anisotropic lateral etching to form an air gap cavity, the dependence of traditional sacrificial layer technology on planarization and release steps is effectively avoided, simplifying the process flow and improving the fabrication yield.

[0010] The entire device utilizes a substrate as a support framework before piezoelectric layer deposition, instead of the traditional sacrificial layer. Furthermore, due to the optimized sequence of piezoelectric layer deposition and cavity formation, the piezoelectric thin film can be deposited or annealed at high temperatures, unrestricted by subsequent processes. This results in thin film materials with higher crystallinity and superior piezoelectric performance, improving the electromechanical conversion efficiency and frequency consistency of the resonator. In addition, the air gap structure formed by this method provides an ideal acoustic reflection interface, contributing to a higher quality factor.

[0011] This embodiment also utilizes the excellent thermal conductivity of silicon nitride material. By introducing a silicon nitride sidewall structure below the electrode, an effective additional heat dissipation path is provided for the working electrode, significantly improving the device's thermal management capabilities, thereby enhancing its power handling capacity and long-term operational reliability. The silicon nitride located beneath the piezoelectric layer has a thermal expansion coefficient that matches that of the piezoelectric layer material, effectively compensating for thermal stress fluctuations during device operation and improving the resonator's temperature stability and long-term reliability.

[0012] In some alternative implementations, the substrate material is one or more combinations of silicon, silicon carbide, and sapphire; The seed layer is made of one or more of titanium, chromium, and tantalum. The electrode material is one or more of the following: molybdenum, gold, platinum, copper, aluminum, silver, titanium, tungsten, and nickel. The piezoelectric material is one or more combinations of aluminum nitride, scandium-doped aluminum nitride, lead zirconate titanate, and lithium niobate; The passivation material is one or more combinations of silicon oxide, doped silicon oxide, silicon nitride, and doped silicon nitride; The metallic material is one or more of the following: gold, platinum, copper, aluminum, silver, titanium, and nickel.

[0013] In some alternative implementations, an array of micropores is etched on the substrate surface, including: Micropores are formed on the substrate surface by photolithography and deep reactive ion etching processes. The diameter of the micropores is 1-30 μm and the depth of the micropores is 2-10 μm.

[0014] In some alternative implementations, a seed layer is deposited on the front side of the substrate, including: A seed layer is deposited on the protective layer wall using magnetron sputtering technology; Electrode materials are deposited on the seed layer, including: Electrode material is deposited on the seed layer using a magnetron sputtering process.

[0015] In some alternative embodiments, a piezoelectric material is deposited on the front side of the substrate and patterned to form a piezoelectric layer, including: A piezoelectric layer is deposited on the front side of the substrate using a radio frequency magnetron sputtering process.

[0016] In some alternative embodiments, electrode material is deposited on the piezoelectric layer, including: Electrode materials are deposited on the piezoelectric layer using magnetron sputtering. Passivation materials are deposited on the front side of the substrate, including: Passivation materials are deposited on the substrate using PECVD or magnetron sputtering processes.

[0017] In some alternative implementations, a passivation material is deposited on the front side of the substrate and patterned to expose a first region of the top electrode, including: The passivation layer is patterned using photolithography and reactive ion etching processes to expose a first region of the top electrode. In some alternative embodiments, the piezoelectric layer is etched to expose a second region of the bottom electrode and a third region of the seed layer, including: The piezoelectric layer is patterned using photolithography and reactive ion etching processes, exposing the second region of the bottom electrode and the third region of the seed layer.

[0018] In some alternative implementations, the third region of the seed layer is etched down to below the protective layer wall to form a deep hole, including: The temperature compensation layer, polysilicon, and substrate are etched from the third region using photolithography and deep reactive ion etching processes. The etching stops below the protective layer wall, forming a deep hole.

[0019] In some alternative embodiments, metallic material is deposited in the first and second regions to form metal pads, including: Electron beam evaporation is used to deposit metallic materials in the first and second regions, and metal pads are formed by a stripping process.

[0020] In some alternative embodiments, anisotropic wet etching is performed through deep holes to laterally etch the substrate and form an air gap cavity, including: Through deep holes, anisotropic wet etching is performed at 70℃-90℃ for 3-5 hours using a 1%-25% TMAH solution.

[0021] This application provides a thin-film bulk acoustic resonator, which includes a substrate, a protective layer wall, and a resonant stack structure. The protective layer wall is set on the substrate, and a resonant stack structure is set on the protective layer wall; The protective layer wall opens downwards and forms a cavity with the substrate. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart illustrating the steps of a method for fabricating a thin-film bulk acoustic resonator without sacrificial layer filling, as provided in this application embodiment; Figure 2 This application provides a schematic diagram of the substrate after micropores have been formed. Figure 3 This is a schematic diagram of the base after the protective layer wall has been formed, provided in an embodiment of this application. Figure 4 This is a schematic diagram of a polysilicon-filled substrate provided in an embodiment of this application; Figure 5 This is a schematic diagram of the substrate after surface planarization, provided in an embodiment of this application. Figure 6 This is a schematic diagram of the substrate after the formation of the temperature compensation layer, provided in an embodiment of this application. Figure 7 This is a schematic diagram of a substrate with a seed layer and bottom electrode formed, as provided in an embodiment of this application. Figure 8 This is a schematic diagram of the substrate after the formation of the piezoelectric layer, provided in an embodiment of this application. Figure 9 This is a schematic diagram of a substrate with a top electrode formed and patterned according to an embodiment of this application; Figure 10 A schematic diagram of the substrate formed by the lower electrode exposure and release groove provided in an embodiment of this application; Figure 11 This is a schematic diagram of the substrate for forming the passivation layer provided in an embodiment of this application; Figure 12 This is a schematic diagram of the substrate after deep hole formation provided in an embodiment of this application; Figure 13 This is a schematic diagram of the substrate after the metal pads have been formed, provided in an embodiment of this application. Figure 14 This is a schematic diagram of a substrate with an air gap structure formed by lateral etching with TMAH etchant provided in an embodiment of this application. Figure 15 Performance test diagram of the thin-film bulk acoustic resonator provided in the embodiments of this application.

[0024] Icons: 100-Substrate, 101-Microvia, 102-Protective layer wall, 103-Polycrystalline silicon, 104-Temperature compensation layer, 105-Seed layer, 106-Bottom electrode, 107-Piezoelectric layer, 108-Top electrode, 109-Passivation layer, 110-Deep hole, 111-Metal pad; 112-Air gap cavity. Detailed Implementation

[0025] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0026] Please refer to Figure 1 , Figure 1 A flowchart illustrating the steps of a method for fabricating a thin-film bulk acoustic resonator without sacrificial layer filling, as provided in this application embodiment, includes: Step S1: Etch a micro-hole array on the substrate surface; Step S2: Deposit a protective layer material on the front side of the substrate to conformally cover the inner wall of the micropores and the substrate surface, and then etch and drill holes at the location of the micropores to form a protective layer wall. The protective layer material includes silicon nitride or silicon dioxide.

[0027] Step S3: Deposit polysilicon 103 on the front side of the substrate and then perform CMP planarization; deposit silicon dioxide on the front side of the substrate to form a temperature compensation layer 104. Step S4: Deposit a seed layer on the front side of the substrate; deposit electrode material on the seed layer and pattern it to obtain the bottom electrode; Step S5: Deposit piezoelectric material on the front side of the substrate and pattern it to form a piezoelectric layer; Step S6: Deposit electrode material on the piezoelectric layer and pattern it to obtain the top electrode; Step S7: Etch the piezoelectric layer to expose the second region of the bottom electrode and the third region of the seed layer; Step S8: Deposit passivation material on the front side of the substrate and pattern it to expose the first area of ​​the top electrode, thus obtaining the passivation layer; Step S9: Etch the third region of the seed layer down to the bottom of the protective layer wall to form a deep hole; Step S10: Deposit metal material in the first and second regions to form metal pads; Step S11: Perform anisotropic wet etching through deep holes to laterally etch the substrate and form an air gap cavity 112.

[0028] In the above technical solution, a micro-hole array 101 is prepared on the substrate 100 by photolithography and deep etching processes; then, a conformal protective layer wall 102 structure is formed on the inner wall of the micro-hole 101 and the surface of the substrate 100 using chemical vapor deposition; next, on the substrate 100 with the protective layer wall 102, the bottom electrode 106, the piezoelectric layer 107, the top electrode 108 and the passivation layer 109 are deposited and patterned in sequence to construct a complete resonant stacked structure; finally, the selective etching characteristics of anisotropic wet etchants such as TMAH (the lateral etching rate is significantly faster than the longitudinal etching rate) are used to perform lateral etching on the substrate 100 through the channels of the micro-hole 101 to form a complete air gap cavity 112 below the resonant stacked structure, while retaining the longitudinal support structure.

[0029] The photolithography process involves transferring the designed pattern to the surface of the substrate 100 using a combination of photosensitive material (photoresist) and a mask. The deep etching process involves etching microstructures with a high aspect ratio (depth much greater than width) onto the substrate 100 through a combination of physical and chemical actions. This typically employs reactive ion etching (RIE) technology, combined with alternating etching and passivation steps.

[0030] Anisotropic wet etching is a chemical etching method that typically uses liquid chemical reagents (such as TMAH and KOH) for wet etching. Its characteristic is that the etching rate varies significantly across different crystal orientations or spatial directions. In micro / nano fabrication, this property is used to selectively etch materials in specific orientations to form high-precision three-dimensional structures (such as cavities and trenches). The etching rate is related to the crystal orientation or geometric direction; for example, in silicon substrate 100, the etching rate of TMAH on the (100) crystal plane is much higher than that on the (111) crystal plane.

[0031] This embodiment provides a thin-film bulk acoustic resonator that does not require sacrificial layer filling and its fabrication method. By adopting a process path of first constructing a complete resonant stack and then using anisotropic transverse etching to form an air gap cavity 112, the dependence of traditional sacrificial layer technology on planarization and release steps is effectively avoided, simplifying the process flow and improving the fabrication yield.

[0032] The entire device uses a substrate 100 as a support framework before the piezoelectric layer 107 is deposited, instead of a traditional sacrificial layer. Furthermore, due to the optimized sequence of piezoelectric layer 107 deposition and cavity formation, the piezoelectric thin film can be deposited or annealed at high temperatures, unrestricted by subsequent processes. This results in a thin film material with higher crystallinity and superior piezoelectric performance, improving the electromechanical conversion efficiency and frequency consistency of the resonator. In addition, the air gap structure formed by this method provides an ideal acoustic reflection interface, contributing to a higher quality factor.

[0033] This embodiment also utilizes the excellent thermal conductivity of silicon nitride material. By introducing a silicon nitride sidewall structure below the electrode, an effective additional heat dissipation path is provided for the working electrode, significantly improving the device's thermal management capabilities, thereby enhancing its power handling capacity and long-term operational reliability. The silicon nitride located below the piezoelectric layer 107 has a thermal expansion coefficient that matches that of the piezoelectric layer material, effectively compensating for thermal stress fluctuations during device operation and improving the resonator's temperature stability and long-term reliability.

[0034] In some alternative embodiments, the substrate 100 is made of one or more combinations of silicon, silicon carbide, and sapphire; The seed layer 105 is made of one or more combinations of titanium, chromium, and tantalum; The electrode material is one or more of the following: molybdenum, gold, platinum, copper, aluminum, silver, titanium, tungsten, and nickel. The piezoelectric material is one or more combinations of aluminum nitride, scandium-doped aluminum nitride, lead zirconate titanate, and lithium niobate; The passivation material is one or more combinations of silicon oxide, doped silicon oxide, silicon nitride, and doped silicon nitride; The metallic material is one or more of the following: gold, platinum, copper, aluminum, silver, titanium, and nickel.

[0035] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the substrate after the formation of micropores 101, as provided in an embodiment of this application.

[0036] In some optional embodiments, an array of micro-holes 101 is etched on the surface of the substrate 100, including: forming micro-holes 101 on the surface of the substrate 100 using photolithography and deep reactive ion etching (DRIE) processes. The diameter of the micro-holes 101 is 1-30 μm, and the depth of the micro-holes 101 is 2-10 μm. Specifically, before etching, the substrate 100 is ultrasonically cleaned using an SPM solution. Photoresist is spin-coated on the surface of the substrate 100, and a circular array of micro-holes 101 with a diameter of 1.2 μm is defined by ultraviolet photolithography. A deep reactive ion etching process is then used to form micro-holes 101 with a depth of 3 μm. The etching process parameters are: SF6 flow rate 180 sccm, C4F8 flow rate 120 sccm, etching / passivation cycle times of 8 s / 6 s, and RF power of 1000 W.

[0037] Please refer to Figure 3 , Figure 3This is a schematic diagram of the substrate after the protective layer wall 102 has been formed, as provided in an embodiment of this application. First, silicon nitride is deposited to form a passivation layer, then etching and drilling are performed to re-form micropores. The newly formed micropores have a smaller radius. The protective layer wall mainly serves to surround a portion of the substrate area downwards. Subsequently, this portion of the substrate area is etched away laterally, forming a cavity between the protective layer wall and the substrate. Simultaneously, the protective layer wall has good thermal conductivity, providing additional heat dissipation pathways for the electrodes.

[0038] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a polysilicon-filled substrate provided in an embodiment of this application, in which polysilicon is deposited to fill micropores.

[0039] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the substrate after surface planarization provided in an embodiment of this application, which has undergone chemical mechanical polishing (CMP) planarization treatment.

[0040] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the substrate after the formation of the temperature compensation layer provided in the embodiments of this application. Silicon dioxide is deposited on the substrate to form the temperature compensation layer.

[0041] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the substrate after the formation of the seed layer 105 and the bottom electrode 106, as provided in an embodiment of this application.

[0042] In some alternative embodiments, electrode material is deposited on the piezoelectric layer, including: Electrode materials are deposited on the piezoelectric layer using magnetron sputtering. Passivation materials are deposited on the front side of the substrate, including: Passivation materials are deposited on the substrate using PECVD or magnetron sputtering processes.

[0043] Specifically, titanium was deposited as a seed layer 105 on the surface of the protective layer wall 102 using magnetron sputtering. The thickness of the seed layer 105 was 20-100 nm. Subsequently, molybdenum was deposited as the bottom electrode 106, with a thickness of 50-2000 nm. The sputtering conditions were: Ar gas flow rate 50 sccm, pressure 3 mTorr, and power 500 W. Patterning was then performed using photolithography and reactive ion etching. The etching gas was an SF6 / O2 mixed gas (flow rate 80 / 20 sccm) at a power of 300 W, forming the designed bottom electrode 106 pattern with a lateral width of 50-500 μm.

[0044] Among them, magnetron sputtering is a physical vapor deposition (PVD) technology that uses high-energy particles (usually argon ions) to bombard the surface of a target material, causing the target atoms or molecules to be sputtered out and deposited on a substrate 100 to form a thin film. Its core feature is the use of a magnetic field to confine the plasma, which significantly improves sputtering efficiency and film quality.

[0045] Please refer to Figure 8 , Figure 8 The top electrode 108 is a schematic diagram of the substrate after the formation of the piezoelectric layer provided in the embodiments of this application.

[0046] In some alternative embodiments, a piezoelectric material is deposited on the front side of the substrate and patterned to form a piezoelectric layer, including: A piezoelectric layer was deposited on the front side of the substrate using radio frequency magnetron sputtering. Specifically, aluminum nitride was deposited as a piezoelectric layer 107 on the patterned bottom electrode 106 using radio frequency magnetron sputtering, and the thickness of the piezoelectric layer 107 was 0.1-2 μm. The process conditions were: Ar / N2 mixed gas (ratio 1:1), pressure 5 mTorr, power 800 W, and substrate temperature 400 °C.

[0047] Please refer to Figure 9 , Figure 9 A schematic diagram of a substrate with a top electrode formed and patterned, provided for an embodiment of this application.

[0048] In some alternative embodiments, electrode material is deposited on the piezoelectric layer, including: Electrode materials are deposited on the piezoelectric layer using magnetron sputtering. Passivation materials are deposited on the front side of the substrate, including: Passivation materials are deposited on the substrate using PECVD or magnetron sputtering processes.

[0049] Specifically, molybdenum is deposited as the top electrode 108 on the piezoelectric layer 107 using magnetron sputtering. The thickness of the top electrode 108 is 50-2000 nm. The sputtering conditions are: Ar gas flow rate 50 sccm, pressure 3 mTorr, and power 500 W. Silicon nitride is deposited as the passivation layer 109 at 350 °C using PECVD. The thickness of the passivation layer 109 is 100-500 nm. The designed top electrode 108 pattern is formed by photolithography and reactive ion etching, with a lateral width of 50-500 μm. The etching gas is a CF4 / O2 mixed gas (flow rate 40 / 10 sccm) and power 400 W.

[0050] Please refer to Figure 10 , Figure 10 This is a schematic diagram of the substrate formed by the lower electrode exposure and release groove provided in the embodiments of this application.

[0051] In some alternative implementations, the piezoelectric layer is etched to expose a second region of the bottom electrode and a third region of the seed layer, including: The piezoelectric layer is patterned using photolithography and reactive ion etching processes, exposing the second region of the bottom electrode and the third region of the seed layer.

[0052] Please refer to Figure 11 , Figure 11 This is a schematic diagram of the substrate for forming the passivation layer provided in an embodiment of this application.

[0053] In some alternative implementations, a passivation material is deposited on the front side of the substrate and patterned to expose a first region of the top electrode, including: The passivation layer is patterned using photolithography and reactive ion etching processes to expose the first region of the top electrode.

[0054] Please refer to Figure 12 , Figure 12 This is a schematic diagram of the substrate after deep hole formation, provided in an embodiment of this application.

[0055] In some alternative implementations, the third region of the seed layer is etched down to below the protective layer wall to form a deep hole, including: The temperature compensation layer, polysilicon, and substrate are etched from the third region using photolithography and deep reactive ion etching processes. The etching stops below the protective layer wall, forming a deep hole.

[0056] Please refer to Figure 13 , Figure 13 This is a schematic diagram of the substrate after the metal pads have been formed, provided in an embodiment of this application.

[0057] In some optional embodiments, depositing metal material in the first and second regions to form metal pads 111 includes: depositing metal material in the first and second regions using an electron beam evaporation process, and forming the metal pads 111 by a lift-off process. Specifically, an electron beam evaporation process is used to deposit a metal layer, and the metal pads 111 are formed by a lift-off process. The thickness of the metal pads 111 is 0.4-10 μm. The evaporation rate is 0.5 nm / s, and the vacuum level is better than 5 × 10⁻⁶. -6 Torr.

[0058] Electron beam evaporation is a physical vapor deposition (PVD) technique that uses a high-energy electron beam to bombard a target material, locally heating it to its evaporation temperature. The evaporated material atoms or molecules are then deposited onto the substrate surface in a vacuum environment to form a thin film. Lift-off processing is a technique used in micro / nano fabrication to form patterns on metal or dielectric thin films. Its core steps involve first patterning a photoresist, then depositing the thin film material, and finally dissolving the photoresist to remove excess material, leaving only the desired patterned film. This process is particularly suitable for materials that are difficult to directly etch, such as those requiring electron beam evaporation.

[0059] Please refer to Figure 14 , Figure 14 This is a schematic diagram of a substrate with an air gap structure formed by lateral etching with TMAH etchant provided in an embodiment of this application.

[0060] In some optional embodiments, anisotropic wet etching is performed through deep holes 110 to laterally etch the substrate 100 and form an air gap cavity 112. This includes: performing anisotropic wet etching for 3-5 hours at 70°C-90°C using a 1%-25% TMAH solution through deep holes 110. Specifically, taking advantage of the selective etching characteristic of TMAH, which has a much faster etching rate for the (100) crystal orientation of single-crystal silicon than for the (111) crystal orientation, anisotropic wet etching is performed for 4 hours at 85°C using a 20wt% TMAH solution. Laterally etching is then performed through micro-holes 101 to form an air gap cavity 112 directly below the resonant stack. The lateral dimension of the air gap cavity 112 is 50-200 μm, and the depth is 2-10 μm.

[0061] This application provides a thin-film bulk acoustic resonator, which includes a substrate, a protective layer wall, and a resonant stack structure. The protective layer wall is disposed on the substrate, and the resonant stack structure is disposed on the protective layer wall; The protective layer wall opens downwards and forms a cavity with the substrate.

[0062] Please refer to Figure 15 , Figure 15 The performance test diagram of the thin-film bulk acoustic resonator provided in the embodiment of this application shows that, compared with the conventional structure, the structure of this solution reaches a higher frequency at the resonance peak and can excite a higher frequency.

[0063] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0064] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0065] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0066] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0067] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a thin-film bulk acoustic resonator without sacrificial layer filling, characterized in that, include: An array of micropores is etched on the substrate surface; A protective layer material is deposited on the front side of the substrate to conformally cover the inner wall of the micropores and the substrate surface. Then, holes are etched and drilled at the location of the micropores to form a protective layer wall. Polycrystalline silicon is deposited on the front side of the substrate and then planarized using CMP. Silicon dioxide is deposited on the front side of the substrate to form a temperature compensation layer; Deposit a seed layer on the front side of the substrate; Electrode material is deposited on the seed layer and patterned to obtain the bottom electrode; A piezoelectric material is deposited on the front side of the substrate and patterned to form a piezoelectric layer; Electrode material is deposited on the piezoelectric layer and patterned to obtain the top electrode; The piezoelectric layer is etched to expose the second region of the bottom electrode and the third region of the seed layer; A passivation material is deposited on the front side of the substrate and patterned to expose the first region of the top electrode, thus obtaining a passivation layer. The third region of the seed layer is etched down to below the protective layer wall to form a deep hole; Metallic material is deposited in the first and second regions to form metal pads; Anisotropic wet etching is performed through the deep holes to laterally etch the substrate, forming an air gap cavity.

2. The method as described in claim 1, characterized in that, The substrate is made of one or more combinations of silicon, silicon carbide and sapphire. The seed layer is made of one or more combinations of titanium, chromium, and tantalum. The electrode material is one or more combinations of molybdenum, gold, platinum, copper, aluminum, silver, titanium, tungsten, and nickel; The piezoelectric material is one or more combinations of aluminum nitride, scandium-doped aluminum nitride, lead zirconate titanate, and lithium niobate; The passivation material is one or more combinations of silicon oxide, doped silicon oxide, silicon nitride, and doped silicon nitride; The metallic material is one or more combinations of gold, platinum, copper, aluminum, silver, titanium, and nickel.

3. The method as described in claim 1, characterized in that, The etching of the micro-hole array on the substrate surface includes: Micropores are formed on the substrate surface by photolithography and deep reactive ion etching processes. The diameter of the micropores is 1-30 μm and the depth of the micropores is 2-10 μm.

4. The method as described in claim 1, characterized in that, The seed layer deposited on the front side of the substrate includes: A seed layer is deposited on the protective layer wall using magnetron sputtering technology; The deposition of electrode material on the seed layer includes: Electrode material is deposited on the seed layer using a magnetron sputtering process.

5. The method as described in claim 1, characterized in that, The process of depositing and patterning a piezoelectric material on the front side of a substrate to form a piezoelectric layer includes: A piezoelectric layer is deposited on the front side of the substrate using a radio frequency magnetron sputtering process.

6. The method as described in claim 1, characterized in that, The deposition of electrode material on the piezoelectric layer includes: Electrode materials are deposited on the piezoelectric layer using magnetron sputtering. The passivation material deposited on the front side of the substrate includes: Passivation materials are deposited on the substrate using PECVD or magnetron sputtering processes.

7. The method as described in claim 1, characterized in that, The step of depositing passivation material on the front side of the substrate and patterning it to expose a first region of the top electrode includes: The passivation layer is patterned using photolithography and reactive ion etching processes to expose the first region of the top electrode.

8. The method as described in claim 1, characterized in that, The etching of the piezoelectric layer to expose the second region of the bottom electrode and the third region of the seed layer includes: The piezoelectric layer is patterned using photolithography and reactive ion etching processes to expose the second region of the bottom electrode and the third region of the seed layer.

9. The method as described in claim 1, characterized in that, The third region of the seed layer is etched down to below the protective layer wall to form a deep hole, including: The temperature compensation layer, polysilicon, and substrate are etched from the third region using photolithography and deep reactive ion etching processes. The etching stops below the protective layer wall, forming a deep hole.

10. The method as described in claim 1, characterized in that, The deposition of metallic material in the first and second regions to form metal pads includes: Metal materials are deposited in the first and second regions using an electron beam evaporation process, and metal pads are formed by a stripping process.

11. The method as described in claim 1, characterized in that, The anisotropic wet etching process through the deep hole, laterally etching the substrate to form an air gap cavity, includes: Through the deep holes, anisotropic wet etching is performed for 3-5 hours at 70℃-90℃ using a 1%-25% TMAH solution.

12. A thin-film bulk acoustic resonator, characterized in that, The thin-film bulk acoustic resonator is prepared according to any one of claims 1-11, and comprises a substrate, a protective layer wall, and a resonant stack structure; The protective layer wall is disposed on the substrate, and the resonant stack structure is disposed on the protective layer wall; The protective layer wall opens downwards and forms a cavity with the substrate.

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