A low power level shifter circuit for a power chip

Abstract

The application claims a low-power consumption level shift circuit for a power supply chip, belonging to the field of integrated circuits, comprising a level shift core circuit with power tube voltage mutation noise suppression and a dynamic narrow pulse circuit. The application adopts a power tube voltage mutation noise suppression circuit composed of inverters Inv3-Inv5, delay circuits DL1-DL2, AND gates And1-And2, an OR gate OR1, and MOS tubes MP7-MP10 to improve the reliability of the level shift circuit, suppress the problem of power tube being mistakenly turned on or turned off on the power supply chip circuit caused by power tube voltage mutation noise, and provide dynamic narrow pulse signals for the gates of MOS tubes MN1-MN2 and dynamically control the level shift core circuit with power tube voltage mutation noise suppression, so as to improve the reliability of the level shift circuit, reduce the power consumption of the circuit, and thus realize a low-power consumption level shift circuit suitable for a power supply chip.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a low-power level shifting circuit for power supply chips. Background Technology

[0002] With the rapid development of portable electronic products, power supply chips are gradually evolving towards higher efficiency and lower power consumption. Level shifting circuits are one of the key circuits in power supply chips, providing control signals to the power transistors. Their performance characteristics directly affect the power consumption, switching frequency, and conversion ratio of the power supply chip. With the development of integrated circuit technology, the performance requirements for the internal level shifting circuits of power supply chips are becoming increasingly stringent.

[0003] Figure 1 This is a traditional level shifting circuit, consisting of NMOS transistors MN1 and MN2, PMOS transistors MP1 and MP2, and an inverter Inv. PMOS transistors MP1 and MP2 are identical, and NMOS transistors MN1 and MN2 are identical. When the input terminal VIN is high, NMOS transistor MN1 is turned on, NMOS transistor MN2 is turned off, and the drain of NMOS transistor MN1 is low, turning on PMOS transistor MP2 and charging the output terminal VOUT, causing the output voltage VOUT to rise. PMOS transistor MP1 is then turned off, and the final output voltage VOUT equals the voltage at the signal terminal VDDH. Similarly, when the input voltage VIN is low, NMOS transistor MN1 is turned off, NMOS transistor MN2 is turned on, and the output voltage VOUT is low. While traditional level-shifting circuits are simple in structure and easy to implement, they can only operate within a specific range. The operating power supply voltage must be within the voltage tolerance range of a single transistor. Furthermore, converting a low logic level to a high level requires a large NMOS transistor with a high channel width-to-length ratio to provide a large current to pull down the potential of the corresponding node, which will lead to an increase in propagation delay. Summary of the Invention

[0004] This invention aims to solve the problems of the prior art mentioned above, and proposes a low-power level shifting circuit for power supply chips. The technical solution of this invention is as follows:

[0005] A low-power level shifting circuit for a power supply chip includes: a level shifting core circuit for suppressing power transistor voltage surge noise and a dynamic narrow pulse circuit; wherein the signal output terminal of the level shifting core circuit for suppressing power transistor voltage surge noise is connected to the signal input terminal of the dynamic narrow pulse circuit, and the signal output terminal of the dynamic narrow pulse circuit is connected to the signal input terminal of the level shifting core circuit for suppressing power transistor voltage surge noise; the level shifting core circuit for suppressing power transistor voltage surge noise employs inverters Inv3, Inv4, and Inv5, delay circuits DL1 and DL2, AND gates And1 and And2. A power transistor voltage surge noise suppression circuit composed of OR gate OR1, PMOS transistors MP7, MP8, MP9, and MP10 is used to improve the reliability of the level shift circuit and suppress the problem of power transistors being mistakenly turned on or off on the power chip circuit due to power transistor voltage surge noise. The dynamic narrow pulse circuit provides dynamic narrow pulse signals to the gates of NMOS transistors MN1 and MN2, and performs dynamic narrow pulse control on the level shift core circuit with power transistor voltage surge noise suppression, thereby improving the reliability of the level shift circuit, reducing the power consumption of the level shift circuit, and thus realizing a low-power level shift circuit suitable for power chips.

[0006] Furthermore, the level shifting core circuit for suppressing power transistor voltage surge noise includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, and MN6; PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, and MP10; high-voltage MOSFETs HMN1 and HMN2; inverters Inv3, Inv4, Inv5, Inv7, Inv8, and Inv9; and a delay... The circuit consists of DL1, delay circuit DL2, AND gate And1, AND gate And2, and OR gate OR1. The source of PMOS transistor MP1 is connected to the sources of PMOS transistors MP2, MP3, MP4, MP5, and MP6, as well as the signal terminal BST. The drain of PMOS transistor MP1 is connected to the drain of high-voltage MOS transistor HMN1, the gate of PMOS transistor MP1, the gate of PMOS transistor MP2, and the gate of PMOS transistor MP3. The source of high-voltage MOS transistor HMN1 is connected to the drain of NMOS transistor MN1. The gate of high-voltage MOS transistor HMN1 is connected to the gate of high-voltage MOS transistor HMN2 and an external power supply. The source of NMOS transistor MN1 is connected to VDD. The source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2 and external ground GND. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP7. The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN3, the gate of NMOS transistor MN3, and the gate of NMOS transistor MN4. The source of NMOS transistor MN3 is connected to the sources of NMOS transistors MN4, MN5, and MN6, and the signal terminal SW. The drain of PMOS transistor MP3 is connected to the source of PMOS transistor MP8. The drain of PMOS transistor MP8 is connected to the drain of NMOS transistor MN5, the input terminal of inverter Inv9, and the inverter... The output of Inv8 is connected. The drain of PMOS transistor MP4 is connected to the source of PMOS transistor MP9. The drain of PMOS transistor MP9 is connected to the drain of NMOS transistor MN4, the output of inverter Inv9, the input of inverter Inv7, and the input of inverter Inv8. The drain of PMOS transistor MP5 is connected to the source of PMOS transistor MP10. The drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN6, the gate of NMOS transistor MN6, and the gate of NMOS transistor MN5. The drain of PMOS transistor MP6 is connected to the gate of PMOS transistor MP6, the gate of PMOS transistor MP5, the gate of PMOS transistor MP4, and the drain of high-voltage MOS transistor HMN2.The source of high-voltage MOSFET HMN2 is connected to the drain of NMOS MOSFET MN2. The output of inverter Inv7 is connected to the input of inverter Inv3, the input of the level-down circuit, the input of inverter Inv4, one input of AND gate And2, and the circuit output VOUT. The output of inverter Inv3 is connected to the input of inverter Inv5 and one input of AND gate And1. The output of inverter Inv5 is connected to the input of delay circuit DL2. The output of delay circuit DL2 is connected to the other input of AND gate And1. The output of AND gate And1 is connected to one input of OR gate OR1. The output of inverter Inv4 is connected to the input of delay circuit DL1. The output of delay circuit DL1 is connected to the other input of AND gate And2. The output of AND gate And2 is connected to the other input of OR gate OR1. The output of OR gate OR1 is connected to the gates of PMOS MOSFETs MP7, MP8, MP9, and MP10. ,

[0007] Furthermore, the dynamic narrow pulse circuit includes: inverter Inv1, inverter Inv2, NOR gate Nor1, NOR gate Nor2, NAND gate Nand1, and a level-down circuit. The input terminal of inverter Inv1 is connected to one input terminal of NOR gate Nor2 and the signal input terminal VIN, respectively. The output terminal of inverter Inv1 is connected to one input terminal of NOR gate Nor1. The other input terminal of NOR gate Nor1 is connected to one input terminal of NAND gate Nand1 and the output terminal of the level-down circuit, respectively. The output terminal of NOR gate Nor1 is connected to the gate of NMOS transistor MN1 and the input terminal of inverter Inv2, respectively. The output terminal of inverter Inv2 is connected to the other input terminal of NAND gate Nand1. The output terminal of NAND gate Nand1 is connected to the other input terminal of NOR gate Nor2. The output terminal of NOR gate Nor2 is connected to the gate of NMOS transistor MN2.

[0008] Furthermore, in the level shifting core circuit with power transistor voltage surge noise suppression, when the operating state of the power transistor on the power chip circuit changes, the external bootstrap capacitor between the signal terminal BST and the signal terminal SW enables the voltage of the signal terminal BST to quickly follow the voltage of the signal terminal SW. However, the parasitic capacitance at the gates of the PMOS transistors MP1 and MP6 in the level shifting core circuit with power transistor voltage surge noise suppression causes their gate voltages to fail to quickly follow the voltage of the signal terminal BST, thereby generating power transistor voltage surge noise, which in turn causes the power transistor on the power chip circuit to be mistakenly turned on or off. To address this issue, the present invention employs a power transistor voltage surge noise suppression circuit composed of inverters Inv3, Inv4, Inv5, delay circuits DL1 and DL2, AND gates And1 and And2, OR gate OR1, PMOS transistors MP7, MP8, MP9, and MP10 to improve the reliability of the level shifting circuit and suppress the problem of power transistors being mistakenly turned on or off on the power chip circuit due to power transistor voltage surge noise.High-voltage MOSFETs HMN1 and HMN2 isolate the high-voltage and constant-voltage circuits, preventing the constant-voltage MOSFETs from being damaged and improving their transmission speed. Inverters Inv8 and Inv9 form a latch. PMOS transistors MP7, MP8, MP9, and MP10 suppress voltage surge noise injected into the latch. When the input signal VIN changes from low to high, the output signal VOUT changes from low to high. The output of AND gate And1 remains low, and the output of AND gate And2 generates a narrow pulse signal at the rising edge of the output signal VOUT. Simultaneously, the output of OR gate OR1 generates a narrow pulse signal, causing PMOS transistors MP7, MP8, MP9, and MP10 to turn off. Voltage surge noise generated by the power transistors on the power chip causes PMOS transistors MP2, MP3, and MP10 to turn off through the signal terminal BST. The current generated when MOSFETs MP4 and MP5 are turned on does not affect the output signal of the latch, thus keeping the circuit output VOUT at a high level, thereby improving the reliability of the level shift circuit. When the signal at the input VIN changes from high to low, the signal at the circuit output VOUT changes from high to low. The output of AND gate And2 remains low, and the output of AND gate And1 generates a narrow pulse signal at the rising edge of the signal at the circuit output VOUT. At the same time, the output of OR gate OR1 generates a narrow pulse signal, which turns off MOSFETs MP7, MP8, MP9, and MP10. The voltage surge noise generated by the power transistors on the power chip causes the current generated when MOSFETs MP2, MP3, MP4, and MP5 are turned on through the signal terminal BST, which does not affect the output signal of the latch, thus keeping the circuit output VOUT at a low level, thereby improving the reliability of the level shift circuit.

[0009] Furthermore, in the aforementioned dynamic narrow pulse circuit, a narrow pulse duration that is too short cannot guarantee the reliability of the circuit at various process corners, while a narrow pulse duration that is too long will increase power consumption and limit the minimum on-time of the power chip system, thereby limiting its switching frequency and conversion ratio. To solve this problem, the present invention employs a dynamic narrow pulse circuit composed of a level-down circuit, inverters Inv1 and Inv2, NOR gates Nor1 and Nor2, and NAND gate Nand1. The level-down circuit converts the high power rail signal at the circuit output VOUT into a low power rail signal and uses it as an input signal for NOR gate Nor1 and NAND gate Nand1, while isolating the constant voltage domain circuit and the high voltage domain circuit to prevent the constant voltage MOSFET from being damaged. During the transition from high to low level of the input signal VIN, the gate of NMOS transistor MN1 remains low, causing MN1 to be cut off. At this time, the initial gate level of NMOS transistor MN2 is low. When the falling edge of the input signal VIN arrives, the gate of NMOS transistor MN2 becomes high, turning on MN2. Through the level shifting core circuit that suppresses power transistor voltage surge noise, the output VOUT becomes low. The low level of output VOUT, through the level-down circuit, NAND gate Nand1, and NOR gate Nor2, causes the gate of NMOS transistor MN2 to become low, thus generating a dynamic narrow pulse at the gate of NMOS transistor MN2. During the transition from low to high level of the input signal VIN, the gate of NMOS transistor MN2 remains low. The voltage level causes NMOS transistor MN2 to be cut off. At this time, the initial voltage level of the gate of NMOS transistor MN1 is low. When the rising edge of the signal at the input terminal VIN arrives, the gate of NMOS transistor MN1 becomes high, turning on NMOS transistor MN1. Through the level shifting core circuit that suppresses power transistor voltage surge noise, the output terminal VOUT becomes high. The high voltage level of the output terminal VOUT, through the level down circuit and the NOT gate Nor1, turns the gate of NMOS transistor MN1 low, thereby generating a dynamic narrow pulse at the gate of NMOS transistor MN1. This achieves a dynamic narrow pulse mode to control the level shifting core circuit that suppresses power transistor voltage surge noise, improving the reliability of the level shifting circuit and reducing the power consumption of the level shifting circuit, thus realizing a low-power level shifting circuit suitable for power supply chips.

[0010] The advantages and beneficial effects of this invention are as follows:

[0011] This invention provides a low-power level shift circuit for power supply chips. It employs a power transistor voltage surge noise suppression circuit composed of inverters Inv3, Inv4, Inv5, delay circuits DL1 and DL2, AND gates And1 and And2, OR gate OR1, PMOS transistors MP7, MP8, MP9, and MP10 to improve the reliability of the level shift circuit and suppress the problem of power transistors being mistakenly turned on or off on the power supply chip circuit due to power transistor voltage surge noise. The dynamic narrow pulse circuit provides dynamic narrow pulse signals to the gates of NMOS transistors MN1 and MN2, performing dynamic narrow pulse control on the core level shift circuit with power transistor voltage surge noise suppression function. This improves the reliability of the level shift circuit and reduces its power consumption, thereby realizing a low-power level shift circuit suitable for power supply chips. Attached Figure Description

[0012] Figure 1 It is a traditional level shifter circuit schematic;

[0013] Figure 2 A low-power level shifting circuit for a power chip is provided as a preferred embodiment of the present invention;

[0014] Figure 3 shows the input-output simulation curves of a low-power level shifting circuit for a power chip according to a preferred embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0016] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0017] In this embodiment, an inverter Inv3, inverter Inv4, inverter Inv5, delay circuit DL1, delay circuit DL2, AND gate And1, AND gate And2, OR gate OR1, PMOS transistors MP7, MP8, MP9, and MP10 are used to construct a power transistor voltage surge noise suppression circuit to improve the reliability of the level shift circuit and suppress the problem of power transistors being mistakenly turned on or off on the power chip circuit due to power transistor voltage surge noise. The dynamic narrow pulse circuit provides dynamic narrow pulse signals to the gates of NMOS transistors MN1 and MN2, and performs dynamic narrow pulse control on the level shift core circuit with power transistor voltage surge noise suppression, thereby improving the reliability of the level shift circuit, reducing the power consumption of the level shift circuit, and thus realizing a low-power level shift circuit suitable for power chips.

[0018] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0019] Example

[0020] A low-power level shifting circuit for power supply chips, such as Figure 2 As shown, the circuit includes a level-shifting core circuit 1 for suppressing power transistor voltage surge noise and a dynamic narrow pulse circuit 2. The signal output terminal of the level-shifting core circuit 1 for suppressing power transistor voltage surge noise is connected to the signal input terminal of the dynamic narrow pulse circuit 2, and the signal output terminal of the dynamic narrow pulse circuit 2 is connected to the signal input terminal of the level-shifting core circuit 1 for suppressing power transistor voltage surge noise. The level-shifting core circuit 1 for suppressing power transistor voltage surge noise employs inverters Inv3, Inv4, and Inv5, delay circuits DL1 and DL2, AND gates And1 and And2, and OR gates OR1. The power transistor voltage surge noise suppression circuit, composed of PMOS transistors MP7, MP8, MP9, and MP10, improves the reliability of the level shift circuit and suppresses the problem of power transistors being mistakenly turned on or off on the power chip circuit due to power transistor voltage surge noise. The dynamic narrow pulse circuit 2 provides dynamic narrow pulse signals to the gates of NMOS transistors MN1 and MN2, and performs dynamic narrow pulse control on the level shift core circuit 1 with power transistor voltage surge noise suppression, thereby improving the reliability of the level shift circuit, reducing the power consumption of the level shift circuit, and thus realizing a low-power level shift circuit suitable for power chips.

[0021] As a preferred technical solution, such as Figure 2As shown, the level shifting core circuit 1 with power transistor voltage surge noise suppression includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, high-voltage MOS transistors HMN1 and HMN2, inverters Inv3, Inv4, Inv5, Inv7, Inv8, and Inv9, and a delay circuit. The circuit consists of DL1, delay circuit DL2, AND gate And1, AND gate And2, and OR gate OR1. The source of PMOS transistor MP1 is connected to the sources of PMOS transistors MP2, MP3, MP4, MP5, and MP6, as well as the signal terminal BST. The drain of PMOS transistor MP1 is connected to the drain of high-voltage MOS transistor HMN1, the gate of PMOS transistor MP1, the gate of PMOS transistor MP2, and the gate of PMOS transistor MP3. The source of high-voltage MOS transistor HMN1 is connected to the drain of NMOS transistor MN1. The gate of high-voltage MOS transistor HMN1 is connected to the gate of high-voltage MOS transistor HMN2 and an external power supply. The source of NMOS transistor MN1 is connected to VDD. The source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2 and external ground GND. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP7. The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN3, the gate of NMOS transistor MN3, and the gate of NMOS transistor MN4. The source of NMOS transistor MN3 is connected to the sources of NMOS transistors MN4, MN5, and MN6, and the signal terminal SW. The drain of PMOS transistor MP3 is connected to the source of PMOS transistor MP8. The drain of PMOS transistor MP8 is connected to the drain of NMOS transistor MN5, the input terminal of inverter Inv9, and the inverter... The output of Inv8 is connected. The drain of PMOS transistor MP4 is connected to the source of PMOS transistor MP9. The drain of PMOS transistor MP9 is connected to the drain of NMOS transistor MN4, the output of inverter Inv9, the input of inverter Inv7, and the input of inverter Inv8. The drain of PMOS transistor MP5 is connected to the source of PMOS transistor MP10. The drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN6, the gate of NMOS transistor MN6, and the gate of NMOS transistor MN5. The drain of PMOS transistor MP6 is connected to the gate of PMOS transistor MP6, the gate of PMOS transistor MP5, the gate of PMOS transistor MP4, and the drain of high-voltage MOS transistor HMN2.The source of high-voltage MOSFET HMN2 is connected to the drain of NMOS MOSFET MN2. The output of inverter Inv7 is connected to the input of inverter Inv3, the input of the level-down circuit, the input of inverter Inv4, one input of AND gate And2, and the circuit output VOUT. The output of inverter Inv3 is connected to the input of inverter Inv5 and one input of AND gate And1. The output of inverter Inv5 is connected to the input of delay circuit DL2. The output of delay circuit DL2 is connected to the other input of AND gate And1. The output of AND gate And1 is connected to one input of OR gate OR1. The output of inverter Inv4 is connected to the input of delay circuit DL1. The output of delay circuit DL1 is connected to the other input of AND gate And2. The output of AND gate And2 is connected to the other input of OR gate OR1. The output of OR gate OR1 is connected to the gates of PMOS MOSFETs MP7, MP8, MP9, and MP10. ,

[0022] The dynamic narrow pulse circuit 2 includes: inverter Inv1, inverter Inv2, NOR gate Nor1, NOR gate Nor2, NAND gate Nand1, and a level-down circuit. The input terminal of inverter Inv1 is connected to one input terminal of NOR gate Nor2 and the signal input terminal VIN. The output terminal of inverter Inv1 is connected to one input terminal of NOR gate Nor1. The other input terminal of NOR gate Nor1 is connected to one input terminal of NAND gate Nand1 and the output terminal of the level-down circuit. The output terminal of NOR gate Nor1 is connected to the gate of NMOS transistor MN1 and the input terminal of inverter Inv2. The output terminal of inverter Inv2 is connected to the other input terminal of NAND gate Nand1. The output terminal of NAND gate Nand1 is connected to the other input terminal of NOR gate Nor2. The output terminal of NOR gate Nor2 is connected to the gate of NMOS transistor MN2.

[0023] In the level shifting core circuit 1 with power transistor voltage surge noise suppression, when the operating state of the power transistor in the power chip circuit changes, the external bootstrap capacitor between the signal terminal BST and the signal terminal SW enables the voltage of the signal terminal BST to quickly follow the voltage of the signal terminal SW. However, the parasitic capacitance at the gates of PMOS transistors MP1 and MP6 in the level shifting core circuit 1 with power transistor voltage surge noise suppression causes their gate voltages to fail to quickly follow the voltage of the signal terminal BST, thereby generating power transistor voltage surge noise, which leads to the power transistor in the power chip circuit being mistakenly turned on or off. To solve this problem, the present invention employs a power transistor voltage surge noise suppression circuit composed of inverters Inv3, Inv4, Inv5, delay circuits DL1 and DL2, AND gates And1 and And2, OR gate OR1, PMOS transistors MP7, MP8, MP9, and MP10 to improve the reliability of the level shifting circuit and suppress the problem of power transistor voltage surge noise causing the power transistor in the power chip circuit to be mistakenly turned on or off.High-voltage MOSFETs HMN1 and HMN2 isolate the high-voltage and constant-voltage circuits, preventing the constant-voltage MOSFETs from being damaged and improving their transmission speed. Inverters Inv8 and Inv9 form a latch. PMOS transistors MP7, MP8, MP9, and MP10 suppress voltage surge noise injected into the latch. When the input signal VIN changes from low to high, the output signal VOUT changes from low to high. The output of AND gate And1 remains low, and the output of AND gate And2 generates a narrow pulse signal at the rising edge of the output signal VOUT. Simultaneously, the output of OR gate OR1 generates a narrow pulse signal, causing PMOS transistors MP7, MP8, MP9, and MP10 to turn off. Voltage surge noise generated by the power transistors on the power chip causes PMOS transistors MP2, MP3, and MP10 to turn off through the signal terminal BST. The current generated when MOSFETs MP4 and MP5 are turned on does not affect the output signal of the latch, thus keeping the circuit output VOUT at a high level, thereby improving the reliability of the level shift circuit. When the signal at the input VIN changes from high to low, the signal at the circuit output VOUT changes from high to low. The output of AND gate And2 remains low, and the output of AND gate And1 generates a narrow pulse signal at the rising edge of the signal at the circuit output VOUT. At the same time, the output of OR gate OR1 generates a narrow pulse signal, which turns off MOSFETs MP7, MP8, MP9, and MP10. The voltage surge noise generated by the power transistors on the power chip causes the current generated when MOSFETs MP2, MP3, MP4, and MP5 are turned on through the signal terminal BST, which does not affect the output signal of the latch, thus keeping the circuit output VOUT at a low level, thereby improving the reliability of the level shift circuit.

[0024] In the aforementioned dynamic narrow pulse circuit 2, a narrow pulse duration that is too short cannot guarantee the reliability of the circuit at various process corners, while a narrow pulse duration that is too long will increase power consumption and limit the minimum on-time of the power chip system, thereby limiting its switching frequency and conversion ratio. To solve this problem, the present invention employs a dynamic narrow pulse circuit 2 composed of a level-down circuit, inverters Inv1 and Inv2, NOR gates Nor1 and Nor2, and NAND gate Nand1. The level-down circuit converts the high power rail signal at the circuit output VOUT into a low power rail signal and uses it as an input signal for NOR gate Nor1 and NAND gate Nand1, while isolating the constant voltage domain circuit and the high voltage domain circuit to prevent the constant voltage MOSFET from being damaged. During the transition from high to low level of the input signal VIN, the gate of NMOS transistor MN1 remains low, causing MN1 to be off. At this time, the initial gate level of NMOS transistor MN2 is low. When the falling edge of the input signal VIN arrives, the gate of NMOS transistor MN2 becomes high, turning on MN2. Through the level shifting core circuit 1, which suppresses power transistor voltage surge noise, the circuit output VOUT becomes low. The low level of output VOUT, through the level-down circuit, NAND gate Nand1, and NOR gate Nor2, causes the gate of NMOS transistor MN2 to become low, thus generating a dynamic narrow pulse at the gate of NMOS transistor MN2. During the transition from low to high level of the input signal VIN, the gate of NMOS transistor MN2 remains low. The voltage level causes NMOS transistor MN2 to be cut off. At this time, the initial voltage level of the gate of NMOS transistor MN1 is low. When the rising edge of the signal at the input terminal VIN arrives, the gate of NMOS transistor MN1 becomes high, turning on NMOS transistor MN1. Through the level shifting core circuit 1 that suppresses power transistor voltage surge noise, the output terminal VOUT becomes high. The high voltage level of the output terminal VOUT, through the level down circuit and the NOT gate Nor1, turns the gate of NMOS transistor MN1 low, thereby generating a dynamic narrow pulse at the gate of NMOS transistor MN1. This achieves a dynamic narrow pulse mode to control the level shifting core circuit 1 that suppresses power transistor voltage surge noise, improving the reliability of the level shifting circuit and reducing the power consumption of the level shifting circuit, thus realizing a low-power level shifting circuit suitable for power supply chips.

[0025] Figure 3 shows the input-output simulation curves of a low-power level shift circuit for a power chip according to the present invention. Figure 3(a) shows the input-output simulation curves of the low-power level shift circuit without a power transistor voltage surge noise suppression circuit, and Figure 3(b) shows the input-output simulation curves of the low-power level shift circuit with a power transistor voltage surge noise suppression circuit. The simulation results shown in Figure 3(a) indicate that when the input terminal VIN changes from low to high, the output terminal VOUT voltage V... out With signal terminal SW voltage V sw The difference V out -V sw The voltage is 5V, and the level shifting circuit is functioning normally. However, when the voltage at the signal terminal SW suddenly increases, V... out -V sw It has a voltage surge noise of 1.33V; the simulation results shown in Figure 3(b) show that when the voltage at the signal terminal SW experiences a sudden change, V out -V sw The voltage surge noise is only 400mV. Simulation results show that the power transistor voltage surge noise suppression circuit, consisting of inverters Inv3, Inv4, Inv5, delay circuits DL1 and DL2, AND gates And1 and And2, OR gate OR1, PMOS transistors MP7, MP8, MP9, and MP10, effectively improves the ability of the low-power level shift circuit to suppress power transistor voltage surge noise.

[0026] In the above embodiments of this application, a low-power level shifting circuit for a power supply chip includes a level shifting core circuit for suppressing power transistor voltage surge noise and a dynamic narrow pulse circuit. This application employs a power transistor voltage surge noise suppression circuit composed of inverters Inv3, Inv4, Inv5, delay circuits DL1 and DL2, AND gates And1 and And2, OR gate OR1, PMOS transistors MP7, MP8, MP9, and MP10 to improve the reliability of the level shifting circuit and suppress the problem of power transistors being mistakenly turned on or off on the power supply chip circuit due to power transistor voltage surge noise. The dynamic narrow pulse circuit provides dynamic narrow pulse signals to the gates of NMOS transistors MN1 and MN2, performing dynamic narrow pulse control on the level shifting core circuit for suppressing power transistor voltage surge noise, thereby improving the reliability of the level shifting circuit, reducing the power consumption of the level shifting circuit, and thus realizing a low-power level shifting circuit suitable for power supply chips.

[0027] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0028] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0029] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A low-power level shifting circuit for a power supply chip, characterized in that, include: The circuit comprises a level-shifting core circuit (1) for suppressing power transistor voltage surge noise and a dynamic narrow pulse circuit (2); wherein the signal output terminal of the level-shifting core circuit (1) for suppressing power transistor voltage surge noise is connected to the signal input terminal of the dynamic narrow pulse circuit (2), and the signal output terminal of the dynamic narrow pulse circuit (2) is connected to the signal input terminal of the level-shifting core circuit (1) for suppressing power transistor voltage surge noise; the level-shifting core circuit (1) for suppressing power transistor voltage surge noise employs inverters Inv3, Inv4, Inv5, delay circuits DL1 and DL2, AND gate And1, AND gate And2, and OR gate OR.

1. A power transistor voltage surge noise suppression circuit composed of PMOS transistors MP7, MP8, MP9 and MP10 is used to improve the reliability of the level shift circuit, thereby suppressing the problem of power transistors being mistakenly turned on or off on the power chip circuit due to power transistor voltage surge noise. The dynamic narrow pulse circuit (2) provides dynamic narrow pulse signals to the gates of NMOS transistors MN1 and MN2, and performs dynamic narrow pulse control on the level shift core circuit (1) with power transistor voltage surge noise suppression, thereby improving the reliability of the level shift circuit, reducing the power consumption of the level shift circuit, and thus realizing a low-power level shift circuit suitable for power chips.

2. The low-power level shifting circuit for a power supply chip according to claim 1, characterized in that, The level shifting core circuit (1) for suppressing power transistor voltage surge noise includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, high-voltage MOS transistors HMN1 and HMN2, inverters Inv3, Inv4, Inv5, Inv7, Inv8, Inv9, and a delay circuit. The circuit consists of DL1, delay circuit DL2, AND gate And1, AND gate And2, and OR gate OR1. The source of PMOS transistor MP1 is connected to the sources of PMOS transistors MP2, MP3, MP4, MP5, and MP6, as well as the signal terminal BST. The drain of PMOS transistor MP1 is connected to the drain of high-voltage MOS transistor HMN1, the gate of PMOS transistor MP1, the gate of PMOS transistor MP2, and the gate of PMOS transistor MP3. The source of high-voltage MOS transistor HMN1 is connected to the drain of NMOS transistor MN1. The gate of high-voltage MOS transistor HMN1 is connected to the gate of high-voltage MOS transistor HMN2 and the external power supply. The source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2 and external ground GND. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP7. The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN3, the gate of NMOS transistor MN3, and the gate of NMOS transistor MN4. The source of NMOS transistor MN3 is connected to the sources of NMOS transistors MN4, MN5, and MN6, and the signal terminal SW. The drain of PMOS transistor MP3 is connected to the source of PMOS transistor MP8. The drain of PMOS transistor MP8 is connected to the drain of NMOS transistor MN5, the input terminal of inverter Inv9, and inverter I. The output of nv8 is connected. The drain of PMOS transistor MP4 is connected to the source of PMOS transistor MP9. The drain of PMOS transistor MP9 is connected to the drain of NMOS transistor MN4, the output of inverter Inv9, the input of inverter Inv7, and the input of inverter Inv8. The drain of PMOS transistor MP5 is connected to the source of PMOS transistor MP10. The drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN6, the gate of NMOS transistor MN6, and the gate of NMOS transistor MN5. The drain of PMOS transistor MP6 is connected to the gate of PMOS transistor MP6, the gate of PMOS transistor MP5, the gate of PMOS transistor MP4, and the drain of high-voltage MOS transistor HMN2.The source of high-voltage MOSFET HMN2 is connected to the drain of NMOS MOSFET MN2. The output of inverter Inv7 is connected to the input of inverter Inv3, the input of the level-down circuit, the input of inverter Inv4, one input of AND gate And2, and the circuit output VOUT. The output of inverter Inv3 is connected to the input of inverter Inv5 and one input of AND gate And1. The output of inverter Inv5 is connected to the input of delay circuit DL2. The output of delay circuit DL2 is connected to the other input of AND gate And1. The output of AND gate And1 is connected to one input of OR gate OR1. The output of inverter Inv4 is connected to the input of delay circuit DL1. The output of delay circuit DL1 is connected to the other input of AND gate And2. The output of AND gate And2 is connected to the other input of OR gate OR1. The output of OR gate OR1 is connected to the gates of PMOS MOSFETs MP7, MP8, MP9, and MP10. , 3. A low-power level shifting circuit for a power supply chip according to claim 1, characterized in that, The dynamic narrow pulse circuit (1) includes: inverter Inv1, inverter Inv2, NOR gate Nor1, NOR gate Nor2, NAND gate Nand1 and level drop circuit, wherein the input terminal of inverter Inv1 is connected to one input terminal of NOR gate Nor2 and the signal input terminal VIN respectively, the output terminal of inverter Inv1 is connected to one input terminal of NOR gate Nor1, the other input terminal of NOR gate Nor1 is connected to one input terminal of NAND gate Nand1 and the output terminal of level drop circuit respectively, the output terminal of NOR gate Nor1 is connected to the gate of NMOS transistor MN1 and the input terminal of inverter Inv2 respectively, the output terminal of inverter Inv2 is connected to the other input terminal of NAND gate Nand1, the output terminal of NAND gate Nand1 is connected to the other input terminal of NOR gate Nor2, and the output terminal of NOR gate Nor2 is connected to the gate of NMOS transistor MN2.

4. A low-power level shifting circuit for a power supply chip according to claim 2, characterized in that, In the level shift core circuit (1) that suppresses power transistor voltage surge noise, when the operating state of the power transistor on the power chip circuit changes, the external bootstrap capacitor between the signal terminal BST and the signal terminal SW enables the voltage of the signal terminal BST to quickly follow the voltage of the signal terminal SW. However, the parasitic capacitance at the gate of PMOS transistors MP1 and MP6 causes their gate voltage to fail to quickly follow the voltage of the signal terminal BST, thereby generating power transistor voltage surge noise, which leads to the power transistor on the power chip circuit being mistakenly turned on or off. To solve this problem, the present invention uses inverters Inv3, Inv4, Inv5, delay circuits DL1 and DL2, AND gate And1, AND gate And2, and OR gate O. The power transistor voltage surge noise suppression circuit, composed of R1, PMOS transistors MP7, MP8, MP9, and MP10, improves the reliability of the level shift circuit, thereby suppressing the problem of power transistors being mistakenly turned on or off in the power chip circuit due to power transistor voltage surge noise. High-voltage MOSFETs HMN1 and HMN2 isolate the high-voltage domain circuit and the constant-voltage domain circuit, preventing the constant-voltage MOSFET from being damaged and improving the transmission speed of the constant-voltage MOSFET. Inverters Inv8 and Inv9 form a latch, and PMOS transistors MP7, MP8, MP9, and MP10 suppress the injection of power transistor voltage surge noise into the latch.

5. A low-power level shifting circuit for a power supply chip according to claim 4, characterized in that, In the level shift core circuit (1) that suppresses voltage surge noise of power transistors, when the signal at the input terminal VIN changes from low to high, the signal at the circuit output terminal VOUT changes from low to high. The output terminal of AND gate And1 remains low, and the output terminal of AND gate And2 generates a narrow pulse signal at the rising edge of the signal at the circuit output terminal VOUT. At the same time, the output terminal of OR gate OR1 generates a narrow pulse signal and turns off PMOS transistors MP7, MP8, MP9, and MP10. The voltage surge noise generated by the power transistors on the power chip causes the current generated when PMOS transistors MP2, MP3, MP4, and MP5 are turned on through the signal terminal BST, which does not affect the output signal of the latch. Therefore, the circuit output terminal VOUT remains high. This improves the reliability of the level shifting circuit. When the input signal VIN changes from high to low, the output signal VOUT changes from high to low. The output of AND gate And2 remains low, and the output of AND gate And1 generates a narrow pulse signal at the rising edge of the output signal VOUT. At the same time, the output of OR gate OR1 generates a narrow pulse signal, which turns off PMOS transistors MP7, MP8, MP9, and MP10. The voltage surge noise generated by the power transistors on the power chip causes the current generated when PMOS transistors MP2, MP3, MP4, and MP5 are turned on through the signal terminal BST. This does not affect the output signal of the latch, so the output VOUT remains low, thereby improving the reliability of the level shifting circuit.

6. A low-power level shifting circuit for a power supply chip according to any one of claims 2-5, characterized in that, Too short a narrow pulse duration cannot guarantee the reliability of the circuit at various process corners, while too long a narrow pulse duration will increase power consumption and limit the minimum conduction time of the power chip system, thereby limiting its switching frequency and conversion ratio. To solve this problem, the present invention adopts the dynamic narrow pulse circuit (2) composed of a level-down circuit, inverter Inv1, inverter Inv2, NOR gate Nor1, NOR gate Nor2 and NAND gate Nand1. The level-down circuit converts the high power rail signal of the circuit output terminal VOUT into a low power rail signal and uses it as an input signal of NOR gate Nor1 and NAND gate Nand1. At the same time, it isolates the constant voltage domain circuit and the high voltage domain circuit to prevent the constant voltage MOS transistor from being broken down.

7. A low-power level shifting circuit for a power supply chip according to claim 6, characterized in that, During the process of the input signal VIN changing from high level to low level, the gate of NMOS transistor MN1 remains low level, causing NMOS transistor MN1 to be cut off. At this time, the initial level of the gate of NMOS transistor MN2 is low level. When the falling edge of the input signal VIN arrives, the gate of NMOS transistor MN2 becomes high level, causing NMOS transistor MN2 to be turned on. Through the level shifting core circuit (1) that suppresses power transistor voltage change noise, the circuit output VOUT becomes low level. The low level of the output VOUT, through the level falling circuit, NAND gate Nand1 and NOR gate Nor2, causes the gate of NMOS transistor MN2 to become low level, thereby generating a dynamic narrow pulse at the gate of NMOS transistor MN2. During the process of the input signal VIN changing from low level to high level, the gate of NMOS transistor MN2 remains low level. The NMOS transistor MN2 is turned off. At this time, the initial level of the gate of the NMOS transistor MN1 is low. When the rising edge of the signal at the input terminal VIN arrives, the gate of the NMOS transistor MN1 becomes high, which turns on the NMOS transistor MN1. The output terminal VOUT becomes high through the level shift core circuit (1) that suppresses the voltage change noise of the power transistor. The high level of the output terminal VOUT turns the gate of the NMOS transistor MN1 low through the level drop circuit and the NOT gate Nor1, thereby generating a dynamic narrow pulse at the gate of the NMOS transistor MN1. This achieves the dynamic narrow pulse mode to control the level shift core circuit (1) that suppresses the voltage change noise of the power transistor, improves the reliability of the level shift circuit, reduces the power consumption of the level shift circuit, and thus realizes a low-power level shift circuit suitable for power chips.

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