A low-jitter injection-locked phase-locked loop based on three-point injection and self-correction

Abstract

The application discloses a kind of low-jitter injection locking phase-locked loop based on three-point injection and self-correction, belongs to radio frequency integrated circuit technical field, by self-correction circuit regulation and control injection signal injection time and pulse width, introduce tail injection, direct injection and differential symmetrical injection three-point injection technology, through three-point injection technology, realize the synchronization shaping of injection signal to oscillation signal, do not introduce common-mode amplitude modulation, suppress reference spur, improve injection strength simultaneously, improve the jitter performance of phase-locked loop system;By linear pressure flow conversion, the voltage output by the high spur loop filter is converted into current, and a linear low-spur control voltage signal is formed through resistance, effectively suppressing system spur, the spur performance of phase-locked loop based on injection locking ring oscillator is significantly improved by the synergy of the two, a low-jitter low-spur injection locking phase-locked loop system with high timing accuracy is realized.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, specifically to a low-jitter injection-locked phase-locked loop based on three-point injection and self-calibration, which is suitable for high-frequency high-quality wireless communication systems, high-speed high-performance computing chips, and other scenarios requiring low jitter range. Background Technology

[0002] A phase-locked loop (PLL) is a precision electronic control loop that dynamically adjusts the frequency and phase of the output signal through closed-loop feedback to precisely lock onto the input reference signal. It produces a highly stable, low-noise output signal that is synchronized with the reference source. Its core applications include precise modulation and demodulation of radio frequency signals and carrier synchronization in high-quality wireless communication, as well as providing low-jitter clock signals for high-speed chips (such as processors and memory) in high-performance computing, ensuring the timing accuracy of data transmission. As a key technology in electronic engineering, the PLL provides crucial support for achieving precise timing control and signal integrity in complex systems through its superior frequency control and phase synchronization capabilities.

[0003] Phase-locked loops (PLLs) based on ring oscillators (ROLs) offer a wider frequency modulation range, allowing for flexible adaptation to the needs of multi-band communication and processing. Furthermore, the highly compact circuit structure of ring oscillators effectively reduces chip area usage and manufacturing costs. Since ring oscillators achieve positive feedback oscillation based on multi-stage phase shifting, they naturally support multi-phase clock output. However, PLLs based on ring oscillators have relatively poor spurious and jitter control. This high jitter directly leads to reduced clock signal timing accuracy. Ring oscillators also lack a high-Q resonant frequency selection structure, and their output is not an ideal sine wave; their output signal spectrum contains a large number of odd harmonic components in addition to the fundamental frequency, resulting in poor spurious performance. Injection-locked loops (PLLs), employing injection-locking technology, periodically inject signals into the oscillator to clear accumulated jitter, effectively improving the jitter performance of the PLL system and representing one method to address the inherent defects of ring oscillators. There is a technical contradiction between increasing injection strength and suppressing reference spurious signals. While excessive injection can significantly improve jitter performance, it will strongly modulate the amplitude and operating point of the oscillator output signal, introducing severe spurious signals. On the other hand, insufficient injection strength has little impact on spurious signals and cannot effectively eliminate jitter. At the same time, the output of the charge pump in the phase-locked loop system will also affect the spurious signals of the final output.

[0004] Therefore, overcoming the challenges of injection-locked structures, breaking through the inherent clock jitter and high spurious defects of ring oscillator phase-locked loops, and without sacrificing their key advantages such as tuning range and integration density, so that they can meet the stringent timing accuracy requirements of applications such as high-quality wireless communication and high-performance computing, is a key technical challenge that researchers in this field urgently need to solve. Summary of the Invention

[0005] This invention proposes a low-jitter injection-locked phase-locked loop (PLL) based on three-point injection and stable voltage, wherein the injection-locked PLL comprises: The injection path includes an injection pulse generator, a third NOT gate, and a transmission gate. The input terminal of the injection pulse generator is connected to a reference signal, its first output terminal is connected to the input terminal of the third NOT gate, and its second output terminal is connected to the input terminal of the transmission gate. The output terminal of the third NOT gate outputs a first injection signal, and the output terminal of the transmission gate outputs a second injection signal. The self-calibrating circuit has an input terminal connected to a first injection signal, an oscillation signal, and a reference signal, and an output terminal outputting a first control signal and a second control signal to the injection pulse generator for adjusting the injection time and pulse width of the first injection signal and the second injection signal. An injection-locked ring oscillator includes a first ring oscillator unit, a second ring oscillator unit, and a third ring oscillator unit. The input terminal of each ring oscillator unit is connected to a control voltage signal, a first injection signal, and a second injection signal. The first injection signal is directly injected into each ring oscillator unit, and the second injection signal is injected into each ring oscillator unit in a differential symmetrical manner. The differential symmetrical injection adopts narrow pulse pair injection to generate symmetrical injection action during the injection process, realize the synchronous shaping of the oscillation signal by the injection signal, and avoid the reference spurious introduced by the amplitude modulation of the oscillation signal by the injection signal. A linear voltage-to-current converter outputs a control voltage signal to the injection-locked ring oscillator to convert the voltage output from the preceding loop filter into current and form a linear, low-spurious control voltage signal through a resistor.

[0006] Furthermore, through the synergistic effect of the three-point injection technology and the linear voltage-current converter, the system spurious performance of the phase-locked loop reaches below -66.5dBc.

[0007] Furthermore, the self-calibration circuit includes an injection time calibration circuit and an injection pulse width calibration circuit. The injection time calibration circuit has its input terminal connected to a first injection signal and an oscillation signal, and its output terminal outputs a first control signal to the injection pulse generator for adjusting the injection time of the injection signal. The injection pulse width calibration circuit has its input terminal connected to a reference signal and a first injection signal, and its output terminal outputs a second control signal to the injection pulse generator for adjusting the pulse width of the injection signal.

[0008] Furthermore, the injection pulse generator includes a first voltage-controlled delay line, a second voltage-controlled delay line, and an AND gate. The input terminal of the first voltage-controlled delay line is connected to a reference signal and a first control signal, and its output terminal is connected to the first input terminal of the second voltage-controlled delay line and the second input terminal of the AND gate. The second input terminal of the second voltage-controlled delay line is connected to a second control signal, and its output terminal is connected to the first input terminal of the AND gate. The output terminal of the AND gate is the output terminal of the injection pulse generator.

[0009] Furthermore, the injection time correction circuit includes a pulse generator, a delay unit, a first NOT gate, a second NOT gate, a first switch, a second switch, a third switch, a fourth switch, a first current source for the accumulator, a second current source for the accumulator, a first capacitor, a phase detector, and a D flip-flop. The phase detector's first input terminal is connected to a first injection signal, its second input terminal is connected to an oscillation signal, and its output terminal is connected to the D input terminal of the D flip-flop. The D flip-flop's clock input terminal is connected to the FE1 signal, and its output terminal generates a DE signal, which is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate controls the first switch to turn off, and the DE signal controls the second switch to turn off. The pulse generator's input terminal is connected to the oscillation signal, and its output terminal generates an FE1 signal, which is connected to the input terminal of the delay unit. The delay unit's output terminal is connected to the input terminal of the first NOT gate and one end of the second switch. The output terminal of the first NOT gate is connected to one end of the first switch. The first switch controls the third switch to turn off, and the second switch controls the fourth switch to turn off. One end of the accumulator's first current source is connected to a power supply, and its other end is connected to one end of the third switch. One end of the accumulator's second current source is connected to one end of the fourth switch, and its other end is grounded. The other end of the third switch is connected to the other end of the fourth switch, and is also connected to one end of the first capacitor, which serves as the output terminal of the injection time correction circuit. The other end of the first capacitor is grounded.

[0010] Furthermore, the injected pulse width correction circuit includes a fifth switch, a sixth switch, a first current source, a second current source, and a second capacitor; one end of the first current source is connected to a power supply, and the other end is connected to one end of the fifth switch; one end of the second current source is grounded, and the other end is connected to one end of the sixth switch; the other end of the fifth switch is connected to the other end of the sixth switch and one end of the second capacitor, and serves as the output terminal of the injected pulse width correction circuit; the other end of the second capacitor is grounded. In the injected pulse width correction circuit, the first injected signal controls the sixth switch to turn off, the reference signal controls the fifth switch to turn off, and the current ratio of the first current source to the second current source is 1:2N, where N is the frequency division ratio of the frequency divider.

[0011] Furthermore, in the injection-locked ring oscillator, the first input terminal of the first ring oscillator unit is connected to the second output terminal of the third ring oscillator unit, the second input terminal of the first ring oscillator unit is connected to the first output terminal of the third ring oscillator unit, the first output terminal of the first ring oscillator unit is connected to the first input terminal of the second ring oscillator unit, and its second output terminal is connected to the second input terminal of the second ring oscillator unit; the first output terminal of the second ring oscillator unit is connected to the first input terminal of the third ring oscillator unit, and its second output terminal is connected to the second input terminal of the third ring oscillator unit; the third input terminals of the first ring oscillator unit, the second ring oscillator unit, and the third ring oscillator unit are all connected to the first injection signal, and their fourth input terminals are all connected to the second injection signal; the fifth input terminals of the first ring oscillator unit, the second ring oscillator unit, and the third ring oscillator unit are all connected to the control voltage signal.

[0012] Furthermore, each of the ring resonator units includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a sixteenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; The gate of the first NMOS transistor is connected to the gate of the first PMOS transistor and serves as the second input terminal of each ring resonator. The source of the first NMOS transistor is grounded, and its drain is connected to the drain of the first PMOS transistor and serves as the second output terminal of each ring resonator. The gate of the second NMOS transistor is connected to the gate of the second PMOS transistor and serves as the first input terminal of each ring resonator. The source of the second NMOS transistor is grounded, and its drain is connected to the drain of the second PMOS transistor and serves as the first output terminal of each ring resonator. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, the second injection signal, and the control voltage signal. The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the third PMOS transistor is connected to the source of the second PMOS transistor, and the drain of the fourth PMOS transistor is connected to the source of the first PMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fifth PMOS transistor and the first output terminal of each ring oscillator unit. The source of the third NMOS transistor is grounded, and its drain is connected to the source of the fourth NMOS transistor. The gates of the fourth NMOS transistor and the eighth PMOS transistor are both connected to a first injection signal. The drain of the fourth NMOS transistor is connected to the drain of the sixth PMOS transistor and the second output terminal of each ring oscillator unit. The source of the fifth PMOS transistor is connected to a power supply, and its drain is connected to the source of the sixth PMOS transistor. The gates of the sixth PMOS transistor and the sixth NMOS transistor are both connected to a second injection signal. The gate of the fifth NMOS transistor is connected to the gate of the seventh PMOS transistor and the second output terminal of each ring oscillator unit. The source of the fifth NMOS transistor is grounded, and its drain is connected to the source of the sixth NMOS transistor. The drain of the sixth NMOS transistor is connected to the drain of the eighth PMOS transistor and the first output terminal of each ring oscillator unit. The source of the eighth PMOS transistor is connected to the drain of the seventh PMOS transistor, and the source of the seventh PMOS transistor is connected to a power supply. The gate of the sixteenth NMOS transistor is connected to the first injection signal, its source is connected to the second output terminal of each ring oscillator, and its drain is connected to the first output terminal of each ring oscillator.

[0013] Furthermore, the injection-locked phase-locked loop also includes a subsampling phase detector, a transconductance module, a loop filter, a buffer, a charge pump, a frequency detector, a frequency divider, and a first resistor; The input terminal of the frequency and phase detector is connected to the output terminal of the frequency divider and the reference signal. The output terminal of the frequency and phase detector is connected to the input terminal of the charge pump. The output terminal of the charge pump is connected to the input terminal of the loop filter. The output terminal of the loop filter is connected to the first input terminal of the linear voltage-current converter. The second input terminal of the linear voltage-current converter is connected to its output terminal and one end of the first resistor. The output terminal of the linear voltage-current converter generates a control voltage signal. The other end of the first resistor is grounded. The output terminal of the injection-locked ring oscillator is connected to the input terminal of the frequency divider and the input terminal of the buffer. The input terminal of the subsampling phase detector is connected to the reference signal and the output terminal of the buffer. The output terminal of the subsampling phase detector is connected to the input terminal of the transconductance module. The output terminal of the transconductance module is connected to the input terminal of the loop filter. The subsampling phase detector, the transconductance module, the loop filter, the linear voltage-current converter, the first resistor, the injection-locked ring oscillator, and the buffer form a subsampling phase-locked loop; The frequency and phase detector, the charge pump, the loop filter, the linear voltage-current converter, the first resistor, the injection-locked ring oscillator, and the frequency divider form a frequency-locked loop.

[0014] Furthermore, the linear voltage-current converter adopts a double-folded common-source common-gate input structure, which includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a third capacitor, and a second resistor; The sources of the tenth and eleventh NMOS transistors are both grounded. The gate of the tenth NMOS transistor is connected to the gate of the eleventh NMOS transistor. The drain of the tenth NMOS transistor is connected to the drain of the tenth PMOS transistor and the source of the twelfth NMOS transistor. The drain of the eleventh NMOS transistor is connected to the drain of the ninth PMOS transistor and the source of the thirteenth NMOS transistor. The gate of the twelfth NMOS transistor is connected to the gate of the thirteenth NMOS transistor. The drain of the twelfth NMOS transistor is connected to the drain of the fourteenth PMOS transistor, the gate of the twelfth PMOS transistor, and the gate of the thirteenth PMOS transistor. The drain of the thirteenth NMOS transistor is connected to the drain of the fifteenth PMOS transistor. The circuit consists of a terminal of the second resistor, one end of the second resistor, the gate of the sixteenth PMOS transistor, and the gate of the nineteenth PMOS transistor. The gate of the fourteenth PMOS transistor is connected to the gate of the fifteenth PMOS transistor. The source of the fourteenth PMOS transistor is connected to the drain of the twelfth PMOS transistor and the drain of the seventh NMOS transistor. The source of the fifteenth PMOS transistor is connected to the drain of the thirteenth PMOS transistor and the drain of the eighth NMOS transistor. The gate of the twelfth PMOS transistor is connected to the gate of the thirteenth PMOS transistor. The sources of the twelfth and thirteenth PMOS transistors are both connected to the power supply. The other end of the second resistor is connected to one end of the third capacitor, and the other end of the third capacitor is connected to the power supply voltage. The gate of the ninth PMOS transistor is connected to the gate of the seventh NMOS transistor and serves as the first input terminal of the linear voltage-current converter. The gate of the tenth PMOS transistor is connected to the gate of the eighth NMOS transistor and serves as the second input terminal of the linear voltage-current converter. The sources of the ninth and tenth PMOS transistors are both connected to the drain of the eleventh PMOS transistor. The source of the eleventh PMOS transistor is connected to the power supply voltage, and its gate is connected to a second voltage. The sources of the seventh and eighth NMOS transistors are both connected to the drain of the ninth NMOS transistor. The source of the ninth NMOS transistor is grounded, and its gate is connected to a first voltage. Both the first and second voltages are bias voltages. The sources of the fourteenth and fifteenth NMOS transistors are both grounded. The gate of the fourteenth NMOS transistor is connected to the gate of the fifteenth NMOS transistor and the drain of the fourteenth NMOS transistor. The drain of the fourteenth NMOS transistor is connected to the gate and drain of the seventeenth PMOS transistor. The source of the seventeenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor, and the source of the sixteenth PMOS transistor is connected to the power supply voltage. The drain of the fifteenth NMOS transistor is connected to the drain and gate of the eighteenth PMOS transistor and the gate of the twentieth PMOS transistor. The source of the eighteenth PMOS transistor is connected to the power supply voltage, and its gate is connected to the gate of the twentieth PMOS transistor. The drain of the twentieth PMOS transistor is the output terminal of the linear voltage-current converter, and its source is connected to the drain of the nineteenth PMOS transistor, and the source of the nineteenth PMOS transistor is connected to the power supply voltage.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention improves injection intensity and suppresses jitter and spurious emissions in phase-locked loop (PLL) systems by implementing direct injection, tail injection, and differential symmetric injection. Specifically, through a three-point injection mechanism and a linear voltage-current converter, it successfully overcomes the jitter and spurious emission performance bottleneck of traditional ring oscillator PLLs, achieving a PLL system spurious emission performance below -66.5 dBc. This results in a PLL system with excellent timing accuracy, providing an effective technical solution for low-jitter and low-spurious emission design of ring oscillator PLLs, and laying a key technical foundation for next-generation high-quality wireless communication and high-performance computing technologies. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 The diagram shown is a schematic representation of a low-jitter injection-locked loop based on three-point injection and self-correction, as provided in the embodiments of this specification. Figure 2 The diagram shown is a schematic diagram of the ring resonator unit circuit provided in the embodiment of this specification; Figure 3 The diagram shown is a schematic of the self-calibration circuit provided in the embodiment of this specification. Figure 4 The diagram shown is a schematic of a linear voltage-current converter circuit provided in an embodiment of this specification. Figure 5 The image shown is a comparison chart of injection intensity provided in the examples in this manual; Figure 6 The figure shown is the output spectrum of the phase-locked loop provided in the example of this specification without three-point injection; Figure 7The output spectrum of the phase-locked loop provided in this specification under three-point injection is shown. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] The low-jitter injection-locked phase-locked loop based on three-point injection and self-correction of the present invention is specifically implemented in the following manner.

[0019] like Figure 1 As shown, this invention proposes a low-jitter injection-locked loop based on three-point injection and self-calibration, including an injection path comprising an injection pulse generator, a third NOT gate, and a transmission gate. The input terminal of the injection pulse generator is connected to a reference signal REF, its first output terminal is connected to the input terminal of the third NOT gate, its second output terminal is connected to the input terminal of the transmission gate, the output terminal of the third NOT gate outputs a first injection signal INJ_N, and the output terminal of the transmission gate outputs a second injection signal INJ_P. The self-calibrating circuit has its input terminal connected to the first injection signal INJ_N, the oscillation signal OUT_N and the reference signal REF, and its output terminal outputs the first control signal VC1 and the second control signal VC2 to the injection pulse generator to adjust the injection time and pulse width of the first injection signal INJ_N and the second injection signal INJ_P. An injection-locked ring oscillator is provided, comprising a first ring oscillator unit, a second ring oscillator unit, and a third ring oscillator unit. Each ring oscillator unit is connected to a control voltage signal VC, a first injection signal INJ_N, and a second injection signal INJ_P at its input. The first injection signal INJ_N is directly injected into each ring oscillator unit, and the second injection signal INJ_P is injected into each ring oscillator unit via differential symmetric injection. The three-point injection technique consists of direct injection, tail injection, and differential symmetric injection. The differential symmetric injection employs narrow pulse injection to generate symmetrical injection actions during the injection process, thereby achieving synchronous shaping of the oscillation signal by the injected signal and avoiding reference spurious signals introduced by amplitude modulation of the oscillation signal by the injected signal. The linear voltage-to-current converter V2I outputs a control voltage signal VC to the injection-locked loop oscillator, which converts the voltage output from the front-end loop filter into current and forms a linear low-spurious control voltage signal through a resistor to suppress additional low-frequency spurious signals introduced into the injection-locked loop. By combining the three-point injection technique with the self-calibration circuit, the injection strength of the injected signal is improved. Furthermore, by combining the three-point injection technique with the linear voltage-to-current converter (V2I), the ability to suppress jitter and spurious signals in the phase-locked loop (PLL) system is enhanced, enabling the PLL system spurious performance to reach below -66.5 dBc.

[0020] In some embodiments of the present invention, the injection pulses generated by the pulse generator on the injection path are adjusted by a self-calibrating path to obtain the optimal injection time and injection pulse width, thereby improving the injection intensity. The first injection signal INJ_N and the second injection signal INJ_P are injected into the ring oscillator in a coordinated manner through direct injection, tail injection, and differential symmetrical injection using a three-point injection technique. The differential symmetrical injection uses narrow pulse pairs to compensate for the spurious side effects caused by strong injection. While achieving low jitter by utilizing injection, low spurious performance is also achieved. At the same time, a linear voltage-to-current converter V2I is added after the loop filter to convert the voltage output of the loop filter back into current, which is then used to form a linear low spurious control voltage signal through a resistor. This synergistically achieves low jitter and low spurious performance of the phase-locked loop system.

[0021] Specifically, the self-calibration circuit includes an injection time calibration circuit and an injection pulse width calibration circuit. The input of the injection time calibration circuit is connected to the first injection signal INJ_N and the oscillation signal OUT_N, and its output outputs the first control signal VC1 to the injection pulse generator to adjust the injection time of the injection signal. The input of the injection pulse width calibration circuit is connected to the reference signal REF and the first injection signal INJ_N, and its output outputs the second control signal VC2 to the injection pulse generator to adjust the pulse width of the injection signal.

[0022] The injection pulse generator includes a first voltage-controlled delay line VCDL1, a second voltage-controlled delay line VCDL2, and an AND gate. The input of the first voltage-controlled delay line VCDL1 is connected to the reference signal REF and the first control signal VC1, and its output is connected to the first input of the second voltage-controlled delay line VCDL2 and the second input of the AND gate. The second input of the second voltage-controlled delay line VCDL2 is connected to the second control signal VC2, and its output is connected to the first input of the AND gate. The output of the AND gate is the output of the injection pulse generator.

[0023] like Figure 3As shown, the injection time correction circuit includes a pulse generator, a delay unit, a first NOT gate INV1, a second NOT gate INV2, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a first current source for an accumulator, a second current source for an accumulator, a first capacitor C1, a phase detector (Bang-Bang Phase Detector BBPD), and a D flip-flop. The first input terminal of the phase detector BBPD is connected to the first injection signal INJ_N, its second input terminal is connected to the oscillation signal OUT_N, and its output terminal is connected to the D input terminal of the D flip-flop. The clock input terminal of the D flip-flop is connected to the FE1 signal, and its output terminal generates the DE signal, which is connected to the input terminal of the second NOT gate INV2. The output terminal of the second NOT gate INV2 controls the first switch SW1 to turn off, and the DE signal controls the second switch SW2 to turn off. The input terminal of the pulse generator is connected to the oscillation signal OUT_N, and its output terminal generates the FE1 signal, which is connected to the input terminal of the delay unit. The output terminal of the delay unit is connected to the first NOT gate I... The input terminal of NV1 and one end of the second switch SW2 are connected to one end of the first switch SW1. The output terminal of the first NOT gate INV1 is connected to one end of the first switch SW1. The first switch SW1 controls the third switch SW3 to turn off, and the second switch SW2 controls the fourth switch SW4 to turn off. One end of the first current source of the accumulator is connected to the power supply, and the other end is connected to one end of the third switch SW3. One end of the second current source of the accumulator is connected to one end of the fourth switch SW4, and the other end of the second current source of the accumulator is grounded. The other end of the third switch SW3 is connected to the other end of the fourth switch SW4, and is also connected to one end of the first capacitor C1, which is the output terminal of the injection time correction circuit. The other end of the first capacitor C1 is grounded.

[0024] In some embodiments of the present invention, when the rising edge of the first injected signal INJ_N is not aligned with the zero-crossing point of the oscillation signal OUT_N, the phase detector BBPD detects the phase error information between the first injected signal INJ_N and the oscillation signal OUT_N, and outputs an error signal ER. The FE1 signal generated by the pulse generator from the oscillation signal OUT_N is the sampling clock of the D flip-flop. After a delay, FE1 generates a PUL signal. The sampling output DE signal of the D flip-flop controls the transmission of the PUL signal, and the PUL signal controls the switching of the first current source and the second current source of the accumulator. The current source output is converted into a first control signal VC1 through the first capacitor C1, which controls the delay of the first voltage-controlled delay line VCDL1, thereby controlling the generation time of the first injected signal INJ_N and realizing injection time correction.

[0025] like Figure 3As shown, the injection pulse width correction circuit includes a fifth switch SW5, a sixth switch SW6, a first current source, a second current source, and a second capacitor C2. One end of the first current source is connected to the power supply, and the other end is connected to one end of the fifth switch SW5. One end of the second current source is grounded, and the other end is connected to one end of the sixth switch SW6. The other end of the fifth switch SW5 is connected to the other end of the sixth switch SW6 and one end of the second capacitor C2, and serves as the output terminal of the injection pulse width correction circuit. The other end of the second capacitor C2 is grounded. In the injection pulse width correction circuit, the first injection signal INJ_N controls the sixth switch SW6 to turn off, the reference signal REF controls the fifth switch SW5 to turn off, and the current ratio of the first current source to the second current source is 1:2N, where N is the frequency division ratio of the frequency divider.

[0026] In some embodiments of the present invention, when the injected pulse width does not reach the optimal width, i.e., 1 / 4 of the oscillation signal period, the currents of the two current sources in the pulse width correction circuit are different, which will generate a second control signal VC2 at the capacitor terminal. This control signal VC2 controls the delay of the second voltage-controlled delay line VCDL2, thereby adjusting the pulse width. Since the signal controlling the first current source switch in the pulse width correction circuit is the reference signal REF, and the signal controlling the second current source switch is the first injection signal INJ_N, and after frequency locking is completed, the period of the reference signal REF is N times the oscillation signal period, and the effective time of the reference signal REF is 2N oscillation signal periods, therefore, to control the pulse width of the first injection signal INJ_N to be 1 / 4 of the oscillation signal period, the current ratio of the first current source and the second current source should be 1:2N.

[0027] Specifically, in the injection-locked ring oscillator, the first input terminal of the first ring oscillator unit is connected to the second output terminal of the third ring oscillator unit, the second input terminal of the first ring oscillator unit is connected to the first output terminal of the third ring oscillator unit, the first output terminal of the first ring oscillator unit is connected to the first input terminal of the second ring oscillator unit, and its second output terminal is connected to the second input terminal of the second ring oscillator unit; the first output terminal of the second ring oscillator unit is connected to the first input terminal of the third ring oscillator unit, and its second output terminal is connected to the second input terminal of the third ring oscillator unit; the third input terminals of the first, second, and third ring oscillator units are all connected to the first injection signal INJ_N, their fourth input terminals are all connected to the second injection signal INJ_P, and the fifth input terminals of the first, second, and third ring oscillator units are all connected to the control voltage signal VC.

[0028] like Figure 2As shown, each ring oscillator unit includes a first NMOS transistor n1, a second NMOS transistor n2, a third NMOS transistor n3, a fourth NMOS transistor n4, a fifth NMOS transistor n5, a sixth NMOS transistor n6, a sixteenth NMOS transistor n16, a first PMOS transistor p1, a second PMOS transistor p2, a third PMOS transistor p3, a fourth PMOS transistor p4, a fifth PMOS transistor p5, a sixth PMOS transistor p6, a seventh PMOS transistor p7, and an eighth PMOS transistor p8. The gate of the first NMOS transistor n1 is connected to the gate of the first PMOS transistor p1 and serves as the second input terminal of each ring oscillator unit. The source of the first NMOS transistor n1 is grounded, and its drain... The first PMOS transistor p1 is connected to the drain of the first PMOS transistor p1 and serves as the second output terminal of each ring oscillator unit; the second NMOS transistor p2 is connected to the gate of the second PMOS transistor p2 and serves as the first input terminal of each ring oscillator unit, with its source grounded and its drain connected to the drain of the second PMOS transistor p2, serving as the first output terminal of each ring oscillator unit; the third PMOS transistor p3 is connected to the gate of the fourth PMOS transistor p4, the second injection signal INJ_P, and the control voltage signal VC; the third PMOS transistor p3 is connected to the source of the fourth PMOS transistor p4; the third PMOS transistor p3 is connected to the source of the second PMOS transistor p2; and the fourth PMOS transistor p4 is connected to the drain of the fourth PMOS transistor p4. The first NMOS transistor p1 is connected to the source of the first PMOS transistor p1; the gate of the third NMOS transistor n3 is connected to the gate of the fifth PMOS transistor p5 and the first output terminal of each ring oscillator unit, the source of the third NMOS transistor n3 is grounded, and its drain is connected to the source of the fourth NMOS transistor n4; the gates of the fourth NMOS transistor n4 and the eighth PMOS transistor p8 are both connected to the first injection signal INJ_N, and the drain of the fourth NMOS transistor n4 is connected to the drain of the sixth PMOS transistor p6 and the second output terminal of each ring oscillator unit; the source of the fifth PMOS transistor p5 is connected to the power supply, and its drain is connected to the source of the sixth PMOS transistor p6; the gates of the sixth PMOS transistor p6 and the sixth NMOS transistor n6 are both connected to the second... The injection signal is INJ_P; the gate of the fifth NMOS transistor n5 is connected to the gate of the seventh PMOS transistor p7 and the second output terminal of each ring oscillator unit, the source of the fifth NMOS transistor n5 is grounded, its drain is connected to the source of the sixth NMOS transistor n6, the drain of the sixth NMOS transistor n6 is connected to the drain of the eighth PMOS transistor p8 and the first output terminal of each ring oscillator unit; the source of the eighth PMOS transistor p8 is connected to the drain of the seventh PMOS transistor p7, and the source of the seventh PMOS transistor p7 is connected to the power supply; the gate of the sixteenth NMOS transistor n16 is connected to the first injection signal INJ_N, its source is connected to the second output terminal of each ring oscillator unit, and its drain is connected to the first output terminal of each ring oscillator unit.

[0029] In some embodiments of the present invention, in the three-point injection technique, when the first injection signal INJ_N is high, the second injection signal INJ_P is low. At this time, the fourth NMOS transistor n4 and the sixth PMOS transistor p6 are turned on, and the sixth NMOS transistor n6 and the eighth PMOS transistor p8 are turned off. If the first output terminal is high and the second output terminal is low at this time, the third NMOS transistor n3 is turned on and the fifth PMOS transistor p5 is turned off. Differential symmetrical injection tends to maintain the existing output state. At this time, the third PMOS transistor p3 and the fourth PMOS transistor p4 are turned on, and the current flows through the first NMOS transistor n1, the first PMOS transistor p1, and the second NMOS transistor n2; the second PMOS transistor... As the current in p2 increases, the oscillation frequency accelerates, and the directly injected sixteenth NMOS transistor n16 turns on, creating a path between the first and second output terminals, thus accelerating the output switching. Therefore, tail injection and direct injection tend to pull the oscillation signal forward, while differential symmetrical injection tends to pull the oscillation signal backward, producing symmetrical action and avoiding reference spurious signals introduced by amplitude modulation of the oscillation signal by the injected signal. In addition, the three-point injection technique is a synergistic injection mechanism. Differential symmetrical injection allows direct injection and tail injection to operate in a strong state, while differential injection compensates for the spurious side effects caused by strong injection. It achieves low jitter and low spurious performance while utilizing injection.

[0030] Specifically, the injection-locked phase-locked loop also includes a subsampling phase detector, a transconductance module Gm, a loop filter, a buffer, a charge pump, a frequency-phase detector, a frequency divider, and a first resistor r1. The input of the frequency-phase detector is connected to the output of the frequency divider and the reference signal REF. The output of the frequency-phase detector is connected to the input of the charge pump. The output of the charge pump is connected to the input of the loop filter. The output of the loop filter is connected to the first input of the linear voltage-current converter V2I. The second input of the linear voltage-current converter V2I is connected to its output and one end of the first resistor r1. The output of the linear voltage-current converter V2I generates a control voltage signal VC. The other end of the first resistor r1 is grounded. The output of the injection-locked ring oscillator is connected to the input of the frequency divider and the input of the buffer. The input of the subsampling phase detector is connected to the reference signal REF and the output of the buffer. The output of the subsampling phase detector is connected to the input of the transconductance module Gm. The output of the transconductance module Gm is connected to the input of the loop filter. The subsampling phase detector, the transconductance module Gm, the loop filter, the linear voltage-current converter V2I, the first resistor r1, the injection-locked ring oscillator and the buffer form a subsampling phase-locked loop. The frequency-locked phase detector, the charge pump, the loop filter, the linear voltage-current converter V2I, the first resistor r1, the injection-locked ring oscillator and the frequency divider form a frequency-locked loop.

[0031] In some embodiments of the present invention, the phase and frequency locking of the phase-locked loop is completed collaboratively by the subsampling loop and the frequency-locking loop. In the initial stage of the system, the frequency-locking loop is responsible for completing the frequency locking. When the frequency stabilizes, the frequency-locking loop automatically exits the work, and the subsampling phase-locked loop takes over to perform subsequent phase tracking, ultimately achieving precise locking.

[0032] like Figure 4As shown, the linear voltage-to-current converter V2I includes the seventh NMOS transistor n7, the eighth NMOS transistor n8, the ninth NMOS transistor n9, the tenth NMOS transistor n10, the eleventh NMOS transistor n11, the twelfth NMOS transistor n12, the thirteenth NMOS transistor n13, the fourteenth NMOS transistor n14, the fifteenth NMOS transistor n15, the ninth PMOS transistor p9, the tenth PMOS transistor p10, the eleventh PMOS transistor p11, the twelfth PMOS transistor p12, the thirteenth PMOS transistor p13, the fourteenth PMOS transistor p14, the fifteenth PMOS transistor p15, the sixteenth PMOS transistor p16, the seventeenth PMOS transistor p17, and the eighteenth PMOS transistor p18. The nineteenth PMOS transistor p19, the twentieth PMOS transistor p20, the third capacitor c3, and the second resistor r2; the source of the tenth NMOS transistor n10 and the source of the eleventh NMOS transistor n11 are both grounded, the gate of the tenth NMOS transistor n10 is connected to the gate of the eleventh NMOS transistor n11, the drain of the tenth NMOS transistor n10 is connected to the drain of the tenth PMOS transistor p10 and the source of the twelfth NMOS transistor n12, the drain of the eleventh NMOS transistor n11 is connected to the drain of the ninth PMOS transistor p9 and the source of the thirteenth NMOS transistor n13, the gate of the twelfth NMOS transistor n12 is connected to the gate of the thirteenth NMOS transistor n13, and the drain of the twelfth NMOS transistor n12 is connected to the fourteenth PMOS transistor p1. 4. Drain of PMOS transistor p12, gate of PMOS transistor p12, and gate of PMOS transistor p13. Drain of PMOS transistor n13 is connected to drain of PMOS transistor p15, one end of the second resistor r2, gate of PMOS transistor p16, and gate of PMOS transistor p19. Gate of PMOS transistor p14 is connected to gate of PMOS transistor p15. Source of PMOS transistor p14 is connected to drain of PMOS transistor p12 and drain of PMOS transistor n7. Source of PMOS transistor p15 is connected to drain of PMOS transistor p13 and drain of PMOS transistor n8. Gate of PMOS transistor p12 is connected to PMOS transistor p13. The gate of P13, the source of the twelfth PMOS transistor P12, and the source of the thirteenth PMOS transistor P13 are all connected to the power supply; the other end of the second resistor R2 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is connected to the power supply voltage; the gate of the ninth PMOS transistor P9 is connected to the gate of the seventh NMOS transistor N7 and serves as the first input terminal of the linear voltage-current converter V2I; the gate of the tenth PMOS transistor P10 is connected to the gate of the eighth NMOS transistor N8 and serves as the second input terminal of the linear voltage-current converter V2I; the sources of the ninth PMOS transistor P9 and the tenth PMOS transistor P10 are both connected to the drain of the eleventh PMOS transistor P11, the source of the eleventh PMOS transistor P11 is connected to the power supply voltage, and its gate is connected to the second voltage V. b2The sources of the seventh NMOS transistor n7 and the eighth NMOS transistor n8 are both connected to the drain of the ninth NMOS transistor n9. The source of the ninth NMOS transistor n9 is grounded, and its gate is connected to the first voltage V. b1 First voltage V b1 Second voltage V b2 All are bias voltages; the source of the fourteenth NMOS transistor n14 and the source of the fifteenth NMOS transistor n15 are both grounded. The gate of the fourteenth NMOS transistor n14 is connected to the gate of the fifteenth NMOS transistor n15 and the drain of the fourteenth NMOS transistor n14. The drain of the fourteenth NMOS transistor n14 is connected to the gate and drain of the seventeenth PMOS transistor p17. The source of the seventeenth PMOS transistor p17 is connected to the drain of the sixteenth PMOS transistor p16. The source of the sixteenth PMOS transistor p16 is connected to the power supply voltage. The drain of the fifteenth NMOS transistor n15 is connected to the drain and gate of the eighteenth PMOS transistor p18 and the gate of the twentieth PMOS transistor p20. The source of the eighteenth PMOS transistor p18 is connected to the power supply voltage, and its gate is connected to the gate of the twentieth PMOS transistor p20. The drain of the twentieth PMOS transistor p20 is the output terminal of the linear voltage-current converter V2I, and its source is connected to the drain of the nineteenth PMOS transistor p19. The source of the nineteenth PMOS transistor p19 is connected to the power supply voltage.

[0033] In some embodiments of the present invention, the linear voltage-to-current converter V2I employs a double-folded cascode input, avoiding the limited input range problem of single-ended differential input while improving output gain. Since the charge pump's charging and discharging current is prone to mismatch due to external fluctuations, it injects net charge into the loop filter during each phase detection cycle, generating periodic ripple that modulates the output of the injection-locked ring oscillator, producing spurious signals. Furthermore, charge injection occurs when the charge pump switches on and off, generating high-frequency glitches. If these glitches cannot be adequately filtered out by the loop filter, they will form broadband spurious signals. Therefore, a linear voltage-to-current converter is added after the loop filter to convert the voltage output of the loop filter back into current, forming a linear, low-spurious-signal control voltage signal VC through a second resistor r2.

[0034] This invention improves the injection intensity and accelerates the establishment of the oscillation signal edge through a three-point injection technique; for example... Figure 5 As shown, compared to tail injection and tail injection + direct injection, the injection intensity is increased by 166.4% and 14.3% respectively. Furthermore, the differential symmetrical injection signal is a pair of narrow pulse signals, avoiding the interference of wide pulse signals on adjacent oscillation periods and the deterioration of spurious signals. Simultaneously, the increased injection intensity enhances the jitter suppression capability of the phase-locked loop system, achieving low jitter, as shown... Figure 6 and 7As can be seen from the output spectrum of the phase-locked loop, compared with the use of a linear voltage-current converter alone, the phase-locked loop without the three-point injection technology can reduce the system spurious performance to -61.4dBc. However, through the synergistic effect of the three-point injection technology and the linear voltage-current converter, an even lower spurious control voltage signal can be achieved, reducing the system spurious performance to -66.5dBc.

Claims

1. A low-jitter injection-locked phase-locked loop based on three-point injection and self-calibration, characterized in that, The injection-locked phase-locked loop includes: The injection path includes an injection pulse generator, a third NOT gate, and a transmission gate. The input terminal of the injection pulse generator is connected to a reference signal, its first output terminal is connected to the input terminal of the third NOT gate, and its second output terminal is connected to the input terminal of the transmission gate. The output terminal of the third NOT gate outputs a first injection signal, and the output terminal of the transmission gate outputs a second injection signal. The self-calibrating circuit has an input terminal connected to a first injection signal, an oscillation signal, and a reference signal, and an output terminal outputting a first control signal and a second control signal to the injection pulse generator for adjusting the injection time and pulse width of the first injection signal and the second injection signal. An injection-locked ring oscillator includes a first ring oscillator unit, a second ring oscillator unit, and a third ring oscillator unit. The input terminal of each ring oscillator unit is connected to a control voltage signal, a first injection signal, and a second injection signal. The first injection signal is directly injected into each ring oscillator unit, and the second injection signal is injected into each ring oscillator unit in a differential symmetrical manner. The differential symmetrical injection adopts narrow pulse pair injection to generate symmetrical injection action during the injection process, realize the synchronous shaping of the oscillation signal by the injection signal, and avoid the reference spurious introduced by the amplitude modulation of the oscillation signal by the injection signal. A linear voltage-to-current converter outputs a control voltage signal to the injection-locked ring oscillator to convert the voltage output from the preceding loop filter into current and form a linear, low-spurious control voltage signal through a resistor.

2. The low-jitter injection-locked phase-locked loop based on three-point injection and self-correction according to claim 1, characterized in that, Through the synergistic effect of three-point injection technology and linear voltage-current converter, the system spurious performance of the phase-locked loop reaches below -66.5dBc.

3. A low-jitter injection-locked phase-locked loop based on three-point injection and self-correction as described in claim 1, characterized in that, The self-calibration circuit includes an injection time calibration circuit and an injection pulse width calibration circuit. The injection time calibration circuit has an input terminal connected to a first injection signal and an oscillation signal, and an output terminal outputting a first control signal to the injection pulse generator for adjusting the injection time of the injection signal. The injection pulse width calibration circuit has an input terminal connected to a reference signal and a first injection signal, and an output terminal outputting a second control signal to the injection pulse generator for adjusting the pulse width of the injection signal.

4. A low-jitter injection-locked phase-locked loop based on three-point injection and self-correction as described in claim 3, characterized in that, The injection pulse generator includes a first voltage-controlled delay line, a second voltage-controlled delay line, and an AND gate. The input terminal of the first voltage-controlled delay line is connected to a reference signal and a first control signal, and its output terminal is connected to the first input terminal of the second voltage-controlled delay line and the second input terminal of the AND gate. The second input terminal of the second voltage-controlled delay line is connected to a second control signal, and its output terminal is connected to the first input terminal of the AND gate. The output terminal of the AND gate is the output terminal of the injection pulse generator.

5. A low-jitter injection-locked phase-locked loop based on three-point injection and self-correction according to claim 3, characterized in that, The injection time correction circuit includes a pulse generator, a delay unit, a first NOT gate, a second NOT gate, a first switch, a second switch, a third switch, a fourth switch, a first current source for the accumulator, a second current source for the accumulator, a first capacitor, a phase detector, and a D flip-flop. The phase detector's first input terminal is connected to a first injection signal, its second input terminal is connected to an oscillation signal, and its output terminal is connected to the D input terminal of the D flip-flop. The D flip-flop's clock input terminal is connected to the FE1 signal, and its output terminal generates a DE signal, which is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate controls the first switch to turn off, and the DE signal controls the second switch to turn off. The pulse generator's input terminal is connected to the oscillation signal, and its output terminal generates an FE1 signal, which is connected to the input terminal of the delay unit. The delay unit's output terminal is connected to the input terminal of the first NOT gate and one end of the second switch. The output terminal of the first NOT gate is connected to one end of the first switch. The first switch controls the third switch to turn off, and the second switch controls the fourth switch to turn off. One end of the first current source of the accumulator is connected to the power supply, and the other end is connected to one end of the third switch. One end of the second current source of the accumulator is connected to one end of the fourth switch, and the other end of the second current source of the accumulator is grounded. The other end of the third switch is connected to the other end of the fourth switch and is also connected to one end of the first capacitor, which is the output terminal of the injection time correction circuit. The other end of the first capacitor is grounded.

6. A low-jitter injection-locked phase-locked loop based on three-point injection and self-correction according to claim 3, characterized in that, The injected pulse width correction circuit includes a fifth switch, a sixth switch, a first current source, a second current source, and a second capacitor; one end of the first current source is connected to a power supply, and the other end is connected to one end of the fifth switch; one end of the second current source is grounded, and the other end is connected to one end of the sixth switch; the other end of the fifth switch is connected to the other end of the sixth switch and one end of the second capacitor, and is the output terminal of the injected pulse width correction circuit; the other end of the second capacitor is grounded. In the injected pulse width correction circuit, the first injected signal controls the sixth switch to turn off, the reference signal controls the fifth switch to turn off, and the current ratio of the first current source to the second current source is 1:2N, where N is the frequency division ratio of the frequency divider.

7. A low-jitter injection-locked phase-locked loop based on three-point injection and self-correction as described in claim 1, characterized in that, In the injection-locked ring oscillator, the first input terminal of the first ring oscillator unit is connected to the second output terminal of the third ring oscillator unit, the second input terminal of the first ring oscillator unit is connected to the first output terminal of the third ring oscillator unit, the first output terminal of the first ring oscillator unit is connected to the first input terminal of the second ring oscillator unit, and its second output terminal is connected to the second input terminal of the second ring oscillator unit; the first output terminal of the second ring oscillator unit is connected to the first input terminal of the third ring oscillator unit, and its second output terminal is connected to the second input terminal of the third ring oscillator unit; the third input terminals of the first ring oscillator unit, the second ring oscillator unit, and the third ring oscillator unit are all connected to the first injection signal, and their fourth input terminals are all connected to the second injection signal; the fifth input terminals of the first ring oscillator unit, the second ring oscillator unit, and the third ring oscillator unit are all connected to the control voltage signal.

8. A low-jitter injection-locked phase-locked loop based on three-point injection and self-correction according to claim 1, characterized in that, Each of the ring resonator units includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a sixteenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; The gate of the first NMOS transistor is connected to the gate of the first PMOS transistor and serves as the second input terminal of each ring resonator. The source of the first NMOS transistor is grounded, and its drain is connected to the drain of the first PMOS transistor and serves as the second output terminal of each ring resonator. The gate of the second NMOS transistor is connected to the gate of the second PMOS transistor and serves as the first input terminal of each ring resonator. The source of the second NMOS transistor is grounded, and its drain is connected to the drain of the second PMOS transistor and serves as the first output terminal of each ring resonator. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, the second injection signal, and the control voltage signal. The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the third PMOS transistor is connected to the source of the second PMOS transistor, and the drain of the fourth PMOS transistor is connected to the source of the first PMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fifth PMOS transistor and the first output terminal of each ring oscillator unit. The source of the third NMOS transistor is grounded, and its drain is connected to the source of the fourth NMOS transistor. The gates of the fourth NMOS transistor and the eighth PMOS transistor are both connected to a first injection signal. The drain of the fourth NMOS transistor is connected to the drain of the sixth PMOS transistor and the second output terminal of each ring oscillator unit. The source of the fifth PMOS transistor is connected to a power supply, and its drain is connected to the source of the sixth PMOS transistor. The gates of the sixth PMOS transistor and the sixth NMOS transistor are both connected to a second injection signal. The gate of the fifth NMOS transistor is connected to the gate of the seventh PMOS transistor and the second output terminal of each ring oscillator unit. The source of the fifth NMOS transistor is grounded, and its drain is connected to the source of the sixth NMOS transistor. The drain of the sixth NMOS transistor is connected to the drain of the eighth PMOS transistor and the first output terminal of each ring oscillator unit. The source of the eighth PMOS transistor is connected to the drain of the seventh PMOS transistor, and the source of the seventh PMOS transistor is connected to a power supply. The gate of the sixteenth NMOS transistor is connected to the first injection signal, its source is connected to the second output terminal of each ring oscillator, and its drain is connected to the first output terminal of each ring oscillator.

9. A low-jitter injection-locked phase-locked loop based on three-point injection and self-correction according to claim 1, characterized in that, The injection-locked phase-locked loop also includes a subsampling phase detector, a transconductance module, a loop filter, a buffer, a charge pump, a frequency detector, a frequency divider, and a first resistor; The input terminal of the frequency and phase detector is connected to the output terminal of the frequency divider and the reference signal. The output terminal of the frequency and phase detector is connected to the input terminal of the charge pump. The output terminal of the charge pump is connected to the input terminal of the loop filter. The output terminal of the loop filter is connected to the first input terminal of the linear voltage-current converter. The second input terminal of the linear voltage-current converter is connected to its output terminal and one end of the first resistor. The output terminal of the linear voltage-current converter generates a control voltage signal. The other end of the first resistor is grounded. The output terminal of the injection-locked ring oscillator is connected to the input terminal of the frequency divider and the input terminal of the buffer. The input terminal of the subsampling phase detector is connected to the reference signal and the output terminal of the buffer. The output terminal of the subsampling phase detector is connected to the input terminal of the transconductance module. The output terminal of the transconductance module is connected to the input terminal of the loop filter. The subsampling phase detector, the transconductance module, the loop filter, the linear voltage-current converter, the first resistor, the injection-locked ring oscillator, and the buffer form a subsampling phase-locked loop; The frequency and phase detector, the charge pump, the loop filter, the linear voltage-current converter, the first resistor, the injection-locked ring oscillator, and the frequency divider form a frequency-locked loop.

10. A low-jitter injection-locked phase-locked loop based on three-point injection and self-correction according to claim 9, characterized in that, The linear voltage-current converter adopts a double-folded common-source common-gate input structure, which includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a third capacitor, and a second resistor; The sources of the tenth and eleventh NMOS transistors are both grounded. The gate of the tenth NMOS transistor is connected to the gate of the eleventh NMOS transistor. The drain of the tenth NMOS transistor is connected to the drain of the tenth PMOS transistor and the source of the twelfth NMOS transistor. The drain of the eleventh NMOS transistor is connected to the drain of the ninth PMOS transistor and the source of the thirteenth NMOS transistor. The gate of the twelfth NMOS transistor is connected to the gate of the thirteenth NMOS transistor. The drain of the twelfth NMOS transistor is connected to the drain of the fourteenth PMOS transistor, the gate of the twelfth PMOS transistor, and the gate of the thirteenth PMOS transistor. The drain of the thirteenth NMOS transistor is connected to the drain of the fifteenth PMOS transistor. The circuit consists of a terminal of the second resistor, one end of the second resistor, the gate of the sixteenth PMOS transistor, and the gate of the nineteenth PMOS transistor. The gate of the fourteenth PMOS transistor is connected to the gate of the fifteenth PMOS transistor. The source of the fourteenth PMOS transistor is connected to the drain of the twelfth PMOS transistor and the drain of the seventh NMOS transistor. The source of the fifteenth PMOS transistor is connected to the drain of the thirteenth PMOS transistor and the drain of the eighth NMOS transistor. The gate of the twelfth PMOS transistor is connected to the gate of the thirteenth PMOS transistor. The sources of the twelfth and thirteenth PMOS transistors are both connected to the power supply. The other end of the second resistor is connected to one end of the third capacitor, and the other end of the third capacitor is connected to the power supply voltage. The gate of the ninth PMOS transistor is connected to the gate of the seventh NMOS transistor and serves as the first input terminal of the linear voltage-current converter. The gate of the tenth PMOS transistor is connected to the gate of the eighth NMOS transistor and serves as the second input terminal of the linear voltage-current converter. The sources of the ninth and tenth PMOS transistors are both connected to the drain of the eleventh PMOS transistor. The source of the eleventh PMOS transistor is connected to the power supply voltage, and its gate is connected to a second voltage. The sources of the seventh and eighth NMOS transistors are both connected to the drain of the ninth NMOS transistor. The source of the ninth NMOS transistor is grounded, and its gate is connected to a first voltage. Both the first and second voltages are bias voltages. The sources of the fourteenth and fifteenth NMOS transistors are both grounded. The gate of the fourteenth NMOS transistor is connected to the gate of the fifteenth NMOS transistor and the drain of the fourteenth NMOS transistor. The drain of the fourteenth NMOS transistor is connected to the gate and drain of the seventeenth PMOS transistor. The source of the seventeenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor, and the source of the sixteenth PMOS transistor is connected to the power supply voltage. The drain of the fifteenth NMOS transistor is connected to the drain and gate of the eighteenth PMOS transistor and the gate of the twentieth PMOS transistor. The source of the eighteenth PMOS transistor is connected to the power supply voltage, and its gate is connected to the gate of the twentieth PMOS transistor. The drain of the twentieth PMOS transistor is the output terminal of the linear voltage-current converter, and its source is connected to the drain of the nineteenth PMOS transistor, and the source of the nineteenth PMOS transistor is connected to the power supply voltage.

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