Multichannel signal processing device

Abstract

This invention provides a multi-channel signal processing device, belonging to the field of signal processing technology. The device includes multiple data converters for converting analog signals into digital signals or vice versa; a programmable logic chip connected to the data converters; a storage component; and a data processing platform connected to the programmable logic chip and the storage component via a high-speed bus. By employing multi-channel synchronous conversion and high-speed bus data scheduling, the throughput bottleneck of ultra-high bandwidth data acquisition and transmission is solved. This ultimately enables frequent, high-precision performance verification without the need to transport equipment to the field, significantly reducing verification costs and improving verification efficiency.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a multi-channel signal processing device. Background Technology

[0002] In real-world environments, WiFi signals are severely affected by reflections, multipath propagation, obstruction, and dynamic interference, impacting the performance of wearable devices.

[0003] To verify the actual performance of wearable devices, they need to be tested in a real-world environment.

[0004] However, if each verification of the actual performance of a wearable device requires placing it in a real environment for testing, and the wearable device needs to be moved around, this testing method is time-consuming and labor-intensive, and cannot meet the current need for frequent verification. Summary of the Invention

[0005] This invention provides a multi-channel signal processing device to solve the shortcomings of existing technologies that require setting up test environments and placing test equipment for on-site testing, which is time-consuming, labor-intensive, and has low testing efficiency. This invention enables testing in a laboratory environment, reducing testing costs while improving testing efficiency.

[0006] This invention provides a multi-channel signal processing device, comprising the following modules: Multiple data converters, the data converters being used to convert analog signals into digital signals or digital signals into analog signals; Programmable logic chip, connected to multiple of the aforementioned data converters; Storage components; A data processing platform, which is connected to the programmable logic chip and the storage component via a high-speed bus; The programmable logic chip acquires multiple bandwidth signals through multiple data converters and stores them in the storage component through the data processing platform; or the programmable logic chip reads multiple bandwidth signals stored in the storage component through the data processing platform and sends them out through multiple data converters.

[0007] According to a multi-channel signal processing apparatus provided by the present invention, the storage component includes: Storage array; A disk array card, one end of which is connected to the storage array, and the other end of which is connected to the data processing platform via the high-speed bus.

[0008] According to a multi-channel signal processing apparatus provided by the present invention, each of the data converters comprises: Analog-to-digital converter; Digital-to-analog converter; A switching switch, wherein the first end of the switching switch is connected to the digital output terminal of the analog-to-digital converter, the second end of the switching switch is connected to the digital input terminal of the digital-to-analog converter, and the third end of the switching switch is connected to the corresponding pin on the programmable logic chip; The switching switch, depending on the current operating mode of the multi-channel signal processing device, selects to connect the first end of the switching switch to the third end of the switching switch, or selects to connect the second end of the switching switch to the third end of the switching switch.

[0009] According to a multi-channel signal processing device provided by the present invention, based on the current working mode being the acquisition mode, the first terminal of the switching switch is selected to be connected to the third terminal of the switching switch; Based on the fact that the current working mode is the transmission mode, the second terminal of the switch is connected to the third terminal of the switch.

[0010] According to a multi-channel signal processing apparatus provided by the present invention, the multi-channel signal processing apparatus further includes: Multiple signal acquisition branches, the output of each of the signal acquisition branches is connected to the analog input of the analog-to-digital converter in the corresponding data converter; Multiple signal transmission branches, the input terminal of each of the signal transmission branches is connected to the digital input terminal of the digital-to-analog converter in the corresponding data converter; Among them, multiple signal acquisition branches are used to acquire bandwidth signals from different directions for processing by the analog-to-digital converter, and multiple signal transmission branches are used to transmit bandwidth signals to different directions.

[0011] According to the multi-channel signal processing apparatus provided by the present invention, the signal acquisition branch is used to acquire any one of the following bandwidth signals: Bandwidth signals with passband frequencies ranging from 5925MHz to 7125MHz, bandwidth signals with passband frequencies ranging from 5150MHz to 5895MHz, and bandwidth signals with passband frequencies ranging from 2400MHz to 2500MHz.

[0012] According to the present invention, a multi-channel signal processing apparatus is provided, wherein the signal transmitting branch is used to transmit any of the following bandwidth signals: Bandwidth signals with passband frequencies ranging from 5925MHz to 7125MHz, bandwidth signals with passband frequencies ranging from 5150MHz to 5895MHz, and bandwidth signals with passband frequencies ranging from 2400MHz to 2500MHz.

[0013] According to a multi-channel signal processing device provided by the present invention, a plurality of data converters are integrated with the programmable logic chip.

[0014] According to a multi-channel signal processing apparatus provided by the present invention, the multi-channel signal processing apparatus further includes: A storage chip, connected to the programmable logic chip, is used to temporarily store multiple bandwidth signals obtained through multiple data converters or to temporarily store multiple bandwidth signals stored in the storage component and read by the data processing platform.

[0015] According to a multi-channel signal processing apparatus provided by the present invention, the multi-channel signal processing apparatus further includes: Reference clock source, used to generate a reference clock signal; A frequency synthesizer, connected to the reference clock source, is used to output a working clock signal based on the reference clock signal; A clock generation module is connected to the programmable logic chip and the multiple data converters respectively, and is used to receive the working clock signal and send the working clock signal to the programmable logic chip and the data converters.

[0016] This invention provides a multi-channel signal processing device that, through the coupling of a programmable logic chip and multiple data converters, and in conjunction with a high-speed bus-driven data processing platform and storage components, achieves a closed-loop processing of broadband signals from the analog domain to the storage domain and back again. This architecture enables the device to function as a high-fidelity video recorder for recording dynamic electromagnetic interference in complex outdoor environments, and also as a playback device for reproducing such environments in a controlled laboratory setting. From a data processing perspective, the multi-channel synchronous conversion and high-speed bus data scheduling solve the throughput bottleneck of ultra-high bandwidth data during acquisition and transmission, ultimately enabling frequent, high-precision performance verification without the need to transport equipment to the field, significantly reducing verification costs and improving verification efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is one of the schematic block diagrams of the multi-channel signal processing device provided by the present invention.

[0019] Figure 2This is the second schematic block diagram of the multi-channel signal processing device provided by the present invention.

[0020] Figure 3 This is a schematic block diagram of the analog-to-digital converter provided by the present invention.

[0021] Figure label: 10: Data converter; 101: Analog-to-digital converter; 102: Digital-to-analog converter; 103: Switch; 20: Programmable logic chip; 30: Storage component; 301: Storage array; 302: Disk array card; 40: Data processing platform; 50: Signal acquisition branch; 60: Signal transmission branch; 70: Storage chip; 80: Reference clock source; 90: Frequency synthesizer; 100: Clock generation module. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0023] This embodiment provides a multi-channel signal processing device, which is mainly used to capture high-fidelity wireless signals in real electromagnetic environments (such as wearable device usage sites with reflection, multipath, obstruction and dynamic interference) so as to provide accurate data support for subsequent verification of wearable device performance in laboratory environment. It can also realize the transmission of wireless signals, thereby meeting the usage needs of verifying wearable device performance in laboratory environment.

[0024] The multi-channel signal processing device provided in this embodiment of the invention can be executed by the multi-channel signal processing device itself, or by a central processing unit or control chip integrated inside the device, through the entire process of signal acquisition, conversion, logical distribution, storage and transmission.

[0025] The following is combined Figures 1 to 3 The multi-channel signal processing apparatus of the present invention is described.

[0026] Figure 1 This is one of the schematic block diagrams of the multi-channel signal processing device provided by the present invention, such as... Figure 1 , Figure 2 As shown, the multi-channel signal processing device includes the following modules: Multiple data converters 10, which are used to convert analog signals into digital signals or digital signals into analog signals; The programmable logic chip 20 is connected to multiple data converters 10; Storage component 30; The data processing platform 40 is connected to the programmable logic chip 20 and the storage component 30 via a high-speed bus. The programmable logic chip 20 acquires multiple bandwidth signals through multiple data converters 10 and stores them in the storage component 30 through the data processing platform 40; or the programmable logic chip 20 reads multiple bandwidth signals stored in the storage component 30 through the data processing platform 40 and sends them out through multiple data converters 10.

[0027] Among them, multiple data converters 10 serve as a crucial bridge connecting the physical electromagnetic environment and the digital processing system, possessing bidirectional conversion capabilities. Specifically, the data converters 10 are used to convert received analog signals (such as continuous radio frequency waveforms captured by an antenna) into digital signals (such as discrete IQ sampling sequences), or to convert digital signals (such as code streams stored in a medium) into analog signals for transmission. In practical applications, to support high-bandwidth communication protocols such as WiFi 6 / 7 or Bluetooth, the data converters 10 typically have extremely high sampling rates and quantization accuracy, enabling them to capture subtle changes in the signal.

[0028] The storage component 30 provides high-capacity data persistence capabilities. The data processing platform 40 serves as the system's management and control layer, connecting to the programmable logic chip 20 and the storage component 30 via a high-speed bus. The high-speed bus can employ high-bandwidth, low-latency serial communication standards such as PCI-Express (PCIe) to support real-time throughput of massive bandwidth signals.

[0029] In this embodiment, the multi-channel signal processing device supports two core operating modes: Mode 1: Acquisition Mode. The programmable logic chip 20 simultaneously acquires multiple bandwidth signals through multiple data converters 10. Here, acquisition refers to the data converters 10 synchronously sampling multiple analog inputs under a unified clock cycle and converting them into digital streams. After processing these digital streams by format alignment and tagging (such as timestamps and channel numbers), the programmable logic chip 20 transmits the data to the data processing platform 40 via a high-speed bus, and finally stores it in the storage component 30.

[0030] Mode 2: Transmission Mode. The programmable logic chip 20 reads pre-stored multiple bandwidth signals from the storage component 30 via the data processing platform 40. Here, the reading is initiated by the data processing platform 40, which loads large-scale data from the storage component 30 into the logic chip cache. Subsequently, the programmable logic chip 20 distributes these digital signals to the corresponding data converters 10 according to strict timing requirements, converting them into analog radio frequency signals. This process enables the playback of real-world field signals, simulating real interference and multipath environments for the wearable device under test.

[0031] In this embodiment, through the coupling of the programmable logic chip 20 with multiple data converters 10, and in conjunction with the high-speed bus-driven data processing platform 40 and storage component 30, a closed-loop processing of broadband signals from the analog domain to the storage domain and back from the storage domain is achieved. This architecture enables the device to function as a high-fidelity video recorder to record dynamic electromagnetic interference in complex outdoor fields, and also as a playback device to reproduce such environments in a controlled laboratory environment. From a data processing perspective, the throughput bottleneck of ultra-high bandwidth data during acquisition and transmission is solved through multi-channel synchronous conversion and high-speed bus data scheduling. Ultimately, this enables frequent, high-precision performance verification without the need to transport equipment to the field, significantly reducing verification costs and improving verification efficiency.

[0032] In some embodiments, the storage component 30 includes: Storage array 301; The disk array card 302 is connected at one end to the storage array 301, and at the other end to the data processing platform 40 via a high-speed bus.

[0033] In this context, storage array 301 refers to a logical storage unit composed of multiple physical storage media. In acquisition scenarios involving high sampling rates and large bandwidth signals such as WiFi 6E and WiFi 7, the write speed of a single disk is often insufficient to match the high-speed bitstream generated by multiple parallel channels. Therefore, this embodiment employs storage array 301. The storage capacity of storage array 301 can be configured according to testing requirements, for example, to 128TB or larger, to support long-term continuous packet capture in complex external electromagnetic environments.

[0034] The RAID card 302 (Redundant Arrays of Independent Disks) is a hardware controller specifically designed to manage disk arrays. Its core function is to distribute data across the physical disks in the storage array 301 according to a preset array mode (such as RAID 0, RAID 5, or RAID 10). In this embodiment, the RAID card 302 acts as a communication bridge between the data processing platform 40 and the storage array 301, responsible for performing high-speed data I / O scheduling.

[0035] In the specific implementation process, under signal acquisition mode, the data flow is as follows: First, the programmable logic chip 20 packages the multiple digital bandwidth signals obtained by multiple data converters 10 into a protocol and transmits them to the memory buffer of the data processing platform 40 via a high-speed bus (such as a PCIe 3.0 16X bus) through direct memory access. Next, the central processing unit in the data processing platform 40 issues a storage instruction, pushing the data stream in the memory buffer to the disk array card 302 via the high-speed bus; Finally, the disk array card 302 uses its internal hardware acceleration engine to split the large data stream into multiple sub-data blocks and write them in parallel to multiple hard drives in the storage array 301.

[0036] In signal transmission mode, the above process is executed in reverse: the disk array card 302 reads data blocks in parallel from the storage array 301, reassembles them, and submits them to the data processing platform 40 via the high-speed bus, and then the programmable logic chip 20 schedules them to the data converter 10 for restoration and transmission.

[0037] In the above embodiment, the high-speed bus is selected as the PCI-Express bus. Since the data processing platform 40 is usually equipped with multiple PCIe slots (such as SLOT1 and SLOT2), the disk array card 302 can be inserted into one of the slots to establish a point-to-point high-speed connection with the central processing unit of the data processing platform 40, ensuring that the bus bandwidth will not become a system bottleneck when performing multi-channel (such as 4 channels or more) 160MHz bandwidth signal acquisition.

[0038] In this embodiment, by introducing an architecture that combines a disk array card 302 with a storage array 301, and utilizing the parallel writing mechanism of the disk array, the data throughput of the system in the storage stage is greatly improved. This feature, combined with the aforementioned acquisition / transmission process, solves the problem of data impact caused by the inability of a single storage medium to handle the acquisition of multiple ultra-wideband signals in real time, ensuring the continuity and integrity of the bandwidth signal during long-period recording. This enables the effective capture and management of massive amounts of real-world environmental data, providing a solid data foundation for subsequent performance simulation of wearable devices.

[0039] In some embodiments, such as Figure 3 As shown, each data converter 10 includes: Analog-to-digital converter 101; Digital-to-analog converter 102; The switching switch 103 has its first end connected to the digital output terminal of the analog-to-digital converter 101, its second end connected to the digital input terminal of the digital-to-analog converter 102, and its third end connected to the corresponding pin on the programmable logic chip 20. The switching switch 103 selects to connect the first end of the switching switch 103 to the third end of the switching switch 103, or selects to connect the second end of the switching switch 103 to the third end of the switching switch 103, according to the current working mode of the multi-channel signal processing device.

[0040] The analog-to-digital converter 101 is responsible for generating data for the acquisition path. It samples, quantizes, and encodes the input continuous analog signal, outputting a digital encoded stream reflecting the signal amplitude changes—that is, the raw IQ data generated at the digital output terminal. The digital-to-analog converter 102 is responsible for signal reconstruction for the transmission path. It receives the digital code stream from the logic chip, converts it into a stepped voltage signal, and then, after filtering, reconstructs it into an analog radio frequency waveform.

[0041] The switching switch 103 is the core component for realizing time-division multiplexing of the transmit and receive channels. From the perspective of decreasing protection range, the switching switch 103 can be a high-frequency electronic switch, a multiplexer, or a gated logic circuit integrated within a chip. The first terminal of the switching switch 103 is connected to the digital output terminal of the analog-to-digital converter 101, the second terminal is connected to the digital input terminal of the digital-to-analog converter 102, and its third terminal (common terminal) is connected to the corresponding pin on the programmable logic chip 20.

[0042] The specific implementation process is as follows: The control logic of the device monitors the current working mode of the multi-channel signal processing device in real time. When the control system receives an external command or a preset program switches to the acquisition mode, it sends a first control level to the switch 103, driving the switch 103 to connect its first terminal to its third terminal. At this time, the digital stream generated by the analog-to-digital converter 101 can smoothly enter the programmable logic chip 20. Conversely, when switching to the transmission mode, the control system sends a second control level, driving the switch 103 to connect its second terminal to its third terminal, so that the data to be transmitted output by the logic chip can be accurately sent to the digital-to-analog converter 102 for conversion.

[0043] In this embodiment, by introducing a three-terminal switching architecture consisting of an analog-to-digital converter 101, a digital-to-analog converter 102, and a switching switch 103 into each data converter 10, dynamic multiplexing of the two transmission and reception links using a single pin of the programmable logic chip 20 is achieved. From the perspective of spatiotemporal coordination in data processing, this switching mechanism allows the device to flexibly define the signal flow direction of each channel according to task requirements. While ensuring multi-channel concurrent processing performance, it greatly reduces the pin occupancy of the programmable logic chip 20 and the complexity of circuit board wiring, significantly reducing the hardware power consumption and size of the device, and achieving miniaturization and high integration of the signal processing device.

[0044] In some embodiments, based on the current working mode being the acquisition mode, the first terminal of the selector switch 103 is connected to the third terminal of the selector switch 103; Based on the current operating mode being the transmission mode, the second terminal of the selector switch 103 is connected to the third terminal of the selector switch 103.

[0045] Once this physical connection is established, the acquisition link is activated: the analog bandwidth signal from the external environment is captured by the front-end sensor and input to the analog-to-digital converter 101, which quantizes it into a digital stream. This digital stream flows out from the digital output terminal (i.e., the first terminal) of the analog-to-digital converter 101, passes through the switch 103, and enters the corresponding pin (i.e., the third terminal) on the programmable logic chip 20. This configuration ensures that the data stream from the analog domain to the digital domain can accurately and in real-time enter the logic processing unit for protocol encapsulation and storage scheduling.

[0046] When the device receives a command to switch to transmit mode, the execution unit outputs a second control level (such as a low-level signal) to the switch 103. At this time, the switch 103 responds quickly, connecting its second terminal to its third terminal while simultaneously disconnecting from the first terminal. In this connection state, the transmit link is established: the programmable logic chip 20 retrieves a pre-stored digital bandwidth signal from its internal buffer or back-end storage component 30 according to the test timing. This signal is emitted through a pin (i.e., the third terminal) of the programmable logic chip 20, and after being bridged by the switch 103, is precisely delivered to the digital input terminal (i.e., the second terminal) of the digital-to-analog converter 102. The digital-to-analog converter 102 then performs a conversion operation, restoring the digital signal to an analog radio frequency waveform for outward radiation.

[0047] In practical applications, the switch 103 can be an electronic switch with a single-pole double-throw structure, whose switching response time is typically in the nanosecond range, enabling rapid and seamless switching between acquisition and transmission tasks. The mode status can be acquired either through software triggering by reading register flags or through hardware triggering by generating physical voltage levels using a hardware DIP switch.

[0048] In this embodiment, by strongly coupling the operation logic of the switching switch 103 with the current operating mode of the device (acquisition mode or transmission mode), efficient multiplexing of the I / O pins of the programmable logic chip 20 is achieved. From a data processing perspective, this scheme utilizes the switching switch 103 as a digital selector, changing the data flow transmission path between the digital-to-analog converter 102 and the analog-to-digital converter 101 according to mode instructions. This allows the pin resources of the same programmable logic chip 20 to assume the responsibilities of data input and output at different times. This cooperative approach not only greatly saves the pin resource overhead of the programmable logic chip 20 and reduces the complexity of circuit board wiring, but also eliminates the risk of collision interference between the acquisition and transmission data streams from the underlying logic level, thereby ensuring the high reliability of the multi-channel signal processing device in different operating modes.

[0049] In some embodiments, the multi-channel signal processing apparatus further includes: Multiple signal acquisition branches 50, the output of each signal acquisition branch 50 is connected to the analog input of the analog-to-digital converter 101 in the corresponding data converter 10; Multiple signal transmission branches 60, the input terminal of each signal transmission branch 60 is connected to the digital input terminal of the digital-to-analog converter 102 in the corresponding data converter 10; Among them, multiple signal acquisition branches 50 are used to acquire bandwidth signals from different directions for processing by analog-to-digital converter 101, and multiple signal transmission branches 60 are used to transmit bandwidth signals to different directions.

[0050] In this embodiment, the signal acquisition branch 50 refers to a hardware link with spatial directional reception capability. The output of each signal acquisition branch 50 is connected to the analog input of the analog-to-digital converter 101 in the corresponding data converter 10. Specifically, the signal acquisition branch 50 typically includes a directional antenna and supporting radio frequency front-end components (such as a low-noise amplifier, bandpass filter, etc.). In this embodiment, multiple signal acquisition branches 50 are used to acquire bandwidth signals from different directions. Here, "different directions" refers to achieving omnidirectional signal coverage of the surrounding space by physically arranging multiple antennas with different directivity.

[0051] For example, in a specific application scenario, the device is configured with four signal acquisition branches 50, whose corresponding directional antennas are arranged facing the east, south, west, and north directions, or distributed at azimuth intervals of 0°, 90°, 180°, and 270°. When the device is in acquisition mode, each branch independently and synchronously captures electromagnetic waves from a specific direction. These analog signals carrying spatial characteristics are sent to the analog-to-digital converter 101, which performs processing actions, namely, converting the spatial multipath signals into multiple digital streams through high-speed sampling and quantization, and then storing them in the storage component 30 after marking the azimuth with an azimuth identifier by the programmable logic chip 20.

[0052] Accordingly, signal transmission branch 60 refers to a hardware link with spatial directional radiation capability. The input of each signal transmission branch 60 is connected to the output of the corresponding digital-to-analog converter 102 in the data converter 10 (i.e., a logical connection of the digital input). The signal transmission branch 60 is used to transmit bandwidth signals in different directions. In transmission mode, the programmable logic chip 20 reads the digital signal with directional markings from the storage component 30 and distributes it to the corresponding digital-to-analog converter 102.

[0053] In this embodiment, by introducing multiple physically isolated and directionally defined signal acquisition branches 50 and transmission branches, and combining them with the multi-channel parallel processing capability of the data converter 10, a one-to-one correspondence between the digital channel and the physical spatial orientation is established. From a data processing perspective, this architecture enables the system to not only record the frequency and temporal characteristics of the signal, but also to fully preserve and reproduce the spatial multipath characteristics and directional interference features of the signal. Through the independent acquisition and synchronous transmission of signals from different orientations by multiple branches, a near-realistic test field with spatial dimensions and multipath effects is constructed for the wearable device under test. This solves the problem that a single antenna system cannot simulate complex dynamic interference and spatial distribution characteristics, greatly improving the accuracy of verifying the antenna performance and anti-interference capability of the wearable device.

[0054] In some embodiments, the signal acquisition branch 50 is used to acquire any of the following bandwidth signals: Bandwidth signals with passband frequencies ranging from 5925MHz to 7125MHz, bandwidth signals with passband frequencies ranging from 5150MHz to 5895MHz, and bandwidth signals with passband frequencies ranging from 2400MHz to 2500MHz.

[0055] In this embodiment, by limiting and adapting the acquisition capability of the signal acquisition branch 50 to three key communication frequency bands—5925MHz to 7125MHz, 5150MHz to 5895MHz, and 2400MHz to 2500MHz—full coverage of mainstream communication standards for existing and next-generation wearable devices is achieved. From a data processing perspective, the signal acquisition branch 50, at the source of data digitization, achieves on-demand interception and channel purification of massive amounts of environmental electromagnetic waves through precise passband physical filtering. This feature, combined with high-speed quantization processing at the back end, effectively prevents out-of-band broadband noise from crowding out the dynamic range of the analog-to-digital converter 101 and eliminates intermodulation distortion caused by non-target frequency band interference. This ensures that the acquired bandwidth signal can faithfully reproduce the physical characteristics of the real outdoor environment, providing an accurate and reliable data foundation for performance verification in the laboratory.

[0056] In some embodiments, the signal transmitting branch 60 is used to transmit a signal with any of the following bandwidths: Bandwidth signals with passband frequencies ranging from 5925MHz to 7125MHz, bandwidth signals with passband frequencies ranging from 5150MHz to 5895MHz, and bandwidth signals with passband frequencies ranging from 2400MHz to 2500MHz.

[0057] In this embodiment, by precisely limiting the operating range of the signal transmission branch 60 to the three core frequency bands of wireless communication—2.4GHz, 5GHz, and 6GHz—full coverage support for existing and future mainstream wireless protocols is achieved. From a data processing perspective, the signal transmission branch 60, through multi-level filtering and precise frequency band selection, ensures the purity of the emitted analog signal in the spectrum, making it highly consistent with the electromagnetic characteristics of real external fields. This multi-band coverage capability combined with the multi-channel transmission architecture enables the device to simultaneously or time-divisionally simulate interference models under different protocols, thereby providing a highly targeted protocol-level and physical layer testing environment for wearable devices. This completely solves the technical difficulty of simulating ultra-high frequency, wide-bandwidth real interference in a laboratory environment, significantly improving the coverage depth of performance verification.

[0058] In some embodiments, multiple data converters 10 are integrated with an editable logic chip 20.

[0059] The integrated setup refers to combining the originally independent analog-to-digital / digital-to-analog conversion units and logic processing units together using advanced packaging technology or single-chip manufacturing technology. Specifically, the execution entity (i.e., the core processing module of the multi-channel signal processing device) can adopt an RF System-on-Chip (RFSoC) architecture. In this architecture, multiple data converters 10 are manufactured on the same silicon substrate or packaged in the same chip package, thereby forming a highly integrated RF digital processing core.

[0060] In practical implementation, since the data converter 10 and the programmable logic chip 20 are physically located within the same chip, the connection method between them is changed from traditional PCB wiring to an internal ultra-large-scale interconnect structure. The programmable logic chip 20 directly interfaces with the digital ports of each data converter 10 through its internal high-speed data bus.

[0061] In this embodiment, by integrating multiple data converters 10 with the programmable logic chip 20, deep integration of the radio frequency link and the digital logic link is achieved. From the perspective of data processing, this integration eliminates the processing latency caused by external high-speed interfaces (such as serial demultiplexers / multiplexers), shortens the data stream transmission path from the sampling end to the processing end, effectively solves the phase offset problem caused by inconsistent external wiring lengths between multiple channels, and ensures the synchronization accuracy of multiple signals at the picosecond level. At the same time, by reducing the number of high-speed differential pairs on the external circuit board, the signal integrity risk and electromagnetic interference during data transmission are greatly reduced, ultimately significantly improving the fidelity of the device in simulating ultra-wideband, multipath complex signal environments, and providing a cleaner and more accurate reference signal source for the performance testing of wearable devices.

[0062] In some embodiments, the multi-channel signal processing apparatus further includes: The storage chip 70, connected to the programmable logic chip 20, is used to temporarily store multiple bandwidth signals obtained through multiple data converters 10 or to temporarily store multiple bandwidth signals read by the data processing platform 40 and stored in the storage component 30.

[0063] The memory chip 70 refers to a high-speed storage medium with high bandwidth and low latency, primarily serving as a high-performance buffer during data transfer. In this embodiment, the memory chip 70 can be one or more combinations of dynamic random access memory, static random access memory, or 4x data rate static random access memory. The memory chip 70 is directly coupled to the memory controller interface of the programmable logic chip 20 via a parallel address / data bus.

[0064] In this embodiment, a dedicated storage chip 70 is introduced as a high-speed buffer between the programmable logic chip 20 and the high-speed conversion link. Combined with a ping-pong buffer scheduling method, an efficient data queuing mechanism is built at the hardware level. With this feature, the storage chip 70 plays a crucial role in smoothing bandwidth fluctuations. It works in conjunction with the high-speed parallel processing capability of the programmable logic chip 20 to offset data jitter caused by high-speed bus contention or addressing delays of the storage component 30. Ultimately, this achieves the technical effect of preventing data overflow at the acquisition end and ensuring uninterrupted flow at the transmission end during ultra-high bandwidth signal processing. From the perspective of data processing stability, this ensures that the device can perfectly reproduce or capture high-speed transient signals from the real external field, greatly improving the fidelity of signal processing.

[0065] In some embodiments, the multi-channel signal processing apparatus further includes: Reference clock source 80 is used to generate a reference clock signal; The frequency synthesizer 90 is connected to the reference clock source 80 and is used to output a working clock signal based on the reference clock signal. The clock generation module 100 is connected to the programmable logic chip 20 and multiple data converters 10, respectively, and is used to receive the working clock signal and send the working clock signal to the programmable logic chip 20 and the data converters 10.

[0066] In this embodiment, the reference clock source 80 serves as the frequency reference for the entire system, essentially providing an oscillation source for a highly stable pulse signal. In specific implementations, the reference clock source 80 can employ a temperature-compensated crystal oscillator or a temperature-controlled crystal oscillator to ensure that the generated reference clock signal has extremely low frequency drift under different temperature environments. The frequency of this reference clock signal is typically set to a standard frequency, such as 100MHz or 10MHz.

[0067] The frequency synthesizer 90 refers to an electronic system capable of converting an input reference frequency into one or more specific target frequencies through frequency multiplication, division, or mixing techniques. Internally, it typically includes a phase-locked loop (PLL) circuit and a voltage-controlled oscillator (VCO). During implementation, the frequency synthesizer 90 acquires the aforementioned stable reference clock signal and uses it as a phase reference to lock the output frequency at a specific multiple of the reference signal through PLL logic. The generated operating clock signal has a frequency significantly higher than the reference signal, typically reaching the GHz level (e.g., 2GHz to 4GHz), to meet the frequency requirements of the aforementioned analog-to-digital converter 101 for oversampling or high-rate sampling of high-bandwidth signals such as WiFi 7.

[0068] After receiving the working clock signal, the clock generation module 100 synchronously sends the signal to the programmable logic chip 20 and all data converters 10 through its internal symmetrical wiring design and clock drive circuit.

[0069] In this embodiment, by introducing a reference clock source 80 and a frequency synthesizer 90, a frequency evolution link from a stable reference to a high-speed operating clock is constructed. In conjunction with the clock generation module 100, the global clock is distributed from the same source, ensuring that multiple data converters 10 in different locations share the same physical time reference. This effectively eliminates frequency deviation and phase jitter caused by clock independence between multiple data converters 10.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-channel signal processing device, characterized in that, include: Multiple data converters, the data converters being used to convert analog signals into digital signals or digital signals into analog signals; Programmable logic chip, connected to multiple of the aforementioned data converters; Storage components; A data processing platform, which is connected to the programmable logic chip and the storage component via a high-speed bus; The programmable logic chip acquires multiple bandwidth signals through multiple data converters and stores them in the storage component through the data processing platform; or the programmable logic chip reads multiple bandwidth signals stored in the storage component through the data processing platform and sends them out through multiple data converters.

2. The multi-channel signal processing device according to claim 1, characterized in that, The storage component includes: Storage array; A disk array card, one end of which is connected to the storage array, and the other end of which is connected to the data processing platform via the high-speed bus.

3. The multi-channel signal processing device according to claim 1, characterized in that, Each of the data converters includes: Analog-to-digital converter; Digital-to-analog converter; A switching switch, wherein the first end of the switching switch is connected to the digital output terminal of the analog-to-digital converter, the second end of the switching switch is connected to the digital input terminal of the digital-to-analog converter, and the third end of the switching switch is connected to the corresponding pin on the programmable logic chip; The switching switch, depending on the current operating mode of the multi-channel signal processing device, selects to connect the first end of the switching switch to the third end of the switching switch, or selects to connect the second end of the switching switch to the third end of the switching switch.

4. The multi-channel signal processing device according to claim 3, characterized in that, Based on the fact that the current working mode is the acquisition mode, the first terminal of the switch is connected to the third terminal of the switch. Based on the fact that the current working mode is the transmission mode, the second terminal of the switch is connected to the third terminal of the switch.

5. The multi-channel signal processing device according to claim 3, characterized in that, The multi-channel signal processing device further includes: Multiple signal acquisition branches, the output of each of the signal acquisition branches is connected to the analog input of the analog-to-digital converter in the corresponding data converter; Multiple signal transmission branches, the input terminal of each of the signal transmission branches is connected to the digital input terminal of the digital-to-analog converter in the corresponding data converter; Among them, multiple signal acquisition branches are used to acquire bandwidth signals from different directions for processing by the analog-to-digital converter, and multiple signal transmission branches are used to transmit bandwidth signals to different directions.

6. The multi-channel signal processing apparatus according to claim 5, characterized in that, The signal acquisition branch is used to acquire any of the following bandwidth signals: Bandwidth signals with passband frequencies ranging from 5925MHz to 7125MHz, bandwidth signals with passband frequencies ranging from 5150MHz to 5895MHz, and bandwidth signals with passband frequencies ranging from 2400MHz to 2500MHz.

7. The multi-channel signal processing apparatus according to claim 5, characterized in that, The signal transmitting branch is used to transmit any of the following bandwidth signals: Bandwidth signals with passband frequencies ranging from 5925MHz to 7125MHz, bandwidth signals with passband frequencies ranging from 5150MHz to 5895MHz, and bandwidth signals with passband frequencies ranging from 2400MHz to 2500MHz.

8. The multi-channel signal processing apparatus according to claim 1, characterized in that, Multiple data converters are integrated with the programmable logic chip.

9. The multi-channel signal processing apparatus according to claim 1, characterized in that, The multi-channel signal processing device further includes: A storage chip, connected to the programmable logic chip, is used to temporarily store multiple bandwidth signals obtained through multiple data converters or to temporarily store multiple bandwidth signals stored in the storage component and read by the data processing platform.

10. The multi-channel signal processing apparatus according to any one of claims 1 to 9, characterized in that, The multi-channel signal processing device further includes: Reference clock source, used to generate a reference clock signal; A frequency synthesizer, connected to the reference clock source, is used to output a working clock signal based on the reference clock signal; A clock generation module is connected to the programmable logic chip and the multiple data converters respectively, and is used to receive the working clock signal and send the working clock signal to the programmable logic chip and the data converters.

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