Timing control method, electronic device, vehicle, storage medium, and program product

Abstract

This application provides a timing control method, electronic device, vehicle, storage medium, and program product. When a data frame crosses a time slot, the time slot for storing cross-time slot error codes is determined based on the level state of the data storage flag signal corresponding to the frame header reception time. Then, when the frame tail of the data frame is received, the cross-time slot error code is stored in the buffer corresponding to the first target time slot. By determining the storage location of the error code based on the level state of the data storage flag signal at the frame header reception time, differentiated error records can be provided for different abnormal situations, reducing the possibility of data loss or error reporting and improving the security and stability of the system.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a timing control method, electronic equipment, vehicle, storage medium, and program product. Background Technology

[0002] In automotive electronic systems, the Peripheral Sensor Interface (PSI5) is widely used to connect safety-critical sensors (such as airbag sensors, body sensors, etc.) to the electronic control unit (ECU).

[0003] The timing scheme of PSI5 communication directly determines the reliability, real-time performance and compatibility of the system. However, due to the wide distribution of sensors, long transmission distances and complex environments, time slot conflicts often occur in practical applications, leading to data loss or erroneous reports, which in turn affect the security and stability of the system. Summary of the Invention

[0004] The timing control method, electronic device, vehicle, storage medium, and program product provided in this application are used to reduce the possibility of data loss or erroneous reports and improve the security and stability of the system.

[0005] In a first aspect, embodiments of this application provide a timing control method, including:

[0006] When determining the time slot of a data frame, the first target time slot for storing the time slot error code is determined based on the level state of the data storage flag signal corresponding to the time of receiving the frame header of the data frame.

[0007] Upon receiving the end of a data frame, the cross-timeslot error code is stored in the buffer corresponding to the first target timeslot.

[0008] Optionally, determining the first target time slot for storing cross-time slot error codes based on the level state of the data storage flag signal corresponding to the frame header reception time of the data frame includes:

[0009] If the data storage flag signal is at a first level, then the time slot to which the frame header of the data frame belongs is determined to be the first target time slot.

[0010] If the data storage flag signal is at the second level, then the time slot to which the frame tail of the data frame belongs is determined to be the first target time slot.

[0011] Optionally, the method further includes:

[0012] Upon receiving the end of a data frame, the level of the data storage flag signal is pulled high to the second level state;

[0013] At the start of the next time slot, the level of the data storage flag signal is pulled low to the first level.

[0014] Optionally, the method further includes:

[0015] When multiple pieces of data to be stored are received in the same time slot, the data to be finally stored in the corresponding buffer area of ​​the time slot is determined according to the data storage priority rules.

[0016] The data storage priority rule includes: sensor data frames have a higher priority than cross-timeslot error codes.

[0017] Optionally, the method further includes:

[0018] The second target time slot corresponding to the data frame is determined based on the time slot to which the received data frame tail reception time belongs;

[0019] The data frame is stored in the buffer corresponding to the second target time slot.

[0020] Optionally, the method further includes:

[0021] When multiple data to be stored are received in the same time slot, the data to be stored in the corresponding buffer area of ​​that time slot is determined according to the priority rule of the latest sensor data.

[0022] The latest sensor data priority rule includes: the priority of the sensor data frame received later is higher than that of the sensor data frame received earlier.

[0023] Optionally, the method further includes:

[0024] Each time slot is configured with an independent receive signal line, which is used to indicate the time slot buffer area currently allowed to store data;

[0025] According to the preset polling order, the receiving signal lines corresponding to each time slot are pulled up sequentially;

[0026] The received data frames are stored sequentially into the time slot buffer corresponding to the currently high receive signal line;

[0027] When the next synchronization pulse is detected, all receive signal lines are reset.

[0028] Optionally, the method further includes:

[0029] After sending the synchronization pulse, after a preset blanking time, the receive enable signal is set to an active state to allow the reception of sensor data frames.

[0030] When the preset reception end time is reached, the reception enable signal is set to an invalid state to stop receiving sensor data frames;

[0031] If a new synchronization pulse is detected while the receive enable signal is active, an unexpected synchronization pulse error is reported, and the currently received data frame is discarded.

[0032] Optionally, the method further includes:

[0033] Based on multiple preset time slot configuration parameters, determine the start and end times of each time slot;

[0034] The start and end times are sorted and verified.

[0035] If a timing error is detected during the verification, a time slot configuration error will be reported, and the time slot range with the timing error will be marked as an invalid time slot.

[0036] Only the received data frames are stored in the buffer corresponding to the valid time slot.

[0037] Optional, also includes:

[0038] A preset delay time is maintained between the synchronization pulses of the first communication channel and the second communication channel;

[0039] The first communication channel and the second communication channel are used to connect different sensors.

[0040] Secondly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0041] The memory stores computer-executed instructions;

[0042] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0043] Thirdly, embodiments of this application provide a vehicle including the electronic equipment of the second aspect.

[0044] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0045] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0046] The timing control method, electronic device, vehicle, storage medium, and program product provided in this application determine the time slot for storing cross-time slot error codes based on the level state of the data storage flag signal corresponding to the frame header reception time when a data frame crosses a time slot. Then, upon receiving the frame tail of the data frame, the cross-time slot error code is stored in the buffer corresponding to the first target time slot. By determining the storage location of the error code based on the level state of the data storage flag signal at the frame header reception time, differentiated error records can be provided for different abnormal situations, reducing the possibility of data loss or error reporting and improving the security and stability of the system. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0048] Figure 1 The PSI5 transceiver system architecture diagram provided in this application;

[0049] Figure 2 This application provides a system architecture diagram of the PSI5 interface.

[0050] Figure 3 Synchronization mode timing diagram provided for this application;

[0051] Figure 4 The timing definition diagram for the synchronization mode provided in this application;

[0052] Figure 5 This application provides a storage solution for abnormal conditions in the synchronization mode.

[0053] Figure 6 This application provides a storage solution for abnormal conditions in the synchronization mode.

[0054] Figure 7 The synchronization pulse timing diagrams for normal / abnormal synchronization modes provided in this application;

[0055] Figure 8 Timing diagram for abnormal configuration of synchronization mode time slots provided in this application;

[0056] Figure 9 Timing diagram of PSI5 multi-channel simultaneous configuration trigger synchronization pulse provided in this application;

[0057] Figure 10 A flowchart illustrating the timing control method provided in this application;

[0058] Figure 11 The design and storage scheme of the improved time slot monitoring scheme provided in this application;

[0059] Figure 12 The time-slot monitoring improvement scheme provided in this application includes an anomaly handling design and storage scheme.

[0060] Figure 13 The time-slot monitoring improvement scheme provided in this application includes an anomaly handling design and storage scheme.

[0061] Figure 14 The second improved time slot monitoring scheme and storage scheme provided in this application;

[0062] Figure 15 The second improved time slot monitoring solution provided in this application includes an anomaly handling design and storage scheme.

[0063] Figure 16 The design and storage scheme of the third improved time slot monitoring scheme provided in this application;

[0064] Figure 17 The third anomaly handling design and storage scheme provided for the improved time slot monitoring scheme in this application;

[0065] Figure 18 The normal trigger synchronization pulse design diagram provided in this application;

[0066] Figure 19 The abnormal triggering synchronization pulse design diagram provided in this application;

[0067] Figure 20 Threshold diagram for time slot monitoring provided in this application;

[0068] Figure 21 The abnormal time slot configuration design diagram provided for this application;

[0069] Figure 22 The PSI5 multichannel sensor connection topology diagram provided in this application;

[0070] Figure 23 The PSI5 multi-channel design diagram with regard to SDT (configuration of the same trigger point) provided for this application;

[0071] Figure 24 The PSI5 multi-channel design diagram with respect to SDT (configuration of different trigger points) provided in this application;

[0072] Figure 25 A schematic diagram of the structure of the electronic device provided in this application.

[0073] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0074] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0075] In the field of automotive electronics, the Peripheral Sensor Interface (PSI5) plays a crucial role in connecting safety-critical sensors (especially airbag sensors) to the backbone of the vehicle's sensor network. For example... Figure 1 As shown, the PSI5 transceiver receives sensor data frames through PSI5 communication and then transmits them to the host through other communication methods (including but not limited to SPI communication).

[0076] like Figure 2 As shown, the host integrates a PSI5 interface, which receives sensor data frames via PSI5 communication. The PSI5 transceiver supports different sensors driving different data frames and continuously ensures that multiple sensor frames and synchronization pulses do not conflict. This function relies on accurate timing monitoring.

[0077] The PSI5 standard protocol, *Peripheral Sensor Interface – Base Standard V2.3*, defines timing for synchronous mode. The protocol stipulates that when transmitting data via multi-sensor polling in synchronous mode, a fixed time slot must be allocated to each sensor to achieve time-sharing transmission of parameters such as position and temperature, ensuring that multiple sensor frames and synchronization pulses do not conflict. Different timing considerations are important for different applications. Therefore, transceivers should not rely on specific time slots but should be configured individually for different time slots. The following section describes the specific implementation method of the timing definition for synchronous mode in the protocol.

[0078] like Figure 3 As shown, a single interface of the ECU (Electronic Control Unit) connects to multiple sensors (such as...) Figure 3 Synchronous transmission (S1-Sn) is performed. When not communicating, the ECU output voltage is V1; in synchronous operation mode, the ECU periodically sends a high-level voltage signal V2 as a synchronization pulse, with the width (time interval) between the two synchronization pulses being Tsync. After detecting this synchronization pulse, each sensor transmits data according to a pre-configured time slot (e.g., S1-Sn). Figure 3 The transceiver (Tslot1-Tslotn) sends its respective current signal to transmit data. The transceiver transmits data in time slot 1 (e.g., ...). Figure 3 Data frames from sensor S1 were received within the range of Tslot1 in time slot 2 (e.g., in time slot 2). Figure 3 Data frames from sensor S2 were received within the Tslot2 range, and data from each sensor were received in different time slots.

[0079] The PSI5 employs time-division multiplexing technology, dividing the transmission time into multiple time slots, with each sensor allocated a specific time slot for data transmission. All sensors rely on the same timing reference, such as... Figure 4 As shown, six time slots (Tslot1-Tslot6) are defined. The time slot from the start time of slot1 (ST1) to the start time of slot2 (ST2) is designated as time slot one (i.e., Figure 4 In the context of Tslot1), the time slot from the start time of slot2 (ST2) to the start time of slot3 (ST3) is time slot two (i.e., Figure 4 (e.g., Tsot2 in the original text); and so on. Similarly, the transmission time is divided into multiple time slots, and the transceiver determines which sensor a frame originates from based on the time slot corresponding to a received frame.

[0080] However, due to the wide distribution of sensors, long transmission distances, and complex environments, time slot conflicts often occur in practical applications, leading to data loss or erroneous reports, which in turn affects the security and stability of the system.

[0081] Example 1:

[0082] Example 1 involves connecting six sensors via the PSI5 interface. The ECU sends a synchronization pulse, theoretically receiving six frames of sensor data, such as... Figure 4 As shown. The following anomalies may occur during actual communication:

[0083] Abnormal situation 1: such as Figure 5 As shown, time slot two ( Figure 5 Slot 2) FRAME2, time slot three ( Figure 5 In the case of a frame (Frame 3) in Slot 3, the reception is too late, while other frames are received normally. The existing solution reports an Across-Time Slot Error (ASE) in both Slot 2 and Slot 3, and stores the corresponding error code (ASE code) in the corresponding buffer. Figure 5 As shown, in the buffer corresponding to time slot one (such as...) Figure 5 FRAME1 is stored in the slot1 buffer of time slot 2, and FRAME1 is stored in the corresponding buffer of time slot 2 (e.g., ...). Figure 5 The slot2 buffer stores cross-slot error codes, while the corresponding buffer for slot 3 (e.g., ...) stores cross-slot error codes. Figure 5The slot3 buffer stores cross-slot error codes, while the corresponding buffer for slot 4 (e.g., ...) stores cross-slot error codes. Figure 5 FRAME4 is stored in the slot4 buffer (e.g., in the buffer corresponding to slot 5). Figure 5 FRAME5 is stored in the slot5 buffer (e.g., in the buffer corresponding to slot six). Figure 5 The slot6 buffer stores FRAME6.

[0084] Abnormal situation 2: such as Figure 6 As shown, FRAME2 in time slot 2 was received too late and FRAME3 was not received, while other frames were received normally. The existing solution reports cross-time slot errors in both time slot 2 and time slot 3, and stores the cross-time slot error code in the corresponding buffer. For the specific storage method, please refer to anomaly case 1.

[0085] The existing solutions report the same error for both of the above anomalies, making it impossible for users to determine whether FRAME3 has actually been received, i.e., whether sensor S3 has malfunctioned, indicating a flaw in the solution.

[0086] Example 2:

[0087] Example 2 involves connecting six sensors via a PSI5 interface, such as... Figure 7 As shown, the ECU sends a synchronization pulse, and under normal circumstances, it should receive six frames of sensor data. However, abnormalities may occur during actual communication. For example, during the sensor data reception, the next synchronization pulse may be triggered (i.e., the synchronization pulse is sent too frequently, which may cause a conflict between the sensor data and the synchronization pulse). The existing solution stops receiving FRAME3 and sends the next synchronization pulse normally, but there is no error reporting mechanism. This makes it impossible for users to distinguish whether the empty receive buffer corresponding to time slots three / four / five / six within range ① is due to "sensor abnormality causing frame not to be sent" or "synchronization pulse transmission abnormality causing frame not to be sent". The solution has defects.

[0088] Example 3:

[0089] Example 3 involves connecting six sensors via a PSI5 interface. The ECU sends a synchronization pulse, and under normal circumstances, the sensors receive data within their respective time slots. Figure 8 As shown. To adapt to different types of sensors, the transceiver allows users to configure the start time of all time slots and the end time of the last time slot. If a configuration error causes the start time of Tslot2 (ST2) to be earlier than the start time of Tslot1 (ST1), the existing solution will determine that a cross-time slot error has occurred in time slot 2, causing FRAME1 and FRAME2, which are normally transmitted by the sensor, to be unreceived, and there is no corresponding error reporting mechanism, which is a defect in the solution.

[0090] Example 4:

[0091] Example 4 supports multiple PSI5 interfaces, such as Figure 9 As shown, channel 1 is supported (e.g.) Figure 9 PSI5 CH#1) and channel 2 (such as Figure 9 In the PSI5 CH#2 configuration, each PSI5 interface connects to six sensors. The ECU sends a synchronization pulse and receives sensor data within its respective time slot. The width between the synchronization pulses of the two channels (e.g., ...) Figure 9 When Tsync1 and Tsync2 in the configuration are consistent, at point t1, channel 1 and channel 2 are simultaneously configured to automatically trigger synchronization pulses (e.g., ...). Figure 9 The simultaneous triggering of synchronization pulses (SYNC1 and SYNC2) at point t2 by ch#1 AutoTriger & ch#2 Auto Triger in the SPI interface causes a doubling of transient current demand, potentially leading to decreased power supply stability and load surges. Furthermore, the significant current fluctuations radiate stronger electromagnetic interference (EMI), affecting other surrounding electronic devices. At point t3, the simultaneous receipt of FRAME1 and FRAME1' requires the host to read these two frames of data via other communication methods (including but not limited to SPI communication), which may result in delayed data retrieval and reduced SPI data transmission efficiency.

[0092] To address this, this application proposes a timing control method that, when a data frame crosses a time slot, determines the time slot for storing cross-time slot error codes based on the level state of the data storage flag signal corresponding to the frame header reception time of the data frame.

[0093] like Figure 5 and Figure 6 As shown, regardless of whether the frame reception is too late (FRAME2, FRAME3 delay) or the frame is completely lost (FRAME3 loss), the existing solution stores the same cross-time slot error code in the buffers of time slot 2 and time slot 3. This makes it impossible for the upper-layer system or the user to distinguish between the two fundamentally different fault types of delayed data arrival and complete data loss, and to determine whether sensor S3 has failed, which seriously affects the accuracy of fault diagnosis and system maintenance efficiency.

[0094] By determining the storage location of error codes based on the level of the data storage flag signal at the frame header reception time, differentiated error records can be provided for the two types of anomalies mentioned above. For example, cross-slot errors caused by delay can be associated with the time slot where the frame tail is located, while errors caused by frame loss can be associated with the time slot where the frame header is located. Based on this, the origin of the fault can be reflected more accurately, and effective differentiation between delay and frame loss can be achieved.

[0095] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0096] Example 5:

[0097] Figure 10 A flowchart illustrating the timing control method provided in this application is shown below. Figure 10 As shown, the method includes:

[0098] S101. When determining the time slot of a data frame, the first target time slot for storing the time slot error code is determined according to the level state of the data storage flag signal corresponding to the time of receiving the data frame header.

[0099] It should be noted that each time slot has a fixed start and end time. For example, the start time of time slot one is ST1, and the end time is the start time of time slot two, ST2; similarly, the start time of time slot six is ​​ST6, and the end time is END.

[0100] Ideally, the time slot corresponding to a frame is determined based on the received frame header and trailer, and the frame is stored in the receive buffer corresponding to that time slot. However, in actual communication, timing issues or sensor malfunctions may lead to sensor data being received too early, too late, or lost.

[0101] In this embodiment of the application, a Data Storage Flag Line (DSFL) is proposed. By determining the storage location of the error code based on the level state of the data storage flag line at the time of frame header reception, differentiated error records can be provided for two different abnormal situations.

[0102] For example, a sensor data frame refers to a sensor data unit transmitted via the PSI5 protocol, which may include a frame header timestamp and a frame tail timestamp. The frame header timestamp and frame tail timestamp are the start and end timestamps of the sensor data frame, respectively, used to determine the time slot to which the frame belongs.

[0103] Accordingly, it can be determined whether a data frame crosses time slots based on the frame header timestamp and frame tail timestamp. The frame header timestamp and frame tail timestamp determine whether the data frame reception process spans two different time slots. For example, if the frame header timestamp falls within time slot N, while the frame tail timestamp falls within time slot N+1, then the frame is determined to have crossed time slots.

[0104] For example, the frame header reception time, also known as the flag latch time, is used to record the level state of the data storage flag signal.

[0105] For example, the Data Storage Flag Line (DSFL) is a digital level signal used to mark the status of the previous data storage operation, and based on this, to determine the first target time slot for the cross-time slot error code when a data frame is transmitted across time slots.

[0106] In some embodiments, if the level state of the data storage flag signal corresponding to the frame header reception time (flag latching time) of the data frame is a first level state, then the time slot to which the frame header of the data frame belongs is determined to be the first target time slot; if the level state of the data storage flag signal corresponding to the frame header reception time of the data frame is a second level state, then the time slot to which the frame tail of the data frame belongs is determined to be the first target time slot.

[0107] When the frame header arrives, if the data storage flag signal is at the first level, it indicates that the data storage operation in the previous time slot has already been completed and the flag has been reset, meaning the channel is theoretically ready. If the frame is still determined to be across time slots at this time, it means its initial transmission time is significantly behind the start of its allocated time slot. The root cause of the fault is likely the sensor itself sending the frame, such as its power-on delay, internal processing failure, or local clock synchronization deviation. Storing the error code in the time slot containing the frame header marks the error at the direct source of the problem, accurately recording the abnormal sensor response corresponding to this time slot.

[0108] When the frame header arrives, if the data storage flag signal is at the second level, it indicates that the data storage operation in the previous time slot has just been completed, and the flag has not yet been reset. This means that the transmission time of the previous frame was too long, encroaching on the start time of this time slot. In this case, the transmission of the frame in this time slot will inevitably be delayed due to channel occupancy. The root cause of the fault should be traced back to the sensor in the previous time slot, such as its transmitted data frame being too long or interference causing transmission delay. Storing the error code in the next time slot to which the frame tail belongs essentially attributes the error to the previous frame that caused the resource encroachment, accurately reflecting the cascading timing faults caused by the excessive length of the previous frame.

[0109] Based on this, by using the level state of the data storage flag signal, the two different causes of cross-time slot errors can be intelligently distinguished, and the error code can be associated with a more reasonable responsible time slot. This can more clearly indicate the sensor that caused the problem, significantly improving the maintainability and fault location efficiency of the system.

[0110] For example, when the data storage flag signal is at the first level, it indicates that data has been stored in the current time slot; when the data storage flag signal is at the second level, it indicates that no data has been stored in the current time slot.

[0111] For example, the first level state is low and the second level state is high. Then, at the flag latching moment, if the data storage flag signal is low and a frame cross-slot is detected, the first target time slot for storing the cross-slot error code is determined to be the time slot where the frame header is located; if at the flag latching moment, if the data storage flag signal is high and a frame cross-slot is detected, the first target time slot for storing the cross-slot error code is determined to be the time slot where the frame tail is located.

[0112] S102. When the end of a data frame is received, the cross-timeslot error code is stored in the buffer corresponding to the first target timeslot.

[0113] It should be noted that storing data at the end of a frame means that all the information needed to determine whether the frame spans a time slot, and the state of the data storage flag signal at the beginning of the frame, is complete and will not change. Performing the storage operation at this time avoids the risk of state reversal that may occur due to premature decision-making, ensuring the final correctness of the erroneous record.

[0114] For example, the moment when the end of a data frame is received can also be called the data storage moment, indicating when the data frame will be stored.

[0115] For example, a buffer is a storage unit used to temporarily store sensor data frames or error codes.

[0116] Optionally, when the end of a data frame is received, the level of the data storage flag signal is pulled high to the second level; at the beginning of the next time slot, the level of the data storage flag signal is pulled low to the first level.

[0117] Based on this, the timing of the data storage flag signal's generation, changes, and reset is clearly defined, ensuring that the signal accurately reflects the critical historical state of the previous data storage operation's completion. By binding the setting of the data storage flag signal to the complete reception of valid data frames and synchronizing its reset with the system's inherent time slot switching, it is ensured that at each flag latching moment, the level of the data storage flag signal truly represents the end state of the previous storage cycle.

[0118] For example, the data storage flag signal is low by default. During a certain time slot, the data storage flag is pulled high at the time of data storage, and it is automatically pulled low at the beginning of the next time slot. The flag latching time and data storage time are defined on this signal line.

[0119] To facilitate understanding of Embodiment 5, examples are provided to illustrate possible scenarios for data reception and corresponding processing solutions in Embodiment 5:

[0120] Case 1: "Frame correct", such as Figure 11As shown, the host first receives the frame header (L1) of FRAME1 in Tslot1, and records that the data storage flag signal at that moment is low (i.e., the first time slot buffer is currently empty). Then, after receiving the frame tail (S1) of FRAME1, the data storage flag signal goes high, and FRAME1 is stored in the first time slot buffer. The processing scheme for subsequent frames is the same. Figure 11 In this context, BE indicates that the corresponding data has not yet been stored in the cache.

[0121] Scenario 2: "Frame too late", such as Figure 12 As shown, for time slot two, the host first receives the frame header (L2) of FRAME2 in Tslot 2, and records that the data storage flag signal is low at this moment (i.e., the buffer of time slot two is currently empty). Then, in Tslot 3, it receives the frame tail (S2) of FRAME2. Since the data storage flag signal is low at the time of flag latching and FRAME2 is detected to have crossed time slots, the cross-time slot error code is stored in the buffer of time slot two where the frame header is located. Because the buffer of time slot three is temporarily empty, the data storage flag signal is not pulled high during S2.

[0122] Scenario 3: "Frame loss", such as Figure 12 As shown, for slot 4, the host did not receive any frames in slot 4, and the corresponding buffer was empty.

[0123] Scenario 4: "Frame too early", such as Figure 12 As shown, for time slot six, after receiving the frame header (L6) of FRAME6 in Tslot 5, the data storage flag signal is recorded as high at that moment (i.e., the buffer of time slot five is currently not empty). After receiving the frame tail (S6) of FRAME6 in Tslot 6, since the data storage flag signal is high at the time of flag latching and a frame cross-time slot is detected, the cross-time slot error code is stored in the buffer of time slot six where the frame tail is located.

[0124] The "frame too early" anomaly requires special handling for slot 1. For example... Figure 12 As shown, for slot 1, the host receives the frame header (L1) of FRAME1 before ST1, receives the frame tail (S1) of FRAME1 in Tslot1, and detects that the frame crosses a time slot. In this case, the cross-time slot error code can only be stored in the time slot 1 buffer where the frame tail is located.

[0125] In actual communication, timing issues or sensor failures may cause multiple frames of valid information to be received in a certain time slot. Considering the high safety requirements of automotive integrity, the sensor data transmitted by the PSI5 interface is particularly important, and the data must meet high real-time requirements for airbag applications.

[0126] Therefore, in some embodiments, a "data storage priority" is proposed, whereby sensor data has a higher priority than cross-timeslot error codes, and the latest received sensor data has the highest priority. Specifically, if multiple data to be stored are received within the same time slot, the data to be finally stored in the corresponding buffer of that time slot is determined according to the data storage priority rule; wherein, the data storage priority rule includes: the priority of sensor data frames is higher than cross-timeslot error codes.

[0127] In applications with high real-time requirements, such as automotive airbags, the instantaneous state data of sensors directly affects the accuracy and triggering timing of collision judgments. Even if an error code is stored due to a cross-time-slot decision within a time slot, the error code will be overwritten when subsequent valid data frames arrive. The data storage priority rule ensures that the system always retains the valid data that is closest in time to the decision moment within that time slot. This fundamentally avoids the risk of the system using outdated data for safety decisions due to a simple, preconceived strategy. The data selection mechanism directly guarantees the timeliness and accuracy of the safety response, meeting the requirements of the highest functional safety level for automotive electronics (such as ASIL D).

[0128] For example, such as Figure 13 As shown, within Tslot2, the host first stores the cross-timeslot error code of FRAME2 in the timeslot 2 buffer. Then, upon receiving FRAME3, it sorts FRAME3 according to priority, overwriting the cross-timeslot error code and storing it in the timeslot 2 buffer. Within Tslot5, FRAME5 is first stored in the timeslot 5 buffer. Then, upon receiving FRAME6, it sorts FRAME6 according to priority, overwriting FRAME5 and storing it in the timeslot 5 buffer.

[0129] In summary, Example 5 addresses the shortcomings of the existing solution in Example 1. Regarding exception 1 in Example 1, such as... Figure 5 As shown, FRAME2 in time slot 2 and FRAME3 in time slot 3 were received too late, while other frames were received normally. In Example 5, cross-time slot errors were reported in both time slots 2 and 3, and the corresponding buffers stored cross-time slot error codes; for abnormal case 2, such as Figure 6 As shown, FRAME2 in time slot 2 was received too late and FRAME3 was not received, while other frames were received normally. In Example 5, a cross-time slot error was reported only in time slot 2, and the corresponding buffer stored the cross-time slot error code; time slot 3 was empty.

[0130] Example 5 implements correct and different error reports for the two anomalies mentioned above. For anomaly 1, the user can determine that the failure to receive FRAME3 is due to a cross-timeslot error of FRAME3. For anomaly 2, the user can determine that the failure to receive FRAME3 is due to a malfunction in sensor S3.

[0131] Example 5 represents a wise trade-off strategy between functional safety and system reliability. The ASIL-D automotive safety standard requires systems to have fault detection and reporting capabilities. Under this approach, the ECU can perform more intelligent system management upon receiving error reports. Furthermore, cross-time-slot error reporting helps the ECU quickly pinpoint the problem to a specific time slot and corresponding sensor, narrowing down the scope of troubleshooting.

[0132] It should be noted that, in order to provide users with a more flexible time slot monitoring solution, this application also provides Embodiment Six and Embodiment Seven.

[0133] Example 6:

[0134] In this embodiment, only the end time of frames within a time slot is monitored. Each time slot also has a fixed start and end time. The time slot corresponding to the received frame is determined based on the frame tail, and the frame is stored in the corresponding time slot receive buffer. Specifically, based on the time slot to which the received data frame's frame tail reception time belongs, the second target time slot corresponding to the data frame is determined, and the data frame is stored in the buffer corresponding to the second target time slot.

[0135] In this embodiment, the operations of capturing and comparing frame header moments are reduced, which can reduce the requirements for the accuracy and processing power of the microcontroller's timer, or reduce the number of logic gates in the hardware implementation, thereby reducing the implementation cost and power consumption of the system.

[0136] For example, such as Figure 14 As shown, according to the frame end of frame 1, frame 1 is stored in the time slot buffer where the frame end of frame 1 is located; similarly, other frames are stored in the time slot buffer where the frame end of each frame is located.

[0137] However, determining the time slot receive buffer based on the frame tail cannot detect anomalies such as sensor data being received too early or too late, i.e., it does not report cross-time slot errors.

[0138] Therefore, if multiple frames of sensor data are received in a certain time slot, in some embodiments, the latest received sensor data is determined to have the highest priority. Specifically, when multiple data to be stored are received in the same time slot, the data to be stored in the corresponding buffer of that time slot is determined according to the latest sensor data priority rule; wherein, the latest sensor data priority rule includes: the priority of the later received sensor data frame is higher than that of the earlier received sensor data frame.

[0139] If multiple frames of data are received within the same time slot due to interference, retransmission, or anomalies, the latest sensor data priority rule ensures that the system can automatically filter and retain the latest valid data in time.

[0140] For example, such as Figure 15As shown, FRAME1 is stored in the time slot one buffer where its frame tail is located, based on the frame tail (S1) of FRAME1; FRAME2 is stored in the time slot three buffer where its frame tail is located, based on the frame tail (S2) of FRAME2; when FRAME3 is received, it is determined that the frame tail (S3) of FRAME3 should also exist in the time slot three buffer, and FRAME3 is stored in the time slot three buffer according to priority, overwriting FRAME2; similarly, other frames are stored in the time slot buffer where their respective frame tails (Sx) are located.

[0141] In this embodiment, the PSI5 interface can intelligently filter out certain transient, recoverable, and non-critical communication errors (such as minor electromagnetic interference), thereby ensuring that the ECU receives complete sensor data and processes it normally, improving the efficiency and determinism of the system.

[0142] In some embodiments, monitoring is disabled, and received frames are stored sequentially into the time slot buffer in the order they are received. The receive signal line (Slotx Receive Line, SRLx, x=1-6) is raised, and is low by default. Specifically, an independent receive signal line is configured for each time slot, indicating the time slot buffer currently allowed to store data; the receive signal lines corresponding to each time slot are pulled high sequentially according to a preset polling order; the received data frames are sequentially stored into the time slot buffer corresponding to the currently high receive signal line; and all receive signal lines are reset upon receiving the next synchronization pulse.

[0143] For example, such as Figure 16 As shown, after sending the first synchronization pulse, SRL1 is first pulled high, and the received frame 1 is stored in the first time slot buffer; then SRL2 is pulled high, and the received frame 2 is stored in the second time slot buffer, and so on, until all buffers are full. After receiving frame 6, SRL1 is pulled high again, and if a new frame is still received, it is stored in the sixth time slot buffer.

[0144] In this embodiment, the buffer is ensured to always store the most recently received data. However, when multiple sensors are connected to the PSI5 interface, the ECU of this solution cannot determine which sensor the frame data originates from. Figure 17 As shown, since frame 4 is lost, frame 5 of sensor S5 is stored in the time slot four buffer, and frame 6 of sensor S6 is stored in the time slot five buffer.

[0145] Example 7:

[0146] To address the shortcomings of the existing solution in Embodiment 2, Embodiment 7 proposes an unexpected SYNC Pulse exception handling scheme, which includes a Receive Enable Line (REL) and an Unexpected SYNC Pulse Flag (USPF).

[0147] Specifically, after sending a synchronization pulse, after a preset blanking time, the receive enable signal is set to an active state to allow the reception of sensor data frames; when the preset reception end time is reached, the receive enable signal is set to an inactive state to stop the reception of sensor data frames; if a new synchronization pulse is detected while the receive enable signal is active, an unexpected synchronization pulse error is reported, and the currently received data frame is discarded.

[0148] For example, such as Figure 18 As shown, the receive enable signal is low by default. The ECU sends a synchronization pulse, and after the blanking time (BT), the receive enable signal goes high, indicating that any sensor data frames received during this period are stored in the corresponding time slot buffer. The purpose of the blanking time is to prevent abnormal current on the bus due to noise or other anomalies from affecting the reception of normal data after the synchronization pulse is sent. When the reception end time is reached, the receive enable signal goes low, and the reception of sensor data frames stops under the current synchronization pulse. The receive enable signal goes high again after the next synchronization pulse is sent.

[0149] Unexpected synchronization pulse anomaly, such as Figure 19 As shown, during FRAME3 reception, the ECU unexpectedly sends the next synchronization pulse. At this time, the receive enable signal is detected to be high, so the unexpected synchronization pulse flag is pulled high, reporting an unexpected synchronization pulse error (USPF is high), and the unreceived FRAME3 frame is discarded. The next synchronization pulse is then triggered normally (REL is low), and each sensor sequentially sends frame data (REL is high). By reporting an "unexpected synchronization pulse error," the user can determine that the "empty receive buffer in time slots three / four / five / six within range ①" is due to an abnormal synchronization pulse transmission, rather than a fault in sensors S3 / S4 / S5 / S6. This unexpected synchronization pulse error handling scheme solves the shortcomings of the existing scheme in Example 2.

[0150] Example 8

[0151] To address the shortcomings of the existing solution in Example 3, this embodiment proposes a "slot configuration error detection scheme." This scheme includes a slot configuration error flag (SCEF) and valid / invalid time slots. Specifically, based on multiple preset time slot configuration parameters, the start and end times of each time slot are determined; the start and end times are sorted and verified; if a timing error is detected during verification, a time slot configuration error is reported, and the time slot range with timing errors is marked as invalid time slots; only received data frames are stored in the buffer corresponding to the valid time slots.

[0152] like Figure 20 As shown, the ECU sends a synchronization pulse, and the timer starts counting at Timer Start. When the TL0 threshold is reached, it is the start time (ST1) of Tslot1; when counting to the TL1 threshold, it is the end time of Tslot1 and also the start time (ST2) of slot2; similarly, when finally counting to the END threshold, it is the end time (END) of the last Tslot. That is, ST1 < ST2 < ST3 < ST4 < ST5 < ST6 < END is the correct configuration.

[0153] In practical applications, abnormal configurations by users may occur, such as Figure 21 As shown, after the user configures the start and end times of all time slots, the hardware needs to sort these times before performing time slot monitoring and storage. When ST2 < ST1 is detected, SCEF is pulled high to report "time slot configuration error (SCEF is at high level)". During normal communication, the ECU sends a synchronization pulse and sequentially receives FRAME1 - 6. In this abnormal situation, there are seven time slot ranges. Range ① is ST2 < ST1, which is determined to be an invalid time slot; range ② is ST1 < ST3 but ST2 does not appear between them, which is determined to be an invalid time slot; range ③ is ST2 < ST3, which conforms to the correct configuration and is determined to be a valid time slot. Similarly, ranges ④ - ⑦ are valid time slots. Only the frames received in the valid time slots are stored in the corresponding receive buffer. Therefore, FRAME2 is determined to belong to slot2 and is stored in the slot2 receive buffer; FRAME1 is not within any time slot and is discarded; FRAME3 - 6 are normally stored in the corresponding time slot buffers. By reporting the "time slot configuration error", the user can determine that the reason for not receiving FRAME1 is due to the time slot configuration rather than a fault in sensor S1. Therefore, the time slot configuration error detection scheme proposed in Embodiment Eight solves the defects of the existing scheme in Example Three.

[0154] Embodiment Nine:

[0155] To solve the defects of the existing scheme in Example Four, this embodiment proposes a "scheme for delaying synchronization pulses between multiple channels", and this scheme includes a synchronization pulse delay time (SYNC Delay Time, SDT). Specifically, a preset delay time is provided between the synchronization pulses of the first communication channel and the second communication channel; among them, the first communication channel and the second communication channel are used to connect different sensors.

[0156] Exemplarily, when the widths (Tsync1 and Tsync2) of the synchronization pulses of the two channels are the same, the delay SDT between SYNC1 and SYNC2 is achieved.

[0157] For example, in the case of three or more channels, the first communication channel can be a reference channel, the second communication channel can be any other channel, the second communication channel has a delay time compared to the reference channel, and different second communication channels have different delay times compared to the reference channel.

[0158] An exemplary multi-channel sensor connection topology diagram, such as... Figure 22 As shown. The synchronization pulses (SYNC1 and SYNC2) of the two channels have the same trigger time, as... Figure 23 As shown, at point t1, both channel 1 and channel 2 are configured to automatically trigger synchronization pulses (ch#1 Auto Trigger & ch#2 Auto Trigger). The delay between the synchronization pulse (SYNC1) of channel 1 and the synchronization pulse (SYNC2) of channel 2 is fixed at SDT. The purpose is to improve anti-interference capability (especially in long-haul or high-EMI environments, such as automotive applications) and improve power supply stability through load balancing. Furthermore, after the PSI5 transceiver receives sensor data via PSI5 communication, the host needs to read the sensor data through other communication methods (including but not limited to SPI communication). A reasonable time interval between sensor data provides sufficient processing time for the user and optimizes SPI data transmission efficiency. The synchronization pulse delay scheme between multiple channels proposed in this embodiment solves the shortcomings of the existing scheme in Example 4.

[0159] Considering that the trigger times of the synchronization pulses (SYNC1 and SYNC2) for the two channels may be inconsistent, such as Figure 24 As shown, at point t2, channel 1 is configured to automatically trigger the synchronization pulse (ch#1 Auto Trigger); at point t3, channel 2 is configured to automatically trigger the synchronization pulse (ch#2 Auto Trigger). This software-configured delay is too resource-intensive for controlling time precision. To achieve high-precision delay, this invention implements the first synchronization pulse trigger point of channel 2 as the next synchronization pulse (SYNC1_x+1) of channel 1 plus an SDT delay, and the delay between subsequent synchronization pulses of channel 1 (SYNC1_x+2) and channel 2 (SYNC2_2) is fixed at SDT. This scheme is suitable for automotive electronic systems operating for extended periods.

[0160] Figure 25 A schematic diagram of the structure of the electronic device provided in this application. Figure 25 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus 504.

[0161] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0162] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0163] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0164] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0165] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0166] This application also provides a vehicle including the aforementioned electronic equipment.

[0167] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0168] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0169] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0170] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0171] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0172] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0173] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0174] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0175] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0176] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A timing control method, characterized in that, include: When determining the time slot of a data frame, the first target time slot for storing the time slot error code is determined based on the level state of the data storage flag signal corresponding to the time of receiving the frame header of the data frame. Upon receiving the end of a data frame, the cross-timeslot error code is stored in the buffer corresponding to the first target timeslot.

2. The method according to claim 1, characterized in that, The step of determining the first target time slot for storing cross-time slot error codes based on the level state of the data storage flag signal corresponding to the frame header reception time of the data frame includes: If the data storage flag signal is at a first level, then the time slot to which the frame header of the data frame belongs is determined to be the first target time slot. If the data storage flag signal is at the second level, then the time slot to which the frame tail of the data frame belongs is determined to be the first target time slot.

3. The method according to claim 2, characterized in that, The method further includes: Upon receiving the end of a data frame, the level of the data storage flag signal is pulled high to the second level state; At the start of the next time slot, the level of the data storage flag signal is pulled low to the first level.

4. The method according to claim 1, characterized in that, The method further includes: When multiple pieces of data to be stored are received in the same time slot, the data to be finally stored in the corresponding buffer area of ​​the time slot is determined according to the data storage priority rules. The data storage priority rule includes: sensor data frames have a higher priority than cross-timeslot error codes.

5. The method according to claim 1, characterized in that, The method further includes: The second target time slot corresponding to the data frame is determined based on the time slot to which the received data frame tail reception time belongs; The data frame is stored in the buffer corresponding to the second target time slot.

6. The method according to claim 5, characterized in that, The method further includes: When multiple data to be stored are received in the same time slot, the data to be stored in the corresponding buffer area of ​​that time slot is determined according to the priority rule of the latest sensor data. The latest sensor data priority rule includes: the priority of the sensor data frame received later is higher than that of the sensor data frame received earlier.

7. The method according to claim 1, characterized in that, The method further includes: Each time slot is configured with an independent receive signal line, which is used to indicate the time slot buffer area currently allowed to store data; According to the preset polling order, the receiving signal lines corresponding to each time slot are pulled up sequentially; The received data frames are stored sequentially into the time slot buffer corresponding to the currently high receive signal line; When the next synchronization pulse is detected, all receive signal lines are reset.

8. The method according to claim 6 or 7, further comprising: After sending the synchronization pulse, after a preset blanking time, the receive enable signal is set to an active state to allow the reception of sensor data frames. When the preset reception end time is reached, the reception enable signal is set to an invalid state to stop receiving sensor data frames; If a new synchronization pulse is detected while the receive enable signal is active, an unexpected synchronization pulse error is reported, and the currently received data frame is discarded.

9. The method according to claim 1, characterized in that, The method further includes: Based on multiple preset time slot configuration parameters, determine the start and end times of each time slot; The start and end times are sorted and verified. If a timing error is detected during the verification, a time slot configuration error will be reported, and the time slot range with the timing error will be marked as an invalid time slot. Only the received data frames are stored in the buffer corresponding to the valid time slot.

10. The method according to claim 1, characterized in that, Also includes: A preset delay time is maintained between the synchronization pulses of the first communication channel and the second communication channel; The first communication channel and the second communication channel are used to connect different sensors.

11. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-10.

12. A vehicle, characterized in that, Includes the electronic device as described in claim 11.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-10.

14. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-10.

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