A method of fabricating a metal-oxide-semiconductor field effect transistor and a structure

Abstract

The application provides a metal-oxide semiconductor field effect transistor preparation method and structure. Through in-situ dielectric doping treatment of one side surface of an oxide layer back-epitaxy wafer based on plasma, a transition layer is obtained, and the lattice structure of the composition in the transition layer is between the composition in the oxide layer and the composition in the ion blocking protection layer, so that the stability of the lattice change when the oxide layer changes to the ion blocking protection layer is improved, the problem of lattice fracture is reduced, and the stress between the two is reduced. In addition, the transition layer prepared by using the in-situ dielectric doping treatment can realize that the interface between the prepared transition layer and the oxide layer has no gap, improve the density and anti-injection property of the transition layer, can block impurity ions, avoid the impurity ions from entering the oxide layer to cause the prepared oxide layer to have leakage after thickening, and improve the product performance.

Description

Technical Field

[0001] This application belongs to the field of semiconductors, and in particular relates to a method and structure for fabricating a metal-oxide-semiconductor field-effect transistor. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are core semiconductor devices in electronic engineering, with P-channel VDMOS (vertical double-diffused metal-oxide-semiconductor field-effect transistors) being widely used in power management, automotive electronics, and other fields. Currently, to improve switching speed and reduce switching losses, a localized thick oxide process (LOCOS, Local Oxidation of Silicon) is typically performed on the gate oxide. In previous products, the device exhibited gate leakage after the pre-gate oxide process, posing a risk of the following problems: (1) Power consumption will still be generated when the device is off, which will cause abnormal local heating of the device; (2) Gate-source leakage may cause threshold voltage drift; (3) The extra power consumption caused by gate-source leakage causes local heating in the leakage path of the device, which accelerates the aging of the gate oxide layer and affects the service life of the device. (4) If the leakage current is too large, it may evolve into a gate-source short circuit, which will directly cause the device to malfunction. (5) As the temperature rises, leakage current will increase, which will worsen the stability of the device in high-temperature operating environments. Summary of the Invention

[0003] This application provides a method and structure for fabricating a metal-oxide-semiconductor field-effect transistor, which can solve the problem of gate leakage current in the device after the pre-gate oxide process.

[0004] In a first aspect, embodiments of this application provide a method for fabricating a metal-oxide-semiconductor field-effect transistor, the method comprising: Obtain an epitaxial wafer and prepare an oxide layer on one side surface of the epitaxial layer in the epitaxial wafer; A transition layer is obtained by in-situ dielectric doping of one side of the oxide layer facing away from the epitaxial wafer using plasma; the lattice structure of the composition in the transition layer is between that in the oxide layer and that in the ion barrier protective layer. An ion-barrier protective layer is prepared on the surface of the transition layer facing away from the epitaxial wafer; Etching removes the transition layer and ion-blocking protective layer in the corresponding oxide layer to be thickened, and a thickened oxide layer is prepared in the region to be thickened. The transition layer and ion barrier layer are removed, and the gate structure, source structure and drain structure are fabricated to obtain a vertically double-diffused metal-oxide-semiconductor field-effect transistor.

[0005] In one feasible implementation, the above-described preparation of an ion-barrier protective layer on the side of the transition layer facing away from the epitaxial wafer includes: On the side of the transition layer facing away from the epitaxial wafer, multiple sub-protective layers are sequentially prepared, and the content of the intralayer ion blocking component facing away from the transition layer in two adjacent sub-protective layers is greater than the content of the intralayer ion blocking component facing towards the transition layer, thus forming a gradient ion blocking protective layer.

[0006] In one feasible implementation, the above-described method of obtaining the epitaxial wafer includes: Obtain silicon-based epitaxial wafers; The oxide layer is a silicon dioxide layer, the transition layer is a silicon oxynitride layer, and the ion barrier protective layer is a silicon nitride layer.

[0007] In one feasible implementation, after removing the transition layer and ion-barrier protective layer, and before fabricating the gate structure, source structure, and drain structure to obtain a vertically double-diffused metal-oxide-semiconductor field-effect transistor, the method further includes: Continue etching to remove the oxide layer and grow the gate oxide layer.

[0008] In one feasible implementation, the above-described fabrication of the source and drain structures includes: A first type of doped ions are implanted into a first predetermined region on the side of the epitaxial layer that is close to the gate oxide layer to form a trap region; The well region is annealed once using the first annealing temperature; the first annealing temperature is not higher than the preparation temperature of the thickened oxide layer. The well region is annealed a second time using a second annealing temperature; the first annealing temperature is lower than the second annealing temperature. A first type of doped ion is injected into a second predetermined region on the side of the epitaxial layer toward the gate oxide layer to form a first heavily doped region; the second predetermined region is located within the first predetermined region. A second type of dopant ions are implanted into a third preset region on the side of the epitaxial layer toward the gate oxide layer to form a second heavily doped region; the third preset region is located within the first preset region and is located beside the second preset region along the extension direction of the epitaxial layer surface.

[0009] In one feasible implementation, the distance between the aforementioned well region and the thickened oxide layer is greater than a first preset distance; The first preset distance is the sum of the distance affected by the thickened oxide layer and the distance of the well region pushing the junction outward.

[0010] In one feasible implementation, the above-described fabrication of the gate structure includes: On the side of the gate oxide layer and the thickened oxide layer facing away from the epitaxial layer, a polycrystalline layer is prepared corresponding to the fourth preset region as the gate structure; the fourth preset region is the entire area of ​​the epitaxial layer surface except for the first preset region. A first type of doped ions is implanted into a first predetermined region on the side of the epitaxial layer adjacent to the gate oxide layer to form a well region, including: A first photoresist is prepared on the side of the epitaxial layer facing the gate oxide layer, and the opening of the first photoresist corresponds to the first preset region. A trap region is formed by injecting first type doped ions into a first preset region based on the first photoresist; The first photoresist covers the polycrystalline layer, and its edge extends beyond the polycrystalline layer by a second preset distance; the second preset distance is the minimum distance at which the first photoresist blocks the implantation of first type doped ions into the polycrystalline layer.

[0011] In one feasible implementation, after implanting first-type doped ions in a second predetermined region on the side of the epitaxial layer toward the gate oxide layer to form a first heavily doped region, and before implanting second-type doped ions in a third predetermined region on the side of the epitaxial layer toward the gate oxide layer to form a second heavily doped region, the method further includes: The gate oxide layer in the uncovered areas of the polycrystalline layer is removed, and an oxide layer is grown to serve as a cushion oxide layer. Secondly, embodiments of this application provide a metal-oxide-semiconductor field-effect transistor, comprising: An epitaxial wafer includes a substrate and an epitaxial layer grown on one side of the substrate. A gate oxide layer is disposed on the side surface of the epitaxial layer facing away from the substrate; The oxide layer is thickened by a transition layer and an ion barrier layer in the region of the gate oxide layer to be thickened. The transition layer is disposed on the side surface of the oxide layer facing away from the epitaxial layer, and is obtained by in-situ dielectric doping of the side surface of the oxide layer facing away from the epitaxial layer using plasma. The lattice structure of the composition in the transition layer is between that of the composition in the oxide layer and the lattice structure of the composition in the ion barrier layer. The ion barrier layer is disposed on the side surface of the transition layer facing away from the epitaxial layer. Before the gate oxide layer is fabricated, the oxide layer is disposed on the side surface of the epitaxial layer facing away from the substrate. The gate structure is disposed on the side surface of the gate oxide layer and the thickened oxide layer facing away from the epitaxial layer after the transition layer and ion blocking protective layer have been removed. The source and drain structures are respectively disposed in corresponding regions of the epitaxial layer and cooperate with the gate structure and gate oxide layer to form a vertical double-diffused metal-oxide-semiconductor field-effect transistor.

[0012] In one feasible implementation, the ion-blocking protective layer described above includes a plurality of sub-protective layers; In two adjacent sub-protective layers, the content of the intralayer ion-blocking component facing away from the transition layer is greater than the content of the intralayer ion-blocking component facing towards the transition layer, forming a gradient ion-blocking protective layer.

[0013] The metal-oxide-semiconductor field-effect transistor fabrication method and structure of this application embodiment obtain a transition layer by performing in-situ dielectric doping treatment on one side surface of the oxide layer facing away from the epitaxial wafer based on plasma. The crystal structure of the components in the transition layer is between the components in the oxide layer and the components in the ion barrier layer, so as to improve the stability of the crystal change during the transition from the oxide layer to the ion barrier layer, reduce the problem of lattice breakage, and reduce the stress between the two. In addition, the transition layer prepared by in-situ dielectric doping treatment can achieve a gapless interface between the prepared transition layer and the oxide layer, improve the density and implantation resistance of the transition layer, block impurity ions, and prevent impurity ions from entering the oxide layer and causing leakage after the thickened oxide layer is prepared, thereby improving product performance. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic flowchart of a method for fabricating a metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of an existing metal-oxide-semiconductor field-effect transistor; Figure 3 This is a schematic diagram of a structure for preparing an oxide layer on one side surface of an epitaxial wafer, provided in an embodiment of this application. Figure 4 This is a schematic diagram of a structure with a transition layer provided in an embodiment of this application; Figure 5 This is a schematic diagram of a structure for preparing an ion-blocking protective layer on the surface of a transition layer, provided in an embodiment of this application. Figure 6 This is a schematic diagram of a structure with a gradient ion blocking protective layer provided in an embodiment of this application; Figure 7 This is a schematic diagram of a structure for graphically processing a transition layer and an ion barrier protective layer, provided in an embodiment of this application. Figure 8 This is a schematic diagram of a structure with a thickened oxide layer provided in an embodiment of this application; Figure 9This is a schematic diagram of a structure for removing the transition layer and ion barrier protective layer provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of a metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application; Figure 11 This is a schematic flowchart of a method for fabricating a source structure and a drain structure provided in an embodiment of this application; Figure 12 This is a schematic diagram of a structure in which a first photoresist is prepared on the surface of a polycrystalline layer, according to an embodiment of this application. Figure 13 This is a schematic diagram of a trap region implantation structure formed by first photoresist implantation, provided in an embodiment of this application. Figure 14 This is a schematic diagram of a structure for completing the fabrication of the trap region provided in an embodiment of this application; Figure 15 This is a schematic diagram of a structure for fabricating a first heavily doped region based on a second photoresist, provided in an embodiment of this application. Figure 16 This is a schematic diagram of a structure for fabricating a second doped region based on a third photoresist, provided in an embodiment of this application. Figure 17 This is a schematic diagram of a structure for removing an oxide layer provided in an embodiment of this application; Figure 18 This is a schematic diagram of the structure after the gate oxide layer has been re-fabricated, as provided in an embodiment of this application; Figure 19 This is a flowchart illustrating a method for fabricating a metal-oxide-semiconductor field-effect transistor provided in an application scenario embodiment of this application; Figure 20 This is a simulation diagram of the electric field morphology near a thickened oxide layer in the prior art; Figure 21 This is a simulation diagram of the electric field morphology near a thickened oxide layer provided in an embodiment of this application; Figure 22 This is a simulation diagram comparing the electric field strength near a thickened oxide layer with that provided in the embodiments of this application; Figure 23 This is a cell simulation diagram of a process with a thickened oxide layer in the prior art; Figure 24 This is a cell simulation diagram of a preparation with a thickened oxide layer provided in the embodiments of this application; The attached figures are labeled as follows: 201-Substrate, 202-Epipolar layer, 203-Gate oxide layer, 204-Polycrystalline layer, 205-Trap region, 206-Second doped region, 207-Isolation dielectric layer, 208-Front side metal, 209-Back side metal, 210-Passivation layer; 301 - Epitaxial wafer, 302 - Oxide layer; 401 - Transition Layer; 501 - Ion Barrier Protective Layer; 601 - First sub-protective layer; 602 - Second sub-protective layer; 801 - Thickened oxide layer; 1201 - First photoresist; 1301 - Tunnel injection structure; 1501 - Second photoresist, 1502 - First heavily doped region, 1503 - Third photoresist, 1504 - Second heavily doped region. Detailed Implementation

[0016] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0017] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0018] Taking the P-channel VDMOS device in metal-oxide-semiconductor field-effect transistors as an example, the existing fabrication process generally includes the following steps: substrate preparation → growth of a thin oxide layer → preparation of a silicon nitride mask → local thermal oxidation of LOCOS → removal of the silicon nitride mask → gate oxide growth → polysilicon deposition and etching → N-well + NSD (N-type heavily doped region) implantation → diffusion → PSD (P-type heavily doped region) implantation, etc.

[0019] However, the above process has the problem of gate leakage. In the above-mentioned prior art, specifically because there are many interface defects between the prepared silicon nitride mask and the thin oxide layer, after the silicon nitride mask is removed, the thin oxide layer containing defects is retained in the structure.

[0020] The method for fabricating metal-oxide-semiconductor field-effect transistors provided in the embodiments of this application will be described below.

[0021] This application embodiment obtains a transition layer by performing in-situ dielectric doping on one side surface of the oxide layer facing away from the epitaxial wafer based on plasma. The lattice structure of the components in this transition layer is between that in the oxide layer and that in the ion barrier layer, thereby improving the stability of the lattice change during the transition from the oxide layer to the ion barrier layer, reducing the problem of lattice breakage, and lowering the stress between the two. In addition, the transition layer prepared by in-situ dielectric doping can achieve a gapless interface between the prepared transition layer and the oxide layer, improving the density and implantation resistance of the transition layer, blocking impurity ions, and preventing impurity ions from entering the oxide layer and causing leakage after the thickened oxide layer is prepared, thus improving product performance.

[0022] Figure 1 A schematic flowchart of a method for fabricating a metal-oxide-semiconductor field-effect transistor according to an embodiment of this application is shown. Figure 1 As shown, the method may include the following steps: S101: Obtain an epitaxial wafer and prepare an oxide layer on one side surface of the epitaxial layer in the epitaxial wafer; S102: The oxide layer is subjected to in-situ dielectric doping on one side of the epitaxial wafer based on plasma to obtain a transition layer; the lattice structure of the composition in the transition layer is between the composition in the oxide layer and the composition in the ion barrier protective layer. S103: An ion-barrier protective layer is prepared on the surface of the transition layer facing away from the epitaxial wafer; S104: Etching removes the transition layer and ion barrier protective layer in the corresponding oxide layer to be thickened, and prepares a thickened oxide layer in the area to be thickened. S105: Remove the transition layer and ion barrier layer, and fabricate the gate structure, source structure and drain structure to obtain a vertical double-diffused metal-oxide-semiconductor field-effect transistor.

[0023] This application embodiment utilizes plasma to perform in-situ dielectric doping on one side of the oxide layer facing away from the epitaxial wafer, resulting in a transition layer. The lattice structure of the components within this transition layer is intermediate between those within the oxide layer and those within the ion barrier layer. This improves the stability of the lattice change during the transition from the oxide layer to the ion barrier layer, reduces the occurrence of lattice breakage, and lowers the stress between the two layers. Furthermore, the transition layer prepared using in-situ dielectric doping can achieve a gapless interface between the transition layer and the oxide layer, improving the density and implantation resistance of the transition layer. It can also block impurity ions, preventing impurity ions from entering the oxide layer and causing leakage after the thickened oxide layer is prepared, thus improving product performance.

[0024] The following is a detailed explanation of each step: First, before describing the fabrication method of the metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application, a conventional metal-oxide-semiconductor field-effect transistor will be introduced, for details of which can be found in [reference needed]. Figure 2 , Figure 2 This is a schematic diagram of the structure of a metal-oxide-semiconductor field-effect transistor. It includes a substrate 201, an epitaxial layer 202 grown on the upper surface of the substrate 201, a gate oxide layer 203 formed on the upper surface of the epitaxial layer 202, a polycrystalline layer 204 formed on the upper surface of the gate oxide layer 203, a well region 205 formed by implantation and annealing in the epitaxial layer 202, a first heavily doped region and a second heavily doped region 206 formed in the well region 205, an isolation dielectric layer 207 disposed outside the polycrystalline layer 204 and the gate oxide layer 203 to isolate a front-side metal 208, a passivation layer 210 disposed on the upper surface of the front-side metal 208, and a back-side metal 209 disposed on the lower surface of the substrate 201. No thickened oxide layer is provided in this back-side metal.

[0025] In S101 of this embodiment, a P-type vertical double-diffused metal-oxide-semiconductor field-effect transistor can be adapted. Therefore, the epitaxial wafer 301 can be a corresponding P-type silicon-based epitaxial wafer, which may include a P-type silicon substrate and a P-type epitaxial layer grown on the surface of the P-type silicon substrate; or it can be adapted to an N-type vertical double-diffused metal-oxide-semiconductor field-effect transistor. The structure of existing metal-oxide-semiconductor field-effect transistors can be referred to. Figure 2 , Figure 2This is a schematic diagram of a conventional metal-oxide-semiconductor field-effect transistor (MOSFET). The diagram does not show a thickened oxide layer. Directly fabricating this thickened oxide layer would lead to increased defects within the silicon nitride (Si) film during the high-temperature annealing process after N-well implantation following the preparation of the Si / O2 protective layer (LOCOS). This would prevent effective impurity ion diffusion, allowing impurity ions to easily penetrate through defect regions at the LOCOS edge to the gate oxide-silicon interface. Furthermore, the interface between Si / O2 and the gate oxide layer 203 is prone to stress at high temperatures due to the difference in thermal expansion coefficients between the two materials. This results in defects at the interface between the thickened oxide layer and the gate oxide layer 203 in subsequent processes, causing gate-source leakage. However, the structure in this embodiment utilizes a transition layer obtained through in-situ dielectric doping. This layer not only blocks impurity ions but also reduces the difference in thermal expansion coefficients between the gate oxide layer 203 and the ion-blocking protective layer, thus reducing interface stress.

[0026] Furthermore, in this embodiment, an oxide layer 302 can be prepared on the surface of the epitaxial layer 202 of the epitaxial wafer 301 away from the substrate 201 using a thermal oxidation process. This prepared oxide layer 302 is a thin oxide layer, serving as the substrate for subsequent transition layers and ion-barrier protective layers, and also as the basis for the gate oxide structure. The structure obtained after this S101 process can be referred to... Figure 3 , Figure 3 This is a schematic diagram of a structure for preparing an oxide layer on one side surface of an epitaxial wafer, provided in an embodiment of this application.

[0027] In S102, in this embodiment of the application, nitrogen plasma can be used to perform in-situ dielectric doping treatment on the side surface of the prepared oxide layer 302 facing away from the epitaxial wafer 301. Nitrogen gas can be selected as the treatment atmosphere. Through this in-situ dielectric doping treatment, a SiON (silicon oxynitride) transition layer is formed on the surface of the thin oxide layer.

[0028] In this embodiment, the main component of the thin oxide layer can be SiO2 (silicon dioxide), while the main component of the subsequently prepared ion barrier layer is Si3N4 (silicon nitride). The SiON transition layer prepared in this embodiment contains silicon, oxygen, and nitrogen elements, and its lattice structure is between SiO2 and Si3N4. This allows for lattice matching between silicon dioxide and silicon nitride, effectively mitigating the difference in thermal expansion coefficients between the oxide layer 302 and the ion barrier layer in subsequent steps and reducing interfacial stress. The structure obtained after this S102 preparation can be referred to... Figure 4 , Figure 4 This is a schematic diagram of a structure with a transition layer provided in an embodiment of this application.

[0029] In step S103, specifically in this embodiment, a chemical vapor deposition process can be used to prepare an ion-barrier protective layer 501 on the side of the transition layer 401 facing away from the epitaxial wafer 301, thereby enhancing the ability to block impurity diffusion during subsequent ion implantation. The structure obtained after step S103 can be referred to... Figure 5 , Figure 5 This is a schematic diagram of a structure for preparing an ion-blocking protective layer on the surface of a transition layer, provided in an embodiment of this application.

[0030] In one feasible embodiment, to improve the impedance effect against impurity ions, the preparation of an ion-blocking protective layer 501 on the side of the transition layer 401 facing away from the epitaxial wafer 301 may include: On the side of the transition layer 401 facing away from the epitaxial wafer 301, multiple sub-protective layers are sequentially prepared, and the content of the intralayer ion blocking component facing away from the transition layer 401 in two adjacent sub-protective layers is greater than the content of the intralayer ion blocking component facing towards the transition layer 401, thus forming a gradient ion blocking protective layer.

[0031] In this embodiment, the structure of the gradient ion blocking protective layer can be referred to Figure 6 , Figure 6 This is a schematic diagram of a structure with a gradient ion-barrier protective layer provided in an embodiment of this application. Figure 6 The nitrogen content in the first sub-protective layer 601 is less than the nitrogen content in the second sub-protective layer 602. Taking the aforementioned transition layer 401 as a silicon oxynitride transition layer and the ion barrier protective layer 501 as a silicon nitride protective layer as an example, the ion barrier protective layer 501 is specifically set as a gradient silicon nitride protective layer, with nitrogen as the ion barrier component. On the side of the silicon oxynitride transition layer facing away from the epitaxial wafer 301, the first sub-protective layer, the second sub-protective layer, and the third sub-protective layer can be sequentially prepared using a chemical vapor deposition process. The nitrogen content in the first sub-protective layer is less than that in the second sub-protective layer, and the nitrogen content in the second sub-protective layer is less than that in the third sub-protective layer. In adjacent sub-protective layers, the nitrogen content in the layer facing away from the transition layer 401 is greater than that in the layer closer to the transition layer 401, forming a gradient ion barrier protective layer with nitrogen content increasing from bottom to top. This ensures the blocking effect of the outer sub-protective layer on impurity ions while improving the lattice compatibility between the inner sub-protective layer and the oxide layer 302, avoiding stress delamination.

[0032] In one feasible embodiment, in order to reduce interface defects, improve the ability to block impurities, suppress gate leakage current, and improve the reliability and electrical performance of the device, the above-mentioned acquisition of epitaxial wafer 301 may include: Obtain silicon-based epitaxial wafers; The oxide layer 302 is a silicon dioxide layer, the transition layer 401 is a silicon oxynitride layer, and the ion barrier protective layer 501 is a silicon nitride layer.

[0033] In this embodiment, the silicon-based epitaxial wafer is obtained, specifically a P-type silicon-based epitaxial wafer. The P-type silicon-based epitaxial wafer includes a P-type silicon substrate and a P-type epitaxial layer grown on the surface of the P-type silicon substrate. In this embodiment, the silicon dioxide layer can be prepared on the surface of the epitaxial layer 202 of the P-type silicon-based epitaxial wafer using a thermal oxidation process. The silicon oxynitride layer can be formed by in-situ dielectric doping of the side of the silicon dioxide layer facing away from the epitaxial wafer 301 using nitrogen plasma, and its lattice structure is intermediate between silicon dioxide and silicon nitride. The silicon nitride layer can be prepared by chemical vapor deposition to sequentially prepare multiple sub-protective layers to form a gradient structure. Each sub-protective layer is made of silicon nitride. In two adjacent sub-protective layers, the nitrogen content in the sub-protective layer facing away from the transition layer 401 is greater than the nitrogen content in the sub-protective layer closer to the transition layer 401.

[0034] In S104, in this embodiment of the application, a spin coating process can be used to deposit photoresist on the side of the ion barrier protective layer 501 facing away from the transition layer 401. Then, a photolithography process is used to expose, develop, and etch the photoresist according to a preset LOCOS window pattern to form a photoresist mask, which is used to block the transition layer 401 and the ion barrier protective layer 501 in areas that are not to be thickened.

[0035] Then, using the photoresist mask formed above as a shield, a dry etching process is employed to etch away the area to be thickened in the oxide layer 302. This area is the region where LOCOS will subsequently grow with locally thick oxide, including the transition layer 401 and the ion barrier layer 501. The etching gas is a mixture of CF4 (carbon tetrafluoride) and O2 (oxygen), with a volume ratio of CF4 to O2 of 4:1, ensuring complete exposure of the oxide layer 302 in the area to be thickened. After etching, the photoresist mask is removed, and a dry-wet-dry composite thermal oxidation process is used to prepare a thickened oxide layer 801 in the area to be thickened, with a mixture of oxygen and water vapor in the atmosphere. The structure obtained after this S104 process can be referenced. Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of a structure for graphically processing a transition layer and an ion barrier protective layer, provided in an embodiment of this application. Figure 8 This is a schematic diagram of a structure with a thickened oxide layer provided in an embodiment of this application.

[0036] In S105, the removal of the transition layer 401 and the ion barrier protective layer 501 is generally carried out by dry etching process. The unetched transition layer 401 and ion barrier protective layer 501 are etched away. The etching gas can also be a mixture of CF4 and O2 to ensure that the transition layer 401 and the ion barrier protective layer 501 are completely removed.

[0037] The gate structure can be fabricated using a dry-wet-dry composite oxidation process to grow the gate oxide layer 203. Then, a chemical vapor deposition process can be used to deposit polycrystalline silicon to form a polycrystalline layer. After deposition, polycrystalline implantation is performed, with phosphorus ions implanted to reduce gate resistance. This embodiment requires etching a portion of the polycrystalline layer. This etching is performed within a total operation time of less than 100 hours after equipment inspection and maintenance. Furthermore, three dummy wafers can be produced before the formal etching to verify process stability. Dry etching can be used, and a mixture of CF4 and Cl2 (chlorine) can be selected as the etching gas. After etching, over-etching of the gate oxide layer 203 can be performed to avoid thick polycrystalline layer etching residue and prevent leakage between the gate and source caused by residual polycrystalline layer.

[0038] The fabrication of the source structure can include N-well implantation and annealing. Specifically, photoresist can be deposited using a spin coating process, and the N-well window can be etched using photolithography and etching processes. Then, the first main implantation of the N-well can be performed, and phosphorus ions can be used for implantation. After implantation, the photoresist can be removed using a wet stripping process. Subsequently, N-well annealing is performed to activate the implanted impurities in the N-well, repair lattice damage, control the size of impurity diffusion, and finally enable the N-well to form the target size.

[0039] Then, N-well filling is performed. Photoresist can be used for blocking, and the implanted ions can also be phosphorus ions, whose main function is to form N. + The contact area facilitates subsequent contact with the source metal. After implantation, the photoresist can be removed using a wet stripping process. Annealing is then performed, with the annealing atmosphere typically set to nitrogen, to repair implantation damage and activate impurities. Finally, the source region P... + Contact region injection is performed, followed by annealing in a nitrogen atmosphere to activate injected impurities and repair injection damage. In this embodiment, source region P... + Contact area implantation can specifically employ boron ion implantation. Compared to the existing use of boron difluoride ions, boron ions have a smaller mass and a deeper penetration depth, thus avoiding interface damage caused by boron difluoride ion implantation on shallow surfaces.

[0040] Then, a chemical vapor deposition process can be used to deposit an isolation dielectric layer 207. Photolithography and etching processes can be used to etch holes in the isolation dielectric layer 207 to expose the source and gate contact areas. Then, a sputtering process can be used to deposit metal electrodes. Photolithography and etching processes can be used to pattern the metal electrodes to form source metal and gate metal. Finally, a passivation layer 210 is deposited.

[0041] The drain structure fabrication process includes grinding and polishing the back side of the device, followed by sputtering back gold as the drain metal, ultimately yielding a vertically double-diffused metal-oxide-semiconductor field-effect transistor. The structure fabricated using this S105 process can be referenced. Figure 9 and Figure 10 , Figure 9 This is a schematic diagram of a structure for removing the transition layer and ion barrier protective layer provided in an embodiment of this application. Figure 10 This is a schematic diagram of a metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application. In this embodiment, the oxide layer 302 can be removed and the gate oxide layer 203 can be re-fabricated while removing the transition layer 401 and the ion barrier layer 501.

[0042] In one feasible embodiment, to avoid excessively high annealing temperatures exacerbating defects in the gate oxide layer 203, the above-described preparation of the source and drain structures may include the following steps, which can be referred to in detail. Figure 11 , Figure 11 This is a schematic flowchart of a method for fabricating a source structure and a drain structure provided in an embodiment of this application.

[0043] S1101: First type of doped ions are implanted into a first predetermined region on the side of the epitaxial layer toward the gate oxide layer to form a well region; S1102: The well region is annealed once using the first annealing temperature; the first annealing temperature is not higher than the preparation temperature of the thickened oxide layer; S1103: The well region is annealed a second time using the second annealing temperature; the first annealing temperature is lower than the second annealing temperature. S1104: A first type of doped ion is injected into a second preset region on the side of the epitaxial layer toward the gate oxide layer to form a first heavily doped region; the second preset region is located within the first preset region. S1105: A second type of dopant ions are implanted into a third preset region on the side of the epitaxial layer toward the gate oxide layer to form a second heavily doped region; the third preset region is located within the first preset region and is located beside the second preset region along the extension direction of the epitaxial layer surface.

[0044] In the embodiments of this application, the structure obtained after the above S1101 preparation can be referred to Figure 12 and Figure 13 , Figure 12 This is a schematic diagram of a structure in which a first photoresist is prepared on the surface of a polycrystalline layer, according to an embodiment of this application. Figure 13 This is a schematic diagram of a well implantation structure formed based on the implantation of a first photoresist according to an embodiment of this application. The first photoresist 1201 is used to perform ion implantation on a designated area to form a well implantation structure 1301. The structure prepared after the above step S1103 can be referred to... Figure 14 , Figure 14 This is a schematic diagram of a structure for completing the preparation of the trap region provided in an embodiment of this application.

[0045] The first type of doped ion can be phosphorus ions, the well region can be an N-well region, the first preset region can be a preset formation region of the N-well region of the device, and the thickened oxide layer 801 is a local thick oxide layer of LOCOS. In this embodiment, phosphorus ions are implanted into the first preset region on the side of the epitaxial layer 202 of the P-type silicon-based epitaxial wafer that is close to the silicon dioxide layer to form an N-well region. During the implantation process, a first photoresist 1201 can be used to block the process. The N-well region is annealed once using a first annealing temperature, which is not higher than the preparation temperature of the thickened oxide layer 801. The annealing atmosphere is nitrogen, which is used to repair implantation damage and defects in various interfaces and materials. Then, the N-well region is annealed a second time using a second annealing temperature, which is higher than the first annealing temperature, to activate the phosphorus ions in the N-well region, control the diffusion size of the phosphorus ions, and finally make the N-well form the target size.

[0046] In the embodiments of this application, the preparation of the first heavily doped region can be referred to... Figure 15 , Figure 15 This is a schematic diagram of a structure for fabricating a first heavily doped region based on a second photoresist, provided in an embodiment of this application. The first heavily doped region 1502 is formed by doping the second photoresist 1501 with first-type dopant ions.

[0047] The second type of dopant ion can be boron ions. The second heavily doped region 1504 is an N-type heavily doped region. The third preset region is located within the first preset region, and the implantation window is smaller than that of the first preset region. Boron ions are implanted into the third preset region to form the second heavily doped region 1504. During the implantation process, a third photoresist 1503 can be used as a barrier. After implantation, the third photoresist 1503 is removed to form a good ohmic contact with the source metal and reduce the contact resistance. For details of this step, please refer to [reference needed]. Figure 16 , Figure 16 This is a schematic diagram of a structure for fabricating a second doped region based on a third photoresist, provided in an embodiment of this application.

[0048] In this embodiment, the stepwise annealing process for the well region avoids damage to the thickened oxide layer 801 caused by high temperatures, reducing the risk of gate leakage. In this embodiment, during the re-filling of the well region 205, photoresist can also be used to block the polycrystalline layer 204. In this embodiment, after completing step S1103, the re-filling of the well region 205 can be performed by setting a second photoresist 1501 on the surface of the polycrystalline layer 204 to achieve re-filling of a designated area.

[0049] In one feasible embodiment, in order to avoid the electric field and morphology at the thickened oxide layer 801 affecting the first preset region and reduce the risk of gate leakage, the distance between the above-mentioned well region and the thickened oxide layer 801 can be set to be greater than the first preset distance. The first preset distance is the sum of the influence distance of the thickened oxide layer 801 and the outward expansion distance of the well region.

[0050] In this embodiment, the first preset region can be set as the preset formation region of the N-well region, the thickened oxide layer 801 is the thickened oxide layer 801 of the LOCOS local area, and the first preset distance is the sum of the maximum influence distance of the electric field and morphology around the thickened oxide layer 801 and the push-out distance of the well region, so as to avoid the well region and the thickened oxide layer 801 from affecting each other and causing leakage at the thickened oxide layer 801.

[0051] In this embodiment, the first preset distance can be specifically set to 0.5 to 1 micrometer. The distance between the first preset region and the thickened oxide layer 801 needs to ensure that after the N-well region is pushed together, there is still a reasonable distance between the edge of the N-well region and the edge of the thickened oxide layer 801. This effectively avoids the influence of the electric field and morphology around the thickened oxide layer 801, prevents defects in the bird's beak region at the edge of LOCOS from connecting with the N-well and the channel, reduces the risk of gate leakage, and prevents electric field distortion near LOCOS from affecting the electrical performance of the N-well region and the channel, ensuring the stability of the device threshold voltage and improving device reliability.

[0052] In one feasible embodiment, in order to eliminate the influence of the first type of doped ion implantation on the gate oxide layer 203 and improve the efficiency of subsequent second type of doped ion implantation, after the first type of doped ion supplementation is performed in a second predetermined region on the side of the epitaxial layer closer to the gate oxide layer to form a first heavily doped region, and before the second type of doped ions are implanted in a third predetermined region on the side of the epitaxial layer closer to the gate oxide layer to form a second heavily doped region, the above method may further include: Remove the gate oxide layer 203 in the uncovered area of ​​the polycrystalline layer 204 and grow an oxide layer as a cushion oxide layer.

[0053] In this embodiment, after first-type doped ions are implanted into a second predetermined region on the side of the epitaxial layer 202 adjacent to the gate oxide layer 203 to form a first heavily doped region 1502, and before second-type doped ions are implanted into a third predetermined region on the side of the epitaxial layer 202 adjacent to the gate oxide layer 203 to form a second heavily doped region 1504, the process may further include removing the gate oxide layer 203 in the uncovered area of ​​the polycrystalline layer 204 and regrowing a portion of the oxide layer. Specifically, a wet etching process can be used to remove the gate oxide layer 203 in the corresponding area on the surface of the current epitaxial layer 202. To ensure complete removal of damage and impurity residues to the gate oxide layer 203 generated during annealing and pre-implantation, a thermal oxidation process can be used to regrow a portion of the oxide layer after etching. This step effectively eliminates surface damage and impurity contamination of the gate oxide layer 203 introduced during the two annealing and implantation processes in the well region 205, providing a clean and flat interface for ion implantation in the subsequent second doped region 206. This prevents damage from continuing into the implantation process in the second doped region 206 and causing interface defects, thereby reducing gate leakage current, ensuring the electrical performance stability of the source structure, and improving the overall reliability of the device.

[0054] In one feasible embodiment, to avoid damage to the polycrystalline layer 204 during the ion implantation process and to reduce gate defects, the above-described preparation of the gate structure may include: On the side of the gate oxide layer 203 and the thickened oxide layer 801 facing away from the epitaxial layer 202, a polysilicon layer is prepared corresponding to the third preset region as a gate structure; the fourth preset region is all the regions on the surface of the epitaxial layer 202 except for the first preset region. The process of implanting first-type doped ions into a first predetermined region on the side of the epitaxial layer 202 toward the gate oxide layer 203 to form a well region may include the following steps.

[0055] A first photoresist 1201 is prepared on the side of the epitaxial layer 202 that is close to the gate oxide layer 203, and the opening of the first photoresist 1201 corresponds to the first preset region. A first type of doped ions are injected into a first preset region based on the first photoresist 1201 to form a trap region; The first photoresist 1201 covers the polycrystalline layer 204 and extends beyond the polycrystalline layer 204 by a second preset distance; the second preset distance is the minimum distance at which the first photoresist 1201 blocks the implantation of first-type doped ions into the polycrystalline silicon.

[0056] In this embodiment, the steps for preparing the trap region 205 can be referred to the above. Figures 12 to 14In this embodiment, the gate oxide layer 203 can be set as a silicon dioxide layer, the thickened oxide layer 801 is a local thickened oxide layer 801 of LOCOS, the first type of doped ion is phosphorus ion, the well region is an N-well, the first preset region is the preset N-well formation region, the fourth preset region is all regions on the surface of the epitaxial layer in the P-type silicon-based epitaxial wafer except for the first preset region, and the second preset distance is the minimum distance of the first photoresist 1201 to block phosphorus ion implantation into the polysilicon layer.

[0057] In this embodiment, the gate structure can be fabricated using chemical vapor deposition (CVD). A polysilicon layer is fabricated on the side of the silicon dioxide layer and the thickened oxide layer 801 facing away from the epitaxial layer 202, corresponding to the fourth preset region, to serve as the gate structure. After deposition, polysilicon implantation is performed to reduce gate resistance, followed by polysilicon etching. After etching, the polysilicon layer in the fourth preset region is retained as the gate structure. Then, phosphorus ions are implanted into the first preset region on the side of the epitaxial layer 202 facing the silicon dioxide layer to form a well region. The minimum distance to block phosphorus ion implantation into the polysilicon layer can be set to 0.2 to 0.5 micrometers. Therefore, the first photoresist 1201 extends 0.2 to 0.5 micrometers beyond the edge of the polysilicon layer. This first photoresist 1201 can effectively block phosphorus ion implantation into the polysilicon layer, avoiding ion implantation damage to the gate structure, preventing gate leakage, ensuring the accuracy of well region implantation, ensuring electrical isolation between the gate structure and the well region, and improving the overall reliability of the device.

[0058] In one feasible embodiment, in order to remove defects on the oxide layer surface, after removing the transition layer and ion barrier layer, and before fabricating the gate structure, source structure, and drain structure to obtain a vertically double-diffused metal-oxide-semiconductor field-effect transistor, the above method may further include: Continue etching to remove the oxide layer and grow and fabricate the gate oxide layer. In this embodiment, the process of removing the oxide layer 302 and re-fabricating the gate oxide layer 203 described above can be referred to... Figure 17 and Figure 18 , Figure 17 This is a schematic diagram of a structure for removing an oxide layer provided in an embodiment of this application; Figure 18This is a schematic diagram of the structure after re-fabrication of the gate oxide layer according to an embodiment of this application. Both the gate oxide layer 203 and the oxide layer 302 can be set as silicon dioxide layers. Before fabricating the gate structure, source structure, and drain structure during the removal of the transition layer 401 and the ion barrier layer 501, the silicon dioxide layer can be further etched to remove it and then regrown. Specifically, a dry over-etching process can be used to further etch and remove the silicon dioxide layer. The etching gas can be a mixture of oxygen and argon, and the etching amount needs to be controlled to ensure that all silicon dioxide layers are removed. This step can thoroughly remove defects and impurities at the interface of the transition layer 401, the ion barrier layer 501, and the gate oxide layer 203, as well as surface damage to the gate oxide layer 203 generated in the previous process, avoiding the risk of gate leakage, ensuring the electrical performance stability of the subsequent gate structure, and improving the overall reliability of the device.

[0059] The metal-oxide-semiconductor field-effect transistor fabrication method provided in this application involves in-situ dielectric doping of one side of the oxide layer 302 facing away from the epitaxial wafer 301 using plasma-based methods to obtain a transition layer 401. The lattice structure of the components within the transition layer 401 is intermediate between the components within the oxide layer 302 and the ion barrier layer 501. This improves the stability of the lattice change during the transition from the oxide layer 302 to the ion barrier layer 501, reduces the occurrence of lattice breakage, and lowers the stress between the two layers. Furthermore, the transition layer 401 prepared by in-situ dielectric doping can achieve a gapless interface between the prepared transition layer 401 and the oxide layer 302, improving the density and implantation resistance of the transition layer 401. It can also block impurity ions, preventing impurity ions from entering the oxide layer 302 and causing leakage after the thickened oxide layer 801 is prepared, thereby improving product performance.

[0060] Furthermore, in this embodiment, the ion blocking protective layer 501 is configured as a gradient ion blocking protective layer 501 with an increasing content of ion blocking components along the direction opposite to the transition layer 401, thereby improving the impedance effect against impurity ions. By configuring the epitaxial wafer 301 as a silicon-based epitaxial wafer 301, the gate oxide layer 203 as a silicon dioxide layer, the transition layer 401 as a silicon oxynitride layer, and the ion blocking protective layer 501 as a silicon nitride layer, interface defects are reduced, the impediment blocking ability is improved, and gate leakage is suppressed. The stepwise annealing process of the trap area avoids damage to the thickened oxide layer 801 caused by high temperature, reducing the risk of gate leakage. By setting the distance between the first preset region and the thickened oxide layer 801 to be greater than the first preset distance, gate leakage is avoided. The electric field and morphology at the thickened oxide layer 801 affect the first preset region, thereby reducing the risk of gate leakage. After the second annealing of the well region, before the formation of the second doped region, the gate oxide layer 203 is removed and the gate oxide layer 203 is regrown. This can eliminate the influence of the first type of doped ion implantation on the gate oxide layer 203 and improve the efficiency of subsequent second type of doped ion implantation. The first photoresist 1201 is used to block phosphorus ion implantation into the polysilicon layer, avoiding damage to the gate structure by ion implantation and preventing gate leakage. By continuing to etch and remove the oxide layer 302 during the removal of the transition layer 401 and the ion blocking protective layer 501, and regrowing the gate oxide layer 203, defects on the surface of the gate oxide layer 203 are removed.

[0061] To make the metal-oxide-semiconductor field-effect transistor fabrication method mentioned above in the embodiments of this application easier to understand, this application also provides a specific application scenario embodiment, which specifically includes the following steps, which can be referred to. Figure 19 , Figure 19 This is a flowchart illustrating a method for fabricating a metal-oxide-semiconductor field-effect transistor provided in an application scenario embodiment of this application.

[0062] S1901: Obtain a silicon-based epitaxial wafer, prepare a silicon dioxide layer as a gate oxide layer on one side of the epitaxial layer, and perform in-situ nitrogen plasma dielectric doping on the gate oxide layer to form a silicon oxynitride transition layer. S1902: Multiple sub-protective layers are sequentially prepared on the surface of the silicon oxynitride transition layer, such that the content of the ion blocking component in the adjacent sub-protective layers facing away from the transition layer is higher than that in the layers close to the transition layer, thus forming a gradient silicon oxynitride ion blocking protective layer. S1903: Etching removes the silicon oxynitride transition layer and the gradient silicon nitride ion barrier protective layer in the area to be thickened, and prepares a thickened oxide layer in this area; S1904: Remove the remaining silicon oxynitride transition layer and gradient silicon nitride ion barrier layer, and continue etching. Remove Silicon dioxide layer, used to grow gate oxide layer; It should be noted that the regrowth gate oxide layer can also be a silicon dioxide layer.

[0063] S1905: On the surface of the gate oxide layer and the thickened oxide layer, a polysilicon layer is prepared as a gate structure in the region other than the first preset region. S1906: A first photoresist is prepared on the side of the epitaxial layer facing the gate oxide layer. Doped ions are injected into a first preset region based on the first photoresist to form a well region. The well region is then subjected to secondary annealing. It should be noted that the first photoresist covers the polysilicon layer and extends beyond the polysilicon layer by a second preset distance. This second preset distance is the minimum distance at which the first photoresist blocks the implantation of first-type doped ions into the polysilicon. Furthermore, during the secondary annealing of the well region, the first annealing temperature is no higher than the oxide layer thickening preparation temperature, while the second annealing temperature is higher than the first annealing temperature. Before annealing, the first photoresist needs to be removed.

[0064] S1907: A first type of doped ion is injected into a second preset region on the side of the epitaxial layer toward the gate oxide layer to form a first heavily doped region; the second preset region is located within the first preset region. S1908: Remove the remaining gate oxide layer, regenerate the gate oxide layer, and inject second type dopant ions into the third preset region within the first preset region to form a second heavily doped region; S1909: The source and drain structures are fabricated and combined with the gate structure and well region to obtain a vertically double-diffused metal-oxide-semiconductor field-effect transistor.

[0065] To further verify the effect of the proposed structure and process method on gate leakage current suppression, the electric field distribution of key structures in the LOCOS edge region can be compared and analyzed using the TCAD (Technology Computer-Aided Design) simulation tool. Since the simulation tool cannot directly define silicon oxynitride (SiO2) material, OxyN (SiO2) material is used as a substitute in this embodiment. The gradient silicon nitride structure cannot be simulated in the simulation tool either; therefore, equivalent simulation is performed by depositing a single layer of Si3N4 (SiO2). Simultaneously, during the simulation, process conditions were set such as photoresist protection of the polycrystalline material during well implantation and PSD implantation, staged annealing of the well, and changing PSD implantation from BF2 (boron difluoride) ions to B (boron) ions.

[0066] Simulation results are as follows Figures 20 to 24 As shown, it can be seen that the electric field strength of the structure in this application decreases significantly at the LOCOS corner. Figure 20 This is a simulation diagram of the electric field morphology near a thickened oxide layer in the prior art; Figure 21This is a simulation diagram of the electric field morphology near a thickened oxide layer provided in an embodiment of this application; Figure 22 This is a simulation diagram comparing the electric field strength near a thickened oxide layer with that provided in the embodiments of this application; Figure 23 This is a cell simulation diagram of a process with a thickened oxide layer in the prior art; Figure 24 This is a cell simulation diagram of a fabricated oxide layer provided in an embodiment of this application. Wherein, by... Figure 22 It can be determined that the structure of this application exhibits a significant reduction in electric field intensity in the peak electric field region, indicating that it effectively mitigates the electric field concentration effect at the LOCOS edge, thereby reducing the risk of gate leakage. Figure 22 The solid line represents the electric field distribution near the thickened oxide layer after it has been prepared using existing processes. Figure 22 The dashed line represents the electric field distribution near the thickened oxide layer after the thickened oxide layer is prepared using the process described in this application. In the overall comparison, the dashed line is significantly lower than the solid line.

[0067] Figure 10 This is a schematic diagram of the structure of a metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application. For example... Figure 10 As shown, the structure may include: Epitaxial wafer 301 includes a substrate 201 and an epitaxial layer 202 grown on one side surface of the substrate 201; Gate oxide layer 203 is disposed on the side surface of epitaxial layer 202 facing away from substrate 201; The thickened oxide layer 801 is disposed in the region of the gate oxide layer 203 to be thickened, based on the transition layer and the ion barrier layer. The transition layer is disposed on the side surface of the oxide layer facing away from the epitaxial layer 202, and the transition layer is obtained by in-situ dielectric doping of the side surface of the gate oxide layer 203 facing away from the epitaxial wafer 301 by plasma. The lattice structure of the composition in the transition layer is between the lattice structures of the composition in the gate oxide layer 203 and the composition in the ion barrier layer. The ion barrier layer is disposed on the side surface of the transition layer facing away from the epitaxial layer 202. Before the gate oxide layer is prepared, the oxide layer is disposed on the side surface of the epitaxial layer facing away from the substrate. Before the gate oxide layer 203 is prepared, the oxide layer is disposed on the side surface of the epitaxial layer 202 facing away from the substrate 201. The gate structure is disposed on the side surface of the gate oxide layer 203 and the thickened oxide layer 801 facing away from the epitaxial layer 202 after the transition layer and ion blocking protective layer are removed. The transistor comprises a source structure and a drain structure. The source structure is located in the corresponding region of the epitaxial layer 202 and cooperates with the gate structure and the gate oxide layer 203 to form a vertically double-diffused metal-oxide-semiconductor field-effect transistor. The source structure is located on the transistor surface and is connected to the NSD and PSD.

[0068] In this embodiment, the metal-oxide-semiconductor field-effect transistor (MOSFET) can specifically be configured as a P-channel vertical double-diffused MOSFET. The epitaxial wafer 301 can specifically include a P-type silicon substrate and a P-type epitaxial layer grown on the upper surface of the P-type silicon substrate. The gate oxide layer 203 can specifically be configured as a silicon dioxide layer, tightly covering the upper surface of the P-type epitaxial layer, i.e., the surface facing away from the P-type silicon substrate, forming a good interface bond with the P-type epitaxial layer. The transition layer can specifically be configured as a silicon oxynitride layer, tightly covering the upper surface of the silicon dioxide layer, i.e., the surface facing away from the P-type epitaxial layer. The transition layer is obtained by in-situ dielectric doping of the upper surface of the silicon dioxide layer using nitrogen plasma. Its internal lattice structure is between the lattice structure of the silicon dioxide layer and the lattice structure of the ion barrier layer, achieving lattice matching between the silicon dioxide layer and the ion barrier layer, and seamlessly bonding the transition layer to the silicon dioxide layer. In this embodiment, the gate structure includes a polycrystalline layer 204, and an isolation dielectric layer 207 is disposed outside the polycrystalline layer 204. Figure 10 As shown, the front metal 208, the back metal 209, and the passivation layer 210 are all as follows: Figure 10 The setup is shown. Source metal connection well region 205, first heavily doped region, and second heavily doped region 206.

[0069] In this embodiment, the ion barrier layer can be specifically configured as a silicon nitride layer, tightly covering the upper surface of the silicon oxynitride transition layer, i.e., the side surface facing away from the P-type epitaxial layer, and seamlessly bonded to the silicon oxynitride transition layer. The thickened oxide layer 801 is a localized thick oxide layer in LOCOS, disposed in the area of ​​the silicon dioxide layer to be thickened, or it can be configured as a thickened silicon dioxide layer, with its edges smoothly connected to the remaining silicon dioxide layer; the gate structure is a polysilicon gate, tightly covering the upper surface of the gate oxide layer and the upper surface of the thickened oxide layer 801, both disposed on the side surface facing away from the P-type epitaxial layer. The gate structure forms good interface contact with both the silicon dioxide layer and the thickened oxide layer 801. In this embodiment, the transition layer and the ion barrier layer are removed after the thickened oxide layer 801 is prepared. The source metal connects the NSD and PSD. The NSD is the N-type source-drain heavily doped region. The N-well is located in the first predetermined region on the side of the P-type epitaxial layer facing the silicon dioxide layer. The bottom of the N-well extends into the interior of the P-type epitaxial layer, and the top contacts the lower surface of the silicon dioxide layer. There is a gap between the N-well and the thickened oxide layer 801, and this gap is greater than the first predetermined distance. The PSD is located in the third predetermined region inside the N-well. The top of the PSD contacts the lower surface of the silicon dioxide layer, and the bottom extends into the interior of the N-well and is seamlessly connected to the N-well. The drain structure includes a back gold electrode located on the lower surface of the P-type silicon substrate. The back gold electrode can be set as a titanium-nickel-silver metal layer as the drain lead-out electrode. Both the PSD and NSD are connected to the source metal electrode, the gate structure is connected to the gate metal electrode, and the back gold electrode of the drain structure serves as the drain lead-out terminal. All structures work together to form a complete vertical double-diffused metal-oxide-semiconductor field-effect transistor.

[0070] In one feasible embodiment, in order to improve the impedance effect to impurity ions, the ion blocking protective layer may include multiple sub-protective layers. In two adjacent sub-protective layers, the content of the intralayer ion-blocking component facing away from the transition layer is greater than the content of the intralayer ion-blocking component facing towards the transition layer, forming a gradient ion-blocking protective layer.

[0071] In this embodiment, the ion blocking protective layer can be configured as a gradient silicon nitride layer, and may include a first sub-protective layer, a second sub-protective layer, and a third sub-protective layer stacked sequentially. The first sub-protective layer is tightly bonded to the transition layer, the second sub-protective layer is disposed on the side of the first sub-protective layer facing away from the transition layer, and the third sub-protective layer is disposed on the side of the second sub-protective layer facing away from the transition layer. The nitrogen ion content in the sub-protective layer facing away from the transition layer is greater than the nitrogen ion content in the sub-protective layer near the transition layer. It can be configured as a gradient ion blocking protective layer with an increasing ion blocking component content along the direction away from the transition layer, so as to improve the blocking effect on impurity ions while reducing the stress between the gate oxide layer 203 and the ion blocking protective layer, thereby reducing the gate leakage problem.

[0072] Using the metal-oxide-semiconductor field-effect transistor provided in this application embodiment, an in-situ dielectric doping treatment is performed on the side surface of the gate oxide layer 203 facing away from the epitaxial wafer using plasma to obtain a transition layer. The lattice structure of the components in this transition layer is between the components in the gate oxide layer 203 and the components in the ion barrier layer, thereby improving the stability of the lattice change during the transition of the gate oxide layer 203 to the ion barrier layer, reducing the problem of lattice breakage, and reducing the stress between the two. In addition, the transition layer prepared by in-situ dielectric doping can achieve a gapless interface between the prepared transition layer and the gate oxide layer 203, improving the density and implantation resistance of the transition layer, blocking impurity ions, and preventing impurity ions from entering the gate oxide layer 203 and causing leakage after the thickened oxide layer 801 is prepared, thus improving product performance.

[0073] Furthermore, in this embodiment, the ion barrier protection layer includes multiple sub-protective layers, and in two adjacent sub-protective layers, the content of the ion barrier component in the layer facing away from the transition layer is greater than the content of the ion barrier component in the layer facing towards the transition layer, thus forming a gradient ion barrier protection layer, which improves the impedance effect to impurity ions and reduces the stress of the device.

[0074] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or structures based on a series of steps. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0075] The foregoing flowcharts and / or block diagrams of methods and structures according to embodiments of the present disclosure have described various aspects of the present disclosure. It should be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by a computer issuing program instructions to a corresponding device. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by dedicated hardware performing a specified function or action, or by a combination of dedicated hardware and computer instructions.

[0076] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific structures described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for fabricating a metal-oxide-semiconductor field-effect transistor, characterized in that, include: Obtain an epitaxial wafer, and prepare an oxide layer on one side surface of the epitaxial layer in the epitaxial wafer; A transition layer is obtained by in-situ dielectric doping of the oxide layer on the side facing away from the epitaxial wafer using plasma; the lattice structure of the components in the transition layer is between that of the oxide layer and that of the ion barrier layer. An ion-barrier protective layer is prepared on the surface of the transition layer facing away from the epitaxial wafer; Etching removes the transition layer and ion barrier protective layer corresponding to the region to be thickened in the oxide layer, and a thickened oxide layer is prepared in the region to be thickened. The transition layer and the ion barrier layer are removed, and a gate structure, a source structure, and a drain structure are fabricated to obtain a vertically double-diffused metal-oxide-semiconductor field-effect transistor; the gate structure is disposed on the side surface of the thickened oxide layer facing away from the epitaxial layer after the transition layer and the ion barrier layer are removed.

2. The method for fabricating a metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The step of preparing an ion-barrier protective layer on the side of the transition layer facing away from the epitaxial wafer includes: On the side of the transition layer facing away from the epitaxial wafer, a plurality of sub-protective layers are sequentially prepared, and the content of the intralayer ion blocking component facing away from the transition layer in two adjacent sub-protective layers is greater than the content of the intralayer ion blocking component facing towards the transition layer, thus forming a gradient ion blocking protective layer.

3. The method for fabricating a metal-oxide-semiconductor field-effect transistor according to claim 2, characterized in that, The acquisition of the epitaxial wafer includes: Obtain silicon-based epitaxial wafers; The oxide layer is a silicon dioxide layer, the transition layer is a silicon oxynitride layer, and the ion barrier layer is a silicon nitride layer.

4. The method for fabricating a metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, After removing the transition layer and the ion barrier layer, and before fabricating the gate structure, source structure, and drain structure to obtain a vertically double-diffused metal-oxide-semiconductor field-effect transistor, the method further includes: Continue etching to remove the oxide layer and grow a gate oxide layer.

5. The method for fabricating a metal-oxide-semiconductor field-effect transistor according to claim 4, characterized in that, The fabrication of the source and drain structures includes: A first type of dopant ions are implanted into a first predetermined region on the side of the epitaxial layer adjacent to the gate oxide layer to form a trap region; The well region is annealed once using a first annealing temperature; the first annealing temperature is not higher than the preparation temperature of the thickened oxide layer. The well region is subjected to a second annealing at a second annealing temperature; the first annealing temperature is lower than the second annealing temperature. A first type of doped ion is injected into a second predetermined region on the side of the epitaxial layer toward the gate oxide layer to form a first heavily doped region; the second predetermined region is located within the first predetermined region. A second type of dopant ions are implanted into a third predetermined region on the side of the epitaxial layer that is close to the gate oxide layer to form a second heavily doped region; the third predetermined region is located within the first predetermined region and is located beside the second predetermined region along the extension direction of the epitaxial layer surface.

6. The method for fabricating a metal-oxide-semiconductor field-effect transistor according to claim 5, characterized in that, The distance between the well region and the thickened oxide layer is greater than a first preset distance; The first preset distance is the sum of the influence distance of the thickened oxide layer and the outward expansion distance of the well region push junction.

7. The method for fabricating a metal-oxide-semiconductor field-effect transistor according to claim 5, characterized in that, The fabrication of the gate structure includes: On the side of the gate oxide layer and the thickened oxide layer facing away from the epitaxial layer, a polycrystalline layer is prepared corresponding to the fourth preset region as the gate structure; the fourth preset region is the entire area of ​​the epitaxial layer surface excluding the first preset region. The first predetermined region on the side of the epitaxial layer adjacent to the gate oxide layer, wherein a first type of doped ions are implanted to form a well region, includes: A first photoresist is prepared on the side of the epitaxial layer facing the gate oxide layer, and the opening of the first photoresist corresponds to the first preset region; The first type of doped ions are injected into the first preset region based on the first photoresist to form the trap region; The first photoresist covers the polycrystalline layer, and its edge extends beyond the polycrystalline layer by a second preset distance; the second preset distance is the minimum distance at which the first photoresist blocks the first type of doped ions from being implanted into the polycrystalline layer.

8. The method for fabricating a metal-oxide-semiconductor field-effect transistor according to claim 7, characterized in that, After implanting first-type dopant ions in a second predetermined region on the side of the epitaxial layer toward the gate oxide layer to form a first heavily doped region, and before implanting second-type dopant ions in a third predetermined region on the side of the epitaxial layer toward the gate oxide layer to form a second heavily doped region, the method further includes: Remove the gate oxide layer in the uncovered area of ​​the polycrystalline layer and grow an oxide layer as a cushion oxide layer.

9. A metal-oxide-semiconductor field-effect transistor, characterized in that, include: An epitaxial wafer includes a substrate and an epitaxial layer grown on one side surface of the substrate; A gate oxide layer is disposed on the side surface of the epitaxial layer facing away from the substrate; A thickened oxide layer is formed in the region of the gate oxide layer to be thickened, based on a transition layer and an ion-barrier protective layer. The transition layer is disposed on the side surface of the oxide layer facing away from the epitaxial layer, and is obtained by in-situ dielectric doping of the side surface of the oxide layer facing away from the epitaxial layer using plasma. The lattice structure of the components in the transition layer is intermediate between the lattice structures of the components in the oxide layer and the components in the ion-barrier protective layer. The ion-barrier protective layer is disposed on the side surface of the transition layer facing away from the epitaxial layer. Before the gate oxide layer is fabricated, the oxide layer is disposed on the side surface of the epitaxial layer facing away from the substrate. A gate structure is disposed on the side surface of the gate oxide layer and the thickened oxide layer facing away from the epitaxial layer after the transition layer and ion blocking protective layer are removed; The source structure and the drain structure are respectively disposed in the corresponding regions of the epitaxial layer, and cooperate with the gate structure and the gate oxide layer to form a vertical double-diffused metal-oxide-semiconductor field-effect transistor.

10. The metal-oxide-semiconductor field-effect transistor according to claim 9, characterized in that, The ion-blocking protective layer includes multiple sub-protective layers; In two adjacent sub-protective layers, the content of the intralayer ion-blocking component facing away from the transition layer is greater than the content of the intralayer ion-blocking component facing towards the transition layer, thus forming a gradient ion-blocking protective layer.

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