A two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor
By employing a vertically stacked structure of heavily doped p-type silicon substrate, HZO gate dielectric layer, and few-layer tungsten selenide nanosheets in a two-dimensional transistor, a multifunctional integration of high-performance bipolar field-effect switching, non-volatile storage, and neuromorphic synapse bionics was achieved, solving the problems of single function and insufficient gate dielectric material in existing transistors, and adapting to multiple application scenarios of high-density chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU UNIV OF SCI & TECH
- Filing Date
- 2026-03-13
- Publication Date
- 2026-06-09
Smart Images
Figure CN122180102A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of multifunctional transistor fabrication, specifically a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor. Background Technology
[0002] The post-Moore's Law era has placed higher demands on the high density, low power consumption, and multifunctional heterogeneous integration of chips. However, as Moore's Law reaches its physical limits, traditional silicon-based field-effect transistors (FETs) are no longer able to meet these development requirements due to bottlenecks such as short-channel effects, gate control capabilities, power consumption, and limited functionality. Two-dimensional transition metal chalcogenides (TMDs), with their atomic-level thickness, absence of dangling bonds, and excellent amphipathic carrier transport properties, have become core candidate materials for breaking through the physical limits of traditional silicon-based devices. Among them, tungsten selenide (WSe2) is the core channel material for two-dimensional multifunctional transistors due to its intrinsic bipolar band structure, high carrier concentration, and good environmental stability.
[0003] Currently, existing WSe2-based two-dimensional transistors and related devices still have the following technical defects and industry pain points that urgently need to be addressed: (1) Single device function and difficulty in heterogeneous integration; Most existing WSe2-based transistors can only realize basic field-effect switching functions and cannot simultaneously integrate the three core functions of logic switching, non-volatile storage, and neuromorphic synaptic bionics within a single device architecture. To achieve multi-functional heterogeneous integration of the chip system, a large number of single-function devices need to be stacked, resulting in large chip area, high design complexity, increased power consumption, and poor process compatibility, which cannot meet the development needs of high-density integration; (2) Insufficient gate dielectric material design and limited overall device performance: Most existing two-dimensional transistors use traditional SiO2 or single HfO2 as gate dielectrics. Among them, SiO2 has a low dielectric constant and weak gate control capability, which cannot suppress short-channel effects. The device has poor switching ratio and power consumption performance. Moreover, the single HfO2 thin film ferroelectric / resistive switching characteristics are unstable and are prone to performance degradation after long-term operation, resulting in poor resistive state retention capability and low cycle life. It cannot meet the dual requirements of high-performance switching and stable storage. (3) Insufficient electrical performance and poor adaptability to multiple scenarios: Most existing WSe2-based transistors can only achieve unipolar transport, have weak bipolar control capability, and the switching ratio is generally lower than 10. 5 Furthermore, the channel-electrode contact resistance is high, the ohmic contact characteristics are poor, and the current density is low, making it unable to simultaneously meet the electrical requirements of multiple scenarios such as complementary logic circuits, non-volatile storage, and neuromorphic computing. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention addresses the following core technical problems in order of importance: Existing two-dimensional WSe2 transistors have limited functionality and cannot simultaneously achieve the three core functions of high-performance field-effect switching, non-volatile storage, and neuromorphic synaptic bionics within a single, minimally sized device architecture. Multifunctional heterogeneous integration requires stacking multiple devices, resulting in low chip integration density, high power consumption, and poor process compatibility. Existing two-dimensional transistor gate dielectric materials and structural designs have inherent defects. Traditional SiO2 gate dielectrics have weak controllability, and single HfO2 gate dielectrics exhibit unstable ferroelectric / resistive switching characteristics and poor compositional uniformity, failing to simultaneously meet the requirements of high on / off ratio, low power consumption, and stable resistive switching characteristics, leading to insufficient device electrical performance and storage reliability. Existing WSe2-based transistors have poor bipolar transport characteristics, mostly achieving only unipolar conduction, resulting in low on / off ratios, poor ohmic contact characteristics, and low current density, making them unsuitable for the diverse application requirements of logic circuits, storage, and neuromorphic computing.
[0005] This invention is implemented as follows:
[0006] A two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor is disclosed. The transistor is a vertically stacked semiconductor device structure, consisting of a substrate layer, an oxide layer, a tungsten selenide nanosheet channel layer, and an electrode layer, from bottom to top. The materials, structural parameters, spatial relationships, and connections of each layer are as follows: The substrate layer is heavily doped. p Type-100 silicon substrate, specifically 100-oriented. p ++Doped low-resistivity single-crystal silicon substrate, heavily doped without native surface oxide layer p The device consists of a silicon wafer serving as the mechanical support substrate and back gate; an oxide layer made of hafnium zirconium oxide (HZO) material, deposited entirely on the upper surface of the substrate; a tungsten selenide nanosheet channel layer made of few-layer tungsten selenide nanosheets, laid flat on the upper surface of the oxide layer, serving as the semiconductor channel layer; and an electrode layer comprising a source electrode and a drain electrode, both made of gold. The source and drain electrodes are fabricated at both ends of the tungsten selenide nanosheets, directly contacting them to form an electrical connection for electrical signal input and output.
[0007] Furthermore, the thickness of the oxide layer is controlled at 10–20 nm; the hafnium zirconium oxide layer is prepared by alternating deposition of HfO2 single deposition cycle and ZrO2 single deposition cycle in a 1:1 ratio, resulting in a uniform film composition.
[0008] Furthermore, the thickness of the tungsten selenide nanosheet channel layer is 3–8 nm.
[0009] Furthermore, the thickness of the electrode layer is 110 nm.
[0010] The present invention discloses a method for fabricating a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor, the specific steps of which are as follows:
[0011] Step 1: Heavy doping p Step 1: Preparation and pretreatment of silicon substrate; Step 2: Atomic layer deposition of hafnium zirconium oxide gate dielectric layer; Step 3: Mechanical exfoliation and site transfer of tungsten selenide nanosheets; Step 4: Preparation of source and drain electrodes and post-processing of device shaping.
[0012] Furthermore, in step 1, heavy doping is provided. p Type-100 silicon substrate, the substrate being 100-oriented p ++Doped low-resistivity single-crystal silicon wafer, without a native surface oxide layer, step 1 specifically involves:
[0013] First, the substrate is pre-treated by cleaning: the silicon wafer is cut into 1*1cm silicon wafers, and the silicon substrate is placed in distilled water, propanol solution and ethanol solution respectively for ultrasonic treatment for 2 minutes. The above cleaning process is repeated once. Finally, the silicon substrate is dried with dry nitrogen gas and set aside for use.
[0014] The substrate was then cleaned with a 4% HF / H2O solution to completely remove the oxide layer formed by self-oxidation on the surface. The substrate was then treated with a UV ozone cleaner for 1 minute to achieve complete hydroxylation of the substrate surface, providing good substrate conditions for subsequent film formation.
[0015] Furthermore, step 2 involves using atomic layer deposition (ALD) to prepare a hafnium zirconium oxide thin film layer on the surface of the pretreated silicon substrate. The specific process parameters and operations are as follows:
[0016] A four-channel ALD system was used to grow HZO thin films. The precursors for HfO2 were tetra(dimethylamino)hafnium (TDMA-Hf) and deionized water (H2O). A solid hafnium source was used to ensure the stability of the source during the growth process and to avoid the problems of poor thermal stability and easy decomposition of liquid tetra(dimethylamino)hafnium after long-term use.
[0017] The heating temperature of the hafnium precursor source is 90℃, and the heating temperature of the oxygen source (deionized water) is 50℃; the precursor of ZrO2 is tetra(diethylamino)zirconium (TDEA-Zr) and deionized water (H2O), the heating temperature of the zirconium precursor source is 90℃, and the heating temperature of the oxygen source (deionized water) is 50℃.
[0018] High-purity nitrogen was used as the carrier gas to maintain a high vacuum and pollution-free deposition atmosphere in the deposition chamber. Alternating atomic layer deposition was performed strictly according to a 1:1 ratio of HfO2 and ZrO2 single-deposition cycles to ensure the uniformity of the film composition. Furthermore, 50 cycles each of HfO2 and ZrO2 constituted 50 growth cycles of HZO layer, corresponding to a thickness of approximately 11 nm. By precisely controlling the total number of cycles in the aforementioned 1:1 alternating deposition, HZO films with a target thickness of 10–20 nm were prepared.
[0019] Furthermore, in step 3, tungsten selenide nanosheets are prepared on PDMS using a mechanical exfoliation method. Subsequently, the prepared tungsten selenide nanosheets are transferred to the upper surface of the hafnium zirconium oxide layer using a transfer platform. The specific operation process is as follows:
[0020] Tungsten selenide single crystals were adhered to the surface of the tape using adhesive tape, and the tungsten selenide material was peeled off onto the PDMS substrate by mechanical peeling. Transparent thin-layer tungsten selenide nanosheets were screened using an optical microscope, and few-layer tungsten selenide nanosheets with suitable size and thickness of 3-8 nm were selected for later use using computer-aided testing software.
[0021] The glass slide with PDMS is inverted and fixed, and the substrate with hafnium zirconium oxide grown is placed in the transfer station and fixed by vacuum adsorption. The lifting knob of the transfer device is adjusted to make the PDMS and the substrate accurately aligned and in contact. The substrate is heated at 125°C for 8 minutes, and then the lifting knob is adjusted to separate the PDMS from the substrate. The point transfer of tungsten selenide nanosheets on the surface of hafnium zirconium oxide layer is completed.
[0022] Gold electrodes were fabricated at both ends of the tungsten selenide nanosheets using photolithography and electron beam evaporation techniques to form the source and drain electrodes, respectively, ultimately resulting in a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor. The specific operation process is as follows:
[0023] Furthermore, step 4 specifically includes:
[0024] First, the sample is gently cleaned to remove surface dust and trace organic impurities, so as to avoid damaging the HZO functional layer and WSe2 channel.
[0025] Subsequently, photoresist was spin-coated onto the sample surface using standard photolithography. After pre-baking, mask alignment, exposure, and development, the source and drain electrodes were fabricated at both ends of the WSe2 channel. The photolithographically completed sample was then placed in a high-vacuum electron beam evaporation apparatus to deposit a gold electrode film with a thickness of 110 nm at room temperature.
[0026] After deposition, the photoresist and metal film in non-target areas are removed by a stripping process, leaving only the source and drain metal electrodes in the preset pattern area. Then, the sample is placed in a tube furnace at 350°C for annealing for 1 hour. After annealing, the sample is removed to obtain a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor with a complete structure that can be directly tested for electrical performance.
[0027] The two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor of the present invention adopts a vertical stacked structure with bottom gate and top contact, and is heavily doped. p The silicon substrate serves as both the bottom gate electrode and the gate dielectric layer. HZO thin films, deposited alternately in a 1:1 ratio of HfO2 and ZrO2 single-deposition cycles, form the gate dielectric layer. A few-layer WSe2 nanosheet forms the bipolar semiconductor channel layer, and a gold thin film serves as the source and drain electrodes. Leveraging the dielectric properties and interface charge trapping effect of the HZO gate dielectric, combined with the intrinsic bipolar carrier transport and photoelectric response characteristics of the WSe2 channel, the device achieves multifunctional integration of field-effect switching, non-volatile storage, and neuromorphic synaptic biomimetic within a single device architecture. The core working mechanism consists of three parts:
[0028] Working mechanism of field-effect transistor switching
[0029] This device is a typical bottom-gate field-effect transistor (FET). The gate voltage forms a vertical electric field at the WSe2 channel interface through the HZO gate dielectric layer, precisely controlling the carrier concentration and conductivity type within the channel to achieve switching functionality and bipolar transport. When a positive gate voltage is applied to the bottom gate, the electrostatic field induces a large number of electrons in the WSe2 channel, exhibiting n-type electron conductivity characteristics, and the source-drain current increases significantly with increasing positive gate voltage. When a negative gate voltage is applied to the bottom gate, the electrostatic field causes a large number of hole carriers to accumulate in the channel, and the device... p Hole conduction is dominant, and the source-drain current increases significantly with the increase of the absolute value of the negative gate voltage.
[0030] Furthermore, the device exhibits significant hysteresis, providing reliable data support for the measurement of its storage characteristics. n The shaped area exhibits a clockwise lag. pThe region exhibits counterclockwise hysteresis. During the reverse scan, when a positive gate voltage is applied, the ferroelectric polarization in HZO is upward along the applied electric field, causing electrons to be trapped at the WSe2 / HZO interface, while holes are induced into the WSe2 channel. This is the opposite of the electron doping effect of the electrostatic field. Under a large negative gate voltage, the trapped electrons are released from the trap states, while some holes are trapped at the interface traps. The initial positive gate voltage during the reverse scan attracts electrons to the WSe2 / HZO interface, leading to the depletion of electrons in WSe2. Conversely, when the forward scan starts from a large negative bias voltage, the trapped electrons are released from the trap states, while some holes are trapped at the interface traps, resulting in a larger hysteresis curve. Near zero gate voltage, the carrier concentration in the channel is extremely low, the device is in the off state, and the off-state current is as low as 10. -12 A-level, achieving 10 6 The above-mentioned ultra-high on / off ratio. At the same time, the high dielectric constant of HZO significantly enhances gate control efficiency and reduces device subthreshold swing and operating voltage; the gold electrode forms a low-resistance ohmic contact with the WSe2 channel, achieving high current density and completing the high-performance field-effect switching function.
[0031] Non-volatile storage working mechanism
[0032] The non-volatile resistive switching memory characteristic of this device originates from the reversible ferroelectric polarization reversal of the HZO gate dielectric layer and the charge trapping / release effect of the interface trap states. The HZO solid solution film, deposited alternately in a 1:1 ratio of HfO2 and ZrO2 single-deposition cycles, possesses stable ferroelectric properties and controllable interface trap states: when a positive gate pulse is applied to the gate electrode, the HZO film undergoes directional ferroelectric polarization reversal, significantly increasing the channel carrier concentration, and the device switches to the low-resistivity state (LRS); when a reverse pulse is applied to the gate electrode, the HZO film ferroelectric polarization reverses, significantly decreasing the channel electron concentration, and the device switches to the high-resistivity state (HRS). Relying on the non-volatility of the ferroelectric polarization and the charge trapping characteristics of the interface trap states, the high and low resistance states of the device can be stably maintained for more than 1500 seconds without external bias, and more than 1500 reversible cycle switchings can be achieved through continuous SET / RESET pulses without significant performance degradation, achieving stable non-volatile memory functionality.
[0033] Neuromorphic synapse bionic working mechanism
[0034] This device can highly replicate the core learning and memory behaviors of biological synapses. The core mechanism is to continuously, reversibly, and gradient control the charge trapping / release process at the HZO interface and the carrier concentration in the WSe2 channel through gate piezoelectric pulses / optical pulses, thereby achieving precise control of the channel conductivity (corresponding to the biological synapse weight) and completing the biomimetic synapse function. On the one hand, by applying gate piezoelectric pulses of different polarities and pulse widths, the charge trapping amount of the HZO interface trap state can be continuously controlled, thereby achieving bidirectional and precise gradient control of the WSe2 channel conductance, simulating the excitatory and inhibitory postsynaptic current (EPSC) response of biological synapses. On the other hand, by applying light pulses of different numbers and powers, photogenerated carriers can be excited in the WSe2 channel, enabling a change from short-range plasticity to long-range plasticity: under stimulation by a small number of light pulses, photogenerated carriers recombine rapidly, and the channel conductance quickly recovers to the initial state, simulating the short-range plasticity (STP) and two-pulse facilitation (PPF) behavior of biological synapses; as the number of light pulses increases, the number of photogenerated carriers trapped in the interface trap state increases, and the channel conductance can be maintained at a high level for a long time, achieving a controllable transition from short-range plasticity to long-range plasticity (LTP), perfectly replicating the core behavior of short-term memory to long-term memory conversion in biological nervous systems. Meanwhile, the device achieves synaptic function through localized carrier modulation of optical / electric pulses, without large-scale current transport, and the minimum operating power consumption can be as low as 16.28 fJ, meeting the hardware requirements of low-power neuromorphic computing systems.
[0035] Compared with the prior art, the present invention has the following core advantages:
[0036] A single-device architecture achieves three-function integration, breaking through the core bottleneck of heterogeneous integration and adapting to the development needs of high-density chips: This invention uses a vertically stacked, extremely simple architecture of "substrate gate - HZO gate dielectric - WSe2 channel - source / drain electrode" to achieve three core functions simultaneously within a single device without additional functional layers or complex multi-device stacking: ① High-performance bipolar field-effect transistor (BFET) n / p Type switch ratio >10 6 ); ② High-reliability non-volatile storage (on / off ratio > 10) 4 ① Maintaining time > 1500s, number of cycles > 1500 times; ② Multi-dimensional adjustable neuromorphic synaptic bionic functions (bidirectional weight control, short-range / long-range plasticity, minimum power consumption 16.28fJ). Compared with existing single-function two-dimensional transistors, this invention significantly reduces the number of functional devices in the chip system, reduces chip design complexity, interconnection losses and integration costs, and provides core device units for high-density, low-power heterogeneous integrated chips in the post-Moore's Law era.
[0037] The design of the HZO gate dielectric in this invention balances high gate control capability, high stability, and multifunctional adaptability: This invention uses an HZO thin film deposited with alternating atomic layers of HfO2 and ZrO2 in a 1:1 ratio as the gate dielectric. Compared with traditional SiO2 and single HfO2 gate dielectrics, it has three core advantages: ① The high dielectric constant significantly enhances the gate control efficiency, enabling the device to achieve >10 6 Ultra-high switching ratio, with off-state current as low as 10 -12 ① The A-level efficiency significantly reduces the device's static power consumption and operating voltage; ② The HZO thin film prepared by alternating deposition of HfO2 and ZrO2 single deposition cycles in a 1:1 ratio achieves atomic-level uniform control of the film composition, and the ferroelectric / resistive switching characteristics are stable and controllable. This solves the industry pain point of unstable ferroelectric properties and easy degradation during long-term operation of single HfO2 thin films, enabling the device to achieve >10 4 The storage switch window is stable and drift-free in both high and low resistance states for a long time, with a cycle life of over 1500 cycles; ③ The HZO thin film has excellent interface matching with silicon substrate and WSe2 channel, and low interface defect state density, which greatly reduces the impact of interface scattering on carrier transport. At the same time, it takes into account the three major functions of gate dielectric, resistive switching function and synaptic modulation, providing a material basis for multi-functional integration of single device. Attached Figure Description
[0038] Figure 1 This is a flowchart illustrating the fabrication process of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor prepared according to the present invention.
[0039] Figure 2 This is a 3D schematic diagram of the structure of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor prepared according to an embodiment of the present invention;
[0040] Figure 3 A cross-sectional schematic diagram of the structure of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor prepared according to an embodiment of the present invention;
[0041] Figure 4 The transfer characteristic curve of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor device prepared in the embodiment of the present invention;
[0042] Figure 5 The source and drain current of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor device prepared in the embodiments of the present invention. I ds Source-drain voltage V ds The relationship between the changes is used to obtain the output characteristic curve of the device.
[0043] Figure 6 Resistance state retention characteristic curve of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor device prepared for the embodiments of the present invention.
[0044] Figure 7The resistive state cycling characteristic curve of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor device prepared for the embodiments of the present invention (test cycle number not less than 1000 times).
[0045] Figure 8 The variation of source-drain current (i.e., postsynaptic current, EPSC) over time of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor prepared for an embodiment of the present invention.
[0046] Figure 9 The figure shows the simulation test results of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor device prepared in the embodiment of the present invention.
[0047] Figure 10 The figure shows the test results of the optical pulse number modulation synaptic plasticity transition characteristics of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor device prepared in the embodiment of the present invention; Detailed Implementation
[0048] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the following examples provide a more detailed description of the invention. It should be noted that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.
[0049] This invention pioneers a single-device, multi-functional integrated architecture based on a tungsten selenide-hafnium zirconium oxide (WSe2-HZO) heterojunction. Within a minimalist vertically stacked field-effect transistor structure, without the need for additional functional layers or multiple device stacking, it simultaneously achieves three core functions: high-performance bipolar field-effect logic switching, highly reliable non-volatile resistive switching memory, and multi-dimensional optoelectronic synaptic bionics. This fundamentally solves the core industry pain points of existing two-dimensional transistors, such as single-function design and the need for multiple device stacking in heterogeneous chip integration, resulting in large area, high power consumption, and complex design.
[0050] The present invention discloses an integrated device structure for a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor, characterized by a four-layer integrated architecture stacked vertically from bottom to top, consisting of heavily doped layers that serve as both mechanical support and bottom gate electrode. p The structure consists of a silicon substrate layer, a hafnium zirconium oxide (HZO) gate dielectric layer, a few-layer tungsten selenide (WSe2) nanosheet semiconductor channel layer, and gold source and drain electrode layers. This architecture enables the simultaneous implementation of three major functions—field-effect switching, non-volatile storage, and neuromorphic synaptic bionics—within a single device.
[0051] Based on the matching design of the WSe2-HZO heterojunction, a significant improvement in the overall performance of the device is achieved, simultaneously meeting the core performance requirements of three major scenarios: logic switching, non-volatile memory, and neuromorphic computing. This overcomes the bottleneck of existing two-dimensional devices' inability to be compatible with multiple scenarios. The core performance boundary of the multifunctional transistor is specifically defined as: possessing intrinsic bipolar transport characteristics. n Type andp The switching ratios of all conduction modes are greater than 10. 6 In non-volatile storage characteristics, the current switching window between the low-resistance state and the high-resistance state is greater than 10. 4 It has a resistive state stability time of more than 1500s and a cycle switching count of more than 1500 times; it has the ability to precisely control bidirectional synaptic weights and simulate full-scale synaptic plasticity, with a minimum operating power consumption as low as 16.28fJ.
[0052] This invention relates to a heterojunction interface matching design between a few-layer WSe2 nanosheet channel layer and an HZO gate dielectric layer. Through the synergistic matching of the intrinsic bipolar performance band structure of the 3-8 nm few-layer WSe2 with the high dielectric properties and interface charge trapping effect of HZO, excellent bipolar carrier transport, high gate control capability, stable resistive switching characteristics, and photoelectric synaptic response are simultaneously achieved. This solves the problem of poor channel-gate dielectric matching and inability to simultaneously meet multiple performance requirements in existing two-dimensional devices. The heterojunction core structure design of the transistor is characterized by: using a 3-8 nm thick few-layer WSe2 nanosheet flatly laid on the upper surface of the HZO gate dielectric layer as the bipolar semiconductor channel layer of the device, simultaneously undertaking the core functions of carrier transport, photoelectric response, and synaptic weighting regulation; the HZO gate dielectric layer is completely deposited on the upper surface of the substrate, with a thickness of 10-20 nm, simultaneously serving as the gate dielectric, resistive switching functional layer, and synaptic regulation functional layer; protecting the application of this heterojunction structure in multifunctional transistors.
[0053] This invention, based on the optoelectronic synaptic biomimetic functional design of this device architecture, simultaneously achieves bidirectional synaptic weight gradient modulation via electrical pulses, two-pulse facilitation (PPF) via optical pulses, and controllable transition from short-range plasticity (STP) to long-range plasticity (LTP) within a single device. It highly replicates the core learning and memory behaviors of biological synapses and possesses ultra-low operating power consumption, providing a high-performance hardware unit for low-power neuromorphic computing systems. The application of the neuromorphic synaptic biomimetic function of the multifunctional transistor protects the application of this device architecture in electro / optical dual-modulation synaptic devices and neuromorphic computing hardware units.
[0054] Performance data of the two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor device described in this invention:
[0055] Excellent transistor performance: The device exhibits bipolar characteristics, enabling it to conduct electricity primarily electronically (… n Type) and hole conduction are the main types ( p Switching between states of (type). n Type and p The switching ratio of all types is greater than 10. 6 Device transfer curve:
[0056] Test Procedure: Transfer curve testing of the device. During the test, a fixed DC bias voltage is applied to the source and drain. By applying a continuous scanning voltage from -4V to 4V to the bottom gate electrode, the relationship between the source / drain current and the gate voltage is recorded in real time to obtain the transfer characteristic curve of the device; the test results are as follows. Figure 4 As shown.
[0057] Results Analysis: Figure 4 As can be seen, this device exhibits typical bipolar transport characteristics: within the negative gate voltage scanning range, the source-drain current increases significantly with the increase of the absolute value of the gate voltage, demonstrating a clear [transmission characteristic]. p The source-drain current exhibits n-type conductivity behavior; within the positive gate voltage scanning range, the source-drain current increases significantly with increasing gate voltage, demonstrating clear n-type conductivity behavior. Furthermore, the curve shows significant hysteresis, further providing reliable data support for the measurement of its storage characteristics. n The shaped area exhibits a clockwise lag. p The hysteresis curve in the reverse region is counterclockwise. When a positive gate voltage is applied during the reverse scan, the ferropolarization in HZO is upward along the applied electric field, causing electrons to be trapped at the WSe2 / HZO interface, while holes are induced into the WSe2 channel. This is the opposite of the electron doping effect of the electrostatic field. Under a large negative gate voltage, the trapped electrons are released from the trap states, while some holes are trapped at the interface traps. The initial positive gate voltage during the reverse scan attracts electrons to the WSe2 / HZO interface, leading to the depletion of electrons in WSe2. Conversely, when the forward scan starts from a large negative bias voltage, the trapped electrons are released from the trap states, while some holes are trapped at the interface traps, resulting in a larger hysteresis curve. Near zero gate voltage, the carrier concentration in the channel is extremely low, the device is in the off state, and the off-state current is as low as 10. -12 A-level, achieving 10 6 The above-mentioned ultra-high on / off ratio. At the same time, the high dielectric constant of HZO significantly enhances gate control efficiency and reduces device subthreshold swing and operating voltage; the gold electrode forms a low-resistance ohmic contact with the WSe2 channel, which greatly improves carrier transport efficiency.
[0058] The output characteristics of the transistor device of the present invention are as follows: the device has good ohmic contact characteristics, gate control capability and high current drive capability. Under the conditions of 1V source-drain bias and 4.5V gate voltage, the normalized source-drain output current can reach 520μA / μm, which can meet the driving requirements of low power integrated circuits and neuromorphic devices.
[0059] Test Procedure: The device's output characteristic curve is tested. During the test, the source is grounded as a potential reference point, and a continuous sweep DC bias voltage from 0V to 1V is applied to the drain. V ds At the same time, a fixed DC gate voltage is applied to the bottom gate electrode. V gThe gate voltage was set to six gradients: -0.5V, 0.5V, 1.5V, 2.5V, 3.5V, and 4.5V; a complete cycle was performed at each fixed gate voltage. V ds Scan and record source and drain current I in real time ds Source-drain voltage V ds The relationship between the changes is used to obtain the output characteristic curve of the device, as shown in the figure. Figure 5 As shown.
[0060] Results Analysis: Figure 5 As can be seen, this device possesses a clear linear operating region and current saturation region, conforming to the operating characteristics of a classic field-effect transistor. V ds =1V、 V g Under a test condition of 4.5V, the device's normalized source-drain current reaches 520μA / μm, demonstrating excellent high-current drive capability. This characteristic stems from the fact that a positive gate voltage can induce a large number of electron carriers in the device channel. The higher the gate voltage, the higher the electron carrier concentration in the channel, the greater the channel conductivity, and the stronger the corresponding output current, fully demonstrating that the device has excellent gate control capability.
[0061] 2. Excellent non-volatile storage characteristics: The device possesses stable resistive state retention capability and cycle switching durability, with switching windows greater than 10 for both low-resistivity (LRS) and high-resistivity (HRS) states. 4 With a resistive state retention time greater than 1500s and a cycle switching count greater than 1500 times, it can meet the long-term reliable operation requirements of non-volatile storage and neuromorphic synaptic devices.
[0062] The resistance state retention characteristic test was conducted as follows: During the test, the source was grounded, a fixed small-amplitude DC bias voltage was applied to the drain, and the gate was set to a constant bias to eliminate gate voltage interference. The bias remained constant throughout the test to avoid changing the device's resistance state. First, a preset stimulus signal was used to set the device to a low-resistance state (LRS) and a high-resistance state (HRS). Then, for a test duration of up to 1500 seconds, the source-drain current (Id) under the fixed bias was continuously recorded. ds The relationship between the resistance state and time is used to obtain the resistance state retention characteristic curve of the device, such as... Figure 6 As shown. By Figure 6 As can be seen, during the 1500s continuous testing, the device exhibited excellent stability in both the low-resistivity and high-resistivity states. The low-resistivity current showed only a small, gradual decay, remaining at 10 throughout the test. -8 A~10 -6 In section A, there were no sudden drops, drifts, or failures; the high-resistivity current remained stable at 10 throughout the entire range.-11 The current level is extremely low, on the order of A, with no significant increase in leakage current or current fluctuations. Throughout the test period, a current switching window exceeding four orders of magnitude was maintained between the high and low resistance states, without significant window contraction. These results demonstrate that the device possesses excellent non-volatile resistive state retention capability, effectively preventing data loss and misreading, and providing a core foundation for the long-term stable operation of the device as a long-range plastic synaptic unit and non-volatile memory unit.
[0063] Resistance-state cycling endurance test: Test procedure: During the resistance-state cycling endurance test of the device, the source is grounded, a fixed small-amplitude DC bias voltage is applied to the drain, and the gate is set to a constant bias, which remains unchanged throughout the test. The device is subjected to continuous resistance-state cycling operations by alternately applying SET and RESET pulse signals. After each complete SET-RESET cycle, the source and drain currents corresponding to the low-resistance and high-resistance states are recorded using a fixed bias. The resistance-state cycling characteristic curve of the device is obtained. The number of test cycles is no less than 1000. Test results are as follows: Figure 7 As shown, by Figure 7 As can be seen, during 1000 consecutive resistance-state cycles, the device maintains excellent stability in both the low-resistance and high-resistance states. The low-resistance current remains consistently at 10. -6 The current is on the order of A, with no obvious fluctuations, drift, or failures; the high-resistivity current remains stable at 10 throughout the entire range. -11 A~10 -10 The device maintains a stable current switching window of more than four orders of magnitude between the A-level and low-resistivity states, without significant window shrinkage. This result demonstrates excellent cycle durability. During repeated resistive state erase / write switching, the resistive switching physical mechanism of the active layer remains stable and controllable, without irreversible material degradation or performance decline. The device can reliably cycle more than 1500 times, meeting the core requirements for repeated erase / write and long-term stable operation in non-volatile storage and neuromorphic computing applications.
[0064] 3. Excellent synaptic simulation characteristics: It realizes multi-dimensional and precisely controllable synaptic bionic functions within a single device architecture, and has bidirectional synaptic weight control capability, full-scale synaptic plasticity simulation capability and low power consumption characteristics. It can highly replicate the core learning and memory behavior of biological synapses, and provides a high-performance hardware unit for low-power neuromorphic computing systems.
[0065] The gate voltage-controlled postsynaptic current characteristics of the device were tested using the following method: During the test, the optical pulse stimulation parameters were kept constant, and multiple sets of electrical pulse signals (pre-voltage) with amplitudes of -0.5V and 0.5V were applied through the bottom gate electrode, with the pulse width increasing in a gradient. The changes in source-drain current (i.e., postsynaptic current, EPSC) over time were recorded in real time. The test results are as follows: Figure 8 As shown: by Figure 8 (Above) It can be seen that under negative gate voltage conditions, after applying multiple sets of -0.5V gate voltage pulses, the EPSC response of the device is significantly suppressed, and as the gate voltage pulse width continues to increase, the peak current of the EPSC shows a continuous decreasing trend, indicating that the suppression effect is continuously enhanced. From Figure 8 (Below) As can be seen, under the same initial state of negative gate voltage, after applying multiple sets of 0.5V gate voltage pulses, the EPSC response of the device is significantly enhanced. Furthermore, as the gate voltage pulse width gradually increases, the peak current of the EPSC shows a continuous upward trend, and the enhancement effect becomes increasingly significant. This test result clearly demonstrates that this device can achieve bidirectional regulation of the EPSC through the polarity of the gate voltage pulse, and can achieve precise quantitative control of the degree of EPSC suppression and enhancement by adjusting the pulse width of the gate voltage pulse. This is the core electrical regulation characteristic of this device.
[0066] Simulation test of the device's double-pulse facilitated behavior under applied optical pulse signal, the test results are as follows: Figure 9 As shown, the test scheme is as follows: During the test, the source is grounded, a fixed DC bias voltage is applied to the drain, and the gate is set to a constant bias to regulate the initial conductance state of the device. Only optical pulses are used as the presynaptic stimulation signal throughout the test. Two optical pulses with a 25ms interval are applied to the device (e.g., ...). Figure 9 The top left figure is used to characterize the two-pulse facilitation properties of this synaptic device; Result analysis: From Figure 9As can be seen, under a weak light power of 90 nW, two light pulses with an extremely short time interval were applied to the device (top left figure), and the source-drain current (i.e., postsynaptic current, EPSC) was recorded in real time over time. As shown in the bottom left figure, the first light pulse generated a small current spike, while the current spike generated by the immediately following second light pulse was significantly larger than the first, exhibiting obvious two-pulse facilitation (PPF) behavior, achieving two-pulse enhancement, and effectively simulating the short-term plasticity of biological synapses. Based on this, the relationship between the two-pulse facilitation rate (PPF exponent, defined as the ratio of the second pulse response current to the first pulse response current) and the two-pulse time interval (ΔT) was further systematically studied, and the results are shown in the right figure. With the increase of the two-pulse interval time, the PPF exponent showed a significant decreasing trend. This phenomenon indicates that the device's "memory" effect of recent light stimulation exists only on an extremely short timescale. As time progresses, photogenerated carriers recombine rapidly, trapped charges completely relax, the device's conductivity fully recovers to its initial dark state, and the enhancement effect disappears. This perfectly replicates the short-range ordered characteristics of biological synapses, namely, the behavior of synapses' short-term memory of recent stimuli decaying rapidly over time. Furthermore, as shown in the figure, the device's minimum power consumption is approximately 16.28 fJ, exhibiting excellent low-power characteristics.
[0067] The synaptic plasticity transition characteristics of the device were tested by controlling the number of optical pulses. The test procedure was as follows: the source was grounded, a fixed DC bias voltage was applied to the drain, and the gate was set to a constant bias to stabilize the initial conductance state of the device. Basic parameters such as optical pulse power and electrical bias were kept constant throughout the test. Different numbers of optical pulses were used as presynaptic stimuli. After applying 8, 20, 30, 40, and 70 consecutive optical pulses to the device, the relaxation decay characteristics of the source-drain current were continuously recorded after the optical stimulation ended. The test results are as follows: Figure 10 As shown: by Figure 10 It is evident that when the number of light pulses is small, the source and drain current of the device decays rapidly to the initial baseline after stimulation, exhibiting typical short-range plasticity (STP), i.e., short-range ordering characteristics. As the number of light pulses increases, the decay rate of the source and drain current of the device slows down significantly and can be maintained at a high conductivity level for a long time, realizing a controllable transition from short-range ordering to long-range ordering, exhibiting stable long-range plasticity (LTP), effectively simulating the core behavior of biological neural systems that achieves the conversion of short-term memory into long-term memory through repetitive stimulation.
[0068] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements can be made without departing from the principle of the present invention, and these improvements should also be considered within the scope of protection of the present invention.
Claims
1. A two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor, characterized in that, The transistor described is a vertically stacked semiconductor device structure, consisting of a substrate layer, an oxide layer, a tungsten selenide nanosheet channel layer, and a source / drain electrode layer from bottom to top. The materials, structures, parameters, spatial relationships, and connections of each layer are as follows: The substrate layer is heavily doped. p Type-100 silicon substrate, specifically 100-oriented. p ++-doped low-resistivity single-crystal silicon substrate, which is heavily doped without a native surface oxide layer. p Silicon wafers serve as the mechanical support substrate and back gate of devices; The oxide layer: Hafnium zirconium oxide (HZO) material is used as the gate dielectric layer of the device and is completely deposited on the upper surface of the substrate layer; The tungsten selenide nanosheet channel layer described above uses a few layers of tungsten selenide nanosheets, laid flat on the upper surface of the oxide layer, as the semiconductor channel layer of the device. The electrode layer includes a source electrode and a drain electrode, both of which are gold electrodes. The source electrode and the drain electrode are respectively fabricated at both ends of the tungsten selenide nanosheet and are in direct contact with the tungsten selenide nanosheet to form an electrical connection for the electrical signal input and output of the device.
2. The two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor according to claim 1, characterized in that, The thickness of the oxide layer is controlled between 10 and 20 nm; the oxide layer is a hafnium zirconium oxide layer, which is prepared by alternating deposition of HfO2 single deposition cycle and ZrO2 single deposition cycle in a 1:1 ratio, and the film composition is uniform.
3. The two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor according to claim 1, characterized in that, The thickness of the tungsten selenide nanosheet channel layer is 3–8 nm.
4. The two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor according to claim 1, characterized in that, The thickness of the electrode layer is 110 nm.
5. The method for fabricating a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor according to claims 1-4, characterized in that, The specific steps are as follows: Step 1: Heavy doping p Preparation and pretreatment of silicon substrates; Step 2: Atomic layer deposition of hafnium zirconium oxide gate dielectric layer; Step 3: Mechanical exfoliation and site-specific transfer of tungsten selenide nanosheets; Step 4: Source and drain electrode fabrication and device post-processing.
6. The method for fabricating a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor according to claim 5, characterized in that, The step 1 described above provides heavy doping. p Type-100 silicon substrate, the substrate being 100-oriented p ++Doped low-resistivity single-crystal silicon wafer, without a native surface oxide layer, step 1 specifically involves: First, the substrate is pre-treated by cleaning: the silicon wafer is cut into 1*1cm silicon wafers, and the silicon substrate is placed in distilled water, propanol solution and ethanol solution respectively for ultrasonic treatment for 2 minutes. The above cleaning process is repeated once. Finally, the silicon substrate is dried with dry nitrogen gas and set aside for use. The substrate was then cleaned with a 4% HF / H2O solution to completely remove the oxide layer formed by self-oxidation on the surface. The substrate was then treated with a UV ozone cleaner for 1 minute to achieve complete hydroxylation of the substrate surface, providing good substrate conditions for subsequent film formation.
7. The method for fabricating a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor according to claim 5, characterized in that, Step 2 involves using atomic layer deposition (ALD) to prepare a hafnium zirconium oxide thin film layer on the surface of a pretreated silicon substrate. The specific process parameters and operations are as follows: A four-channel ALD system was used to grow HZO thin films. The precursors for HfO2 were tetra(dimethylamino)hafnium (TDMA-Hf) and deionized water (H2O). A solid hafnium source was used to ensure the stability of the source during the growth process and to avoid the problems of poor thermal stability and easy decomposition of liquid tetra(dimethylamino)hafnium after long-term use. The heating temperature of the hafnium precursor source is 90℃, and the heating temperature of the oxygen source (deionized water) is 50℃; the precursor of ZrO2 is tetra(diethylamino)zirconium (TDEA-Zr) and deionized water (H2O), the heating temperature of the zirconium precursor source is 90℃, and the heating temperature of the oxygen source (deionized water) is 50℃. High-purity nitrogen is used as the carrier gas to maintain a high vacuum and pollution-free deposition atmosphere in the deposition chamber. Alternating atomic layer deposition is carried out in strict accordance with the 1:1 ratio of HfO2 single deposition cycle to ZrO2 single deposition cycle to ensure the uniformity of film composition.
8. The method for fabricating a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor according to claim 7, characterized in that, With 50 cycles each of HfO2 and ZrO2, a thickness of approximately 11 nm is obtained. By precisely controlling the total number of cycles of the 1:1 alternating deposition, HZO films with a target thickness of 10–20 nm are prepared.
9. The method for fabricating a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor according to claim 5, characterized in that, Step 3 involves preparing tungsten selenide nanosheets on PDMS using a mechanical exfoliation method. The prepared tungsten selenide nanosheets are then transferred to the upper surface of a hafnium zirconium oxide layer using a transfer platform. The specific operation procedure is as follows: Tungsten selenide single crystals were adhered to the surface of the tape using adhesive tape, and the tungsten selenide material was peeled off onto the PDMS substrate by mechanical peeling. Transparent thin-layer tungsten selenide nanosheets were screened using an optical microscope, and few-layer tungsten selenide nanosheets with suitable size and thickness of 3-8 nm were selected for later use using computer-aided testing software. The glass slide with PDMS is inverted and fixed, and the substrate with hafnium zirconium oxide grown is placed in the transfer station and fixed by vacuum adsorption. The lifting knob of the transfer device is adjusted to make the PDMS and the substrate accurately aligned and in contact. The substrate is heated at 125°C for 8 minutes. Then the lifting knob is adjusted to separate the PDMS from the substrate, thus completing the point transfer of tungsten selenide nanosheets on the surface of hafnium zirconium oxide layer. Gold electrodes were fabricated at both ends of the tungsten selenide nanosheet using photolithography and electron beam evaporation techniques to form the source electrode and drain electrode, respectively, ultimately resulting in a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor.
10. The method for fabricating a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor according to claim 5, characterized in that, Step 4 specifically includes: First, the sample is gently cleaned to remove surface dust and trace organic impurities, so as to avoid damaging the HZO functional layer and WSe2 channel. Subsequently, photoresist was spin-coated onto the sample surface using standard photolithography. After pre-baking, mask alignment, exposure, and development, photoresist patterns corresponding to the source, drain, and matching test pads were prepared at both ends of the WSe2 channel. The photolithographically completed sample was then placed in a high-vacuum electron beam evaporation device to deposit a gold electrode film with a thickness of 110 nm at room temperature. After deposition, the photoresist and metal film in non-target areas are removed by a stripping process, leaving only the source and drain metal electrodes in the preset pattern area. Then, the sample is placed in a tube furnace at 350°C for annealing for 1 hour. After annealing, the sample is removed to obtain a two-dimensional tungsten selenide-hafnium zirconium oxide multifunctional transistor with a complete structure that can be directly tested for electrical performance.