Semiconductor structure, method of fabricating a gate structure, and method of reducing defects

Abstract

The application belongs to the technical field of semiconductors, and discloses a semiconductor structure, a preparation method of a gate structure and a method for reducing defects. After a pseudo gate structure and a gate side wall are prepared, before a metal silicide forming process, a reaction gas containing a silicon source and a nitrogen source is used to react with exposed polysilicon gates in the pseudo gate structure at defect positions of the gate side wall, so that a nitrogen-containing protective layer is formed. The application can ensure that the polysilicon can be etched to be smoothly opened in the process of removing the pseudo gate, can avoid generating under-etching defects, and can further improve the yield of the semiconductor structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and more specifically, relates to a method for preparing a semiconductor structure and a gate structure, as well as a method for reducing defects. Background Technology

[0002] In advanced chip manufacturing at 28nm and below, high dielectric constant metal gates are widely used. K-MetalGate (HK-MG) technology is used to improve chip performance. The basic process of the Gate-Last process typically involves sequentially fabricating a gate dielectric layer, a polysilicon layer, and a mask layer on a semiconductor substrate, followed by etching to form a dummy gate structure, depositing a sidewall material layer, and then using selective etching to form the gate sidewalls. Next, source and drain ion implantation and high-temperature annealing are performed to form the source and drain regions. Finally, a low-resistivity contact layer is formed in the source and drain regions using a metal silicide process. Improper process control can damage the gate sidewalls, resulting in defects such as voids and cracks before the metal silicide process. Figure 1 The diagram shown illustrates the voids generated before the metal silicide process. Figure 1 A dummy gate structure and a gate sidewall 300 located on its sidewalls have been fabricated on the semiconductor substrate 100. The dummy gate structure includes a gate dielectric layer 210, a polysilicon layer 220, and a mask layer 230 stacked sequentially from bottom to top. Figure 1Due to improper process control, a defect 400 resembling a hole was formed on the gate sidewall 300 of the right side of the transistor on the left side, which exposed the polysilicon layer 220 inside the gate sidewall 300 (allowing it to contact the outside world). Among them, the damage to the gate sidewall mainly comes from the following core scenarios, each of which is closely related to the specific process technology and will cause different degrees of damage to the sidewall structure: (1) The first source of damage is the dummy gate fabrication process. If the shape or size of the dummy gate (virtual gate) is not properly controlled, such as the dummy gate sidewall being rough or having residues, the subsequent deposition of sidewall material may result in uneven coverage, leading to local stress concentration or poor bonding, thereby forming holes or cracks in the sidewall. (2) The second source of damage is particles falling off during the sidewall deposition process or uneven film thickness. During the deposition of gate sidewalls (such as the deposition of dielectric materials such as silicon nitride and silicon oxide), whether it is chemical vapor deposition (CVD) or physical vapor deposition (PVD), the reaction chamber, target material, gas pipeline and other components inside the equipment are prone to generating small particles. These particles may detach from the chamber wall or component surface due to factors such as airflow disturbance and unstable process parameters, and attach to and impact the sidewall surface that is being deposited. Since the sidewall material has not been fully cured at this time, the structure is relatively fragile. The impact of particles will cause the sidewall surface to have dents, scratches, or even local material detachment, which will damage the flatness and continuity of the sidewall and create hidden dangers for further damage in subsequent processes. Uneven film thickness will also produce defects when encountering irregular pseudo-gate shape. (3) The third source of damage is the damage to the sidewall caused by the subsequent ion implantation process. After the gate sidewall deposition is completed, in the subsequent ion implantation process, the high-energy ion beam will directly bombard the device surface, and some of the ions will impact the gate sidewall surface. The impact of high-energy ions can destroy the atomic bond structure of the sidewall material, resulting in damage to the sidewall surface. This source has a particularly large impact when the sidewall thickness is uneven or there are weak points. (4) The fourth source of damage is the damage caused to the sidewall by dry etching or wet etching processes when the sidewall is formed by selective etching after the sidewall material is deposited. During the etching process, although the etchant is highly selective and the etching rate on the horizontal sidewall material is much higher than that on the vertical sidewall material, etching still occurs on the vertical sidewall material (sidewall sidewall). If the etching process parameters are not properly controlled, the vertical sidewall material will be over-etched, resulting in problems such as sidewall thinning and contour deformation. When the sidewall material is deposited, if there are residues in the previous pseudo-gate etching process or residues in the deposition process, the vertical sidewall material will be over-etched, which will cause the sidewall to have depressions or gaps, thus exposing the polysilicon in the gate sidewall.

[0003] After the polysilicon gate (i.e., silicon) is exposed, it reacts with the silicon during the subsequent nickel-silicon (NiSi) deposition process in the metal silicide process (in which platinum (Pt) is usually added to the deposited nickel-Ni film to form a NiPt alloy to optimize the performance of NiSi), thereby forming nickel-platinum (NiPt) residues on the polysilicon surface (see Nickel-platinum residue 500). Figure 2 (This is for illustrative purposes only; nickel-platinum residue 500 may adhere to the polysilicon surface or extend into the polysilicon interior.) Subsequent etching to remove the dummy gate typically employs processes with extremely high selectivity for metals (especially aluminum) and oxides, making it difficult to etch away the nickel-platinum residue 500. This issue prevents the subsequent dummy gate removal etching process from properly removing the residue, leading to an under-etch defect. See [link to documentation]. Figure 3 , Figure 3 The dummy gate structure of the transistor on the left cannot be removed properly because it is blocked by the residual nickel-platinum 500, while the dummy gate structure of the transistor on the right can be removed normally. This causes a defect in the gate of the transistor on the left, which ultimately affects the yield of the semiconductor structure.

[0004] Therefore, finding a solution to the above-mentioned technical problems is an urgent issue to be addressed in semiconductor manufacturing processes. Summary of the Invention

[0005] This invention provides a method for fabricating a semiconductor structure and a gate structure, as well as a method for reducing defects, thereby solving the problem in the prior art where under-etching defects are easily caused when the gate sidewall is damaged, which in turn affects the yield of the semiconductor structure.

[0006] In a first aspect, the present invention provides a method for reducing semiconductor structural defects. After the fabrication of the dummy gate structure and the gate sidewall, and before the metal silicide formation process, a nitrogen-containing protective layer is formed at the defect site of the gate sidewall by reacting a reactive gas containing a silicon source and a nitrogen source with the exposed polysilicon gate in the dummy gate structure.

[0007] Preferably, the reaction gas containing silicon and nitrogen sources uses a single-source precursor, which is one of hexamethyldisilazane or divinyltetramethyldisilazane; when the single-source precursor is used, the nitrogen-containing protective layer formed is a silicon carbonitride protective layer.

[0008] Preferably, the reaction gas containing silicon and nitrogen sources is an oxygen-free mixed gas, which is one of the following combinations: silane and ammonia, silane and nitrogen, disilane and ammonia, or trimethylsilane and ammonia. When any one of the following combinations is used, the nitrogen-containing protective layer formed is a silicon nitride protective layer; when the combination of trimethylsilane and ammonia is used, the nitrogen-containing protective layer formed is a carbon-containing silicon nitride protective layer.

[0009] Preferably, the reaction gas containing the silicon source and the nitrogen source is an oxygen-containing mixed gas, wherein the oxygen-containing mixed gas is one of the following: a combination of silane and nitrous oxide, a combination of tetraethoxysilane and nitrous oxide, or a combination of trimethylsilane and nitrous oxide; when a combination of silane and nitrous oxide is used, the nitrogen-containing protective layer formed is a silicon oxynitride protective layer; when a combination of tetraethoxysilane and nitrous oxide is used, the nitrogen-containing protective layer formed is a carbon-doped silicon oxynitride protective layer; when a combination of trimethylsilane and nitrous oxide is used, the nitrogen-containing protective layer formed is a silicon carbonitride protective layer.

[0010] Preferably, the silicon carbonitride protective layer SiC x N y The range of x / y is 0.1 to 0.3.

[0011] Preferably, plasma immersion is used to provide reaction energy to form the nitrogen-containing protective layer.

[0012] Preferably, when plasma immersion is used to provide reaction energy, the temperature range is 300°C to 500°C, the radio frequency power range is 200W to 1000W, and the immersion time is 10 seconds to 60 seconds.

[0013] Preferably, ultraviolet light is used to provide reaction energy to form the nitrogen-containing protective layer.

[0014] In a second aspect, the present invention provides a method for preparing a semiconductor structure, comprising the following steps: A semiconductor substrate is provided, on which a dummy gate structure is formed, the dummy gate structure comprising at least a gate dielectric layer, a polysilicon layer and a mask layer stacked sequentially from bottom to top, and the sidewalls of the dummy gate structure are formed with gate sidewalls. Source and drain regions are formed; At the defects in the gate sidewall, a nitrogen-containing protective layer is formed by reacting a reactive gas containing silicon and nitrogen sources with the exposed polysilicon gate. A low-resistivity contact layer is formed in the source region and the drain region using a metal silicide process.

[0015] Preferably, the reaction gas containing silicon and nitrogen sources is a single-source precursor, an oxygen-free mixed gas, or an oxygen-containing mixed gas.

[0016] Preferably, plasma immersion or ultraviolet light is used to provide reaction energy to form the nitrogen-containing protective layer.

[0017] Thirdly, the present invention provides a method for preparing a gate structure, comprising the following steps: A semiconductor substrate is provided, on which a dummy gate structure is formed, the dummy gate structure comprising at least a gate dielectric layer, a polysilicon layer and a mask layer stacked sequentially from bottom to top, and the sidewalls of the dummy gate structure are formed with gate sidewalls. Source and drain regions are formed; At the defects in the gate sidewall, a nitrogen-containing protective layer is formed by reacting a reactive gas containing silicon and nitrogen sources with the exposed polysilicon gate. A low-resistivity contact layer is formed in the source region and the drain region using a metal silicide formation process; An interlayer dielectric layer is fabricated to fill the periphery of the pseudo-gate structure and the gate sidewall; A thinning process is employed to stop the process at the top of the polycrystalline silicon layer; The polysilicon layer and at least a portion of the nitrogen-containing protective layer are removed by an etching process to expose the bottom gate dielectric layer, forming a trench for filling the metal gate; The trench is filled with a metal grid.

[0018] Preferably, when the nitrogen-containing protective layer is a silicon carbonitride protective layer, the nitrogen-containing protective layer is removed by wet hot phosphoric acid etching or dry fluorine-based plasma etching.

[0019] One or more technical solutions provided in this invention have at least the following technical effects or advantages: In this invention, after the fabrication of the dummy gate structure (which includes at least a gate dielectric layer, a polysilicon layer, and a mask layer stacked sequentially from bottom to top) and the gate sidewall (located on the sidewall of the dummy gate structure), and before the metal silicide formation process, a nitrogen-containing protective layer is formed at the defects in the gate sidewall by reacting a reactive gas containing silicon and nitrogen sources with the exposed polysilicon gate in the dummy gate structure. The unexpected effects achievable by this invention include: by forming the nitrogen-containing protective layer, this protective layer effectively prevents nickel atoms from penetrating into the polysilicon during subsequent nickel-silicon processes, ensuring that the polysilicon can be smoothly etched open during dummy gate removal, avoiding under-etching defects, and thus improving the semiconductor structure yield. Attached Figure Description

[0020] Figure 1 This is a schematic diagram showing damage to the gate sidewall; Figure 2A schematic diagram showing the formation of nickel-platinum residues on the surface of polycrystalline silicon; Figure 3 This is a schematic diagram illustrating the underetching defect caused by the etching process failing to remove residues properly. Figure 4 This is a schematic diagram of the formation of a nitrogen-containing protective layer in the method for reducing semiconductor structural defects provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram illustrating the process of removing dummy gates based on the method for reducing semiconductor structural defects provided in Embodiment 1 of the present invention. Figure 6 This is a flowchart of a method for fabricating a semiconductor structure according to Embodiment 2 of the present invention; Figure 7 This is a flowchart of a method for fabricating a gate structure provided in Embodiment 3 of the present invention; Figure 8 This is a schematic diagram of the structure obtained after completing M2 in the method for fabricating a gate structure according to Embodiment 3 of the present invention; Figure 9 This is a schematic diagram of the structure obtained after completing M3 according to the method for fabricating a gate structure provided in Embodiment 3 of the present invention; Figure 10 This is a schematic diagram of the structure obtained after completing M4 according to the method for fabricating a gate structure provided in Embodiment 3 of the present invention; Figure 11 This is a schematic diagram of the structure obtained after completing M5 in the method for fabricating a gate structure according to Embodiment 3 of the present invention; Figure 12 This is a schematic diagram of the structure obtained after completing M6 according to the method for fabricating a gate structure provided in Embodiment 3 of the present invention; Figure 13 This is a schematic diagram of the structure obtained after completing M7 according to the method for fabricating a gate structure provided in Embodiment 3 of the present invention; Figure 14 This is a schematic diagram of the structure obtained after completing M8 in a method for fabricating a gate structure according to Embodiment 3 of the present invention.

[0021] Among them, 100-semiconductor substrate, 210-gate dielectric layer, 220-polysilicon layer, 230-mask layer, 231-nitride dielectric layer, 232-oxide dielectric layer, 300-gate sidewall, 400-defect, 500-nickel-platinum residue, 600-nitrogen-containing protective layer, 710-source region, 720-drain region, 800-low-resistance contact layer, 900-interlayer dielectric layer, 1000-metal gate. Detailed Implementation

[0022] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0023] Example 1: Example 1 provides a method for reducing semiconductor structural defects, see [link to example]. Figure 1 , Figure 4 and Figure 5 After the dummy gate structure and gate sidewall 300 are fabricated, but before the metal silicide formation process, at the defect 400 of the gate sidewall 300, a nitrogen-containing protective layer 600 is formed by reacting a reactive gas containing silicon and nitrogen sources with the exposed polysilicon gate in the dummy gate structure. Figure 4 As shown, the nitrogen-containing protective layer 600 can not only prevent the polysilicon layer 220 from reacting with and forming byproducts during the metal silicide formation process, but also can be easily removed in the subsequent etching process of the pseudo-gate structure. The effect after removing the pseudo-gate structure is as follows: Figure 5 As shown.

[0024] In Example 1, after the fabrication of the dummy gate structure (which includes at least a gate dielectric layer 210, a polysilicon layer 220, and a mask layer 230 stacked sequentially from bottom to top, and is located on the semiconductor substrate 100) and the gate sidewall 300 (located on the sidewall of the dummy gate structure), before the metal silicide formation process, a nitrogen-containing protective layer 600 is formed at the defect 400 of the gate sidewall 300 by reacting a reactive gas containing silicon and nitrogen sources with the exposed polysilicon gate in the dummy gate structure. Example 1 utilizes the nitrogen-containing protective layer 600 to effectively prevent nickel atoms from penetrating into the polysilicon during subsequent nickel-silicon processes, ensuring that the polysilicon can be smoothly etched open during dummy gate removal, avoiding under-etching defects, and thus improving the semiconductor structure yield.

[0025] The gate dielectric layer 210 can be a thermally oxidized layer or other suitable dielectric material, such as silicon oxide or silicon nitride. For example, the gate dielectric layer 210 is made of silicon dioxide and is formed by thermal oxidation.

[0026] The mask layer 230 includes a nitrided dielectric layer 231 and an oxide dielectric layer 232 from bottom to top. The nitrided dielectric layer 231 can be made of silicon nitride or the like, and the oxide dielectric layer 232 can be made of silicon dioxide or silicon oxide or the like.

[0027] The gate sidewall 300 can be made of silicon nitride, silicon oxide, or a low dielectric constant material. The gate sidewall 300 can have a single-layer or multi-layer structure. For example, in Embodiment 1, the gate sidewall 300 can be constructed using silicon nitride with a single-layer structure.

[0028] The reaction gas used in Example 1 will be described below.

[0029] The reaction gas containing silicon and nitrogen sources can be a single-source precursor, an oxygen-free mixed gas, or an oxygen-containing mixed gas.

[0030] (1) When the reaction gas containing silicon and nitrogen sources uses a single-source precursor, the single-source precursor can be hexamethyldisilazane (HMDS), divinyltetramethyldisilazane (i.e., 1,3-divinyl-1,1,3,3-tetramethyldisilazane), etc. Wherein, when the single-source precursor is used, the nitrogen-containing protective layer formed is silicon carbonitride (SiC). x N y The protective layer is then removed by dry etching (fluorine-based (CF4 / SF6) plasma etching) or hot phosphoric acid wet etching.

[0031] (2) When the reaction gas containing the silicon source and nitrogen source is an oxygen-free mixed gas, the oxygen-free mixed gas may be a combination of silane (SiH4) and ammonia (NH3), a combination of silane (SiH4) and nitrogen (N2), a combination of disilane (Si2H6) and ammonia (NH3), a combination of trimethylsilane (3MS) and ammonia (NH3), or other combinations. Wherein, when any one of the combinations of silane and ammonia, silane and nitrogen, or disilane and ammonia is used, the nitrogen-containing protective layer formed is silicon nitride (SiN). x Protective layer; When a combination of trimethylsilane and ammonia is used, the nitrogen-containing protective layer formed is a silicon carbonitride (SiCN) protective layer, which can be subsequently removed by dry etching (fluorine-based (CF4 / SF6) plasma etching) or hot phosphoric acid wet etching. The specific process parameters are adjusted according to the type of protective layer.

[0032] (3) When the reaction gas containing the silicon source and nitrogen source is an oxygen-containing mixed gas, the oxygen-containing mixed gas may be a combination of silane (SiH4) and nitrous oxide (N2O), a combination of tetraethoxysilane (TEOS) and nitrous oxide (N2O), a combination of trimethylsilane (3MS) and nitrous oxide (N2O), or other combinations. Wherein, when a combination of silane and nitrous oxide is used, the nitrogen-containing protective layer formed is silicon oxynitride (SiO2). x N y Protective layer; when a combination of tetraethoxysilane and nitrous oxide is used, the nitrogen-containing protective layer formed is carbon-doped silicon oxynitride (SiO2). x C y N2) protective layer; when a combination of trimethylsilane and nitrous oxide is used, the resulting nitrogen-containing protective layer is silicon carbonitride (SiC). x N y The protective layer can be removed by dry etching (fluorine-based (CF4 / SF6) plasma etching) or wet etching with dilute hydrofluoric acid; the specific process parameters are adjusted according to the type of protective layer.

[0033] Among them, the silicon carbonitride protective layer SiC x N y The x / y ratio is preferably in the range of 0.1 to 0.3. Within this range, the silicon carbonitride protective layer exhibits better adhesion and stability, resulting in better preparation performance.

[0034] When plasma immersion is used to provide reaction energy, the temperature range is 300℃ to 500℃, the radio frequency power range is 200W to 1000W, and the immersion time is 10 seconds to 60 seconds.

[0035] The aforementioned temperature range represents the optimal range for the plasma reaction, ensuring sufficient dissociation of the reactant gases without causing excessive damage to the polycrystalline silicon surface. The radio frequency (RF) power determines the plasma density and energy, thus affecting the film's compactness. Excessive power leads to intensified etching of the polycrystalline silicon surface, while insufficient power fails to form a uniform protective layer. Considering all factors, Example 1, by setting the aforementioned RF power range, achieves a nitrogen-containing protective layer with excellent performance.

[0036] Furthermore, compared to other methods, plasma immersion results in a nitrogen-containing protective layer with stronger adhesion and does not introduce additional interface defects. The formed nitrogen-containing protective layer exhibits high density and chemical stability, preventing the formation of nickel-platinum residues on the polycrystalline silicon surface.

[0037] Taking nitrous oxide and trimethylsilane as the reactant gases as an example, the flow rate of nitrous oxide ranges from 400 sccm to 2000 sccm, and the flow rate of trimethylsilane ranges from 100 sccm to 1000 sccm. Nitrogen can be used as an auxiliary gas during the preparation process, with a carrier gas flow rate ranging from 1000 sccm to 10000 sccm. The above flow rate ranges result in a nitrogen-containing protective layer with suitable mechanical stress and density, avoiding situations where the stress of the nitrogen-containing protective layer is too high or too low.

[0038] In summary, in Example 1, a nitrogen-containing protective layer is formed at the defect in the gate sidewall by reacting a reactive gas containing silicon and nitrogen sources with the exposed polysilicon gate in the dummy gate structure. This protective layer effectively prevents nickel atoms from penetrating into the polysilicon during subsequent nickel-silicon processes, ensuring that the polysilicon can be smoothly etched open during dummy gate removal, avoiding under-etching defects, and thus improving semiconductor structure yield. Example 1 plays a crucial role in stabilizing and improving chip yield.

[0039] Based on Example 1, the present invention further provides a method for preparing a semiconductor structure and a method for preparing a gate structure, which are described below with reference to Example 2 and Example 3.

[0040] Example 2: Example 2 provides a method for fabricating a semiconductor structure, see [link to example]. Figure 6 This includes the following steps: S1, such as Figure 1 As shown, a semiconductor substrate 100 is provided, on which a dummy gate structure is formed. The dummy gate structure includes at least a gate dielectric layer 210, a polysilicon layer 220 and a mask layer 230 stacked sequentially from bottom to top, and a gate sidewall 300 is formed on the sidewall of the dummy gate structure.

[0041] The semiconductor substrate may be a silicon substrate or a substrate made of other semiconductor materials.

[0042] S2, forming source and drain regions.

[0043] S2 mainly includes two sub-steps: ion implantation and high-temperature annealing activation. Ion implantation involves the exposed areas on both sides of the dummy gate structure, which are the areas to be formed as source and drain regions. Dopant ions are implanted into these exposed areas using an ion implantation device, either perpendicular to the semiconductor substrate or at an angle. The implantation energy is set according to the desired source-drain junction depth to control the projected range of the dopant ions in the semiconductor substrate; the implantation dose is set according to the required doping concentration in the source-drain regions to control the concentration distribution of the dopant ions. High-temperature annealing activation involves placing the ion-implanted semiconductor substrate in an annealing device for heat treatment. The annealing process activates the implanted dopant ions, causing dopant atoms located at interstitial positions to migrate to substitutional positions in the silicon lattice through thermal motion, thereby generating free carriers to achieve conductivity; simultaneously, the annealing process also repairs damage caused by high-energy ion bombardment in the silicon lattice. After annealing, source regions 710 and drain regions 720 with specific junction depths are formed in the semiconductor substrate on both sides of the dummy gate structure, such as... Figure 8 As shown.

[0044] S3. At the defect 400 of the gate sidewall 300, a nitrogen-containing protective layer 600 is formed by reacting a reactive gas containing a silicon source and a nitrogen source with the exposed polysilicon gate. Figure 9 As shown.

[0045] The reaction gas containing silicon and nitrogen sources is a single-source precursor, an oxygen-free mixed gas, or an oxygen-containing mixed gas. Reaction energy can be provided using methods such as plasma immersion or ultraviolet light to form the nitrogen-containing protective layer. Specific details of this step can be found in Example 1.

[0046] S4. Using a metal silicide process, a low-resistivity contact layer 800 is formed in the source region 710 and the drain region 720, such as... Figure 10 As shown.

[0047] In this process, metals (e.g., Ni, Co, Ti) are deposited in the exposed source and drain regions, and low-resistivity metal silicide contacts are formed through an annealing reaction.

[0048] In summary, Example 2, combined with the method for reducing semiconductor structure defects provided in Example 1, presents a method for preparing a semiconductor structure. Example 2 can utilize a nitrogen-containing protective layer to ensure that polysilicon can be successfully etched open during the removal of dummy gates, ultimately resulting in a high-yield semiconductor structure.

[0049] Example 3: Example 3 provides a method for fabricating a gate structure, see below. Figure 7 This includes the following steps: M1. A semiconductor substrate is provided, on which a dummy gate structure is formed. The dummy gate structure includes at least a gate dielectric layer, a polysilicon layer, and a mask layer stacked sequentially from bottom to top, and the sidewalls of the dummy gate structure form gate sidewalls. See steps S1 and S2 in Embodiment 2 for details. Figure 1 .

[0050] M2 forms the source region and the drain region.

[0051] See step S2 in Example 2 for details. Figure 8 .

[0052] M3. At the defect in the gate sidewall, a nitrogen-containing protective layer is formed by reacting a reaction gas containing silicon and nitrogen sources with the exposed polysilicon gate.

[0053] The reaction gas containing silicon and nitrogen sources is a single-source precursor, an oxygen-free mixed gas, or an oxygen-containing mixed gas. Reaction energy can be provided using methods such as plasma immersion or ultraviolet light to form the nitrogen-containing protective layer. See steps S3 and S4 in Example 2 for details. Figure 9 An active region 710 and a drain region 720 are formed, and a nitrogen-containing protective layer 600 is formed thereon.

[0054] M4. A low-resistance contact layer is formed in the source region and the drain region using a metal silicide formation process.

[0055] See step S4 in Example 2 for details. Figure 10 A low-resistance contact layer of 800 is formed.

[0056] M5. Fabricate an interlayer dielectric layer to fill the perimeter of the pseudo-gate structure and the gate sidewall.

[0057] This refers to the deposition of interlayer dielectric layers, where dielectric materials such as silicon oxide are deposited on the device to cover all structures.

[0058] The structure obtained after completing step M5 is shown in the figure. Figure 11 The interlayer medium layer 900 is deposited thereon.

[0059] M6. A thinning process is used to stop at the top of the polycrystalline silicon layer.

[0060] Specifically, M6 may include: planarizing the interlayer dielectric layer and stopping at the top surface of the polysilicon layer; the planarization process can be performed in two steps using chemical mechanical polishing (CMP); first, grinding and polishing until the top of the dummy gate structure is exposed; then, continuing to grind and polish using CMP until stopping at the top of the polysilicon layer 220, as shown. Figure 12 As shown.

[0061] M7. The polysilicon layer and at least a portion of the nitrogen-containing protective layer are removed using an etching process to expose the bottom gate dielectric layer, forming a trench for filling the metal gate.

[0062] The removal of the polysilicon layer and at least a portion of the nitrogen-containing protective layer can be achieved by wet or dry etching.

[0063] For example, when the nitrogen-containing protective layer is a silicon carbonitride protective layer or a silicon nitride protective layer, wet hot phosphoric acid can be used to effectively remove the protective layer. Alternatively, dry fluorine-based plasma etching can also be used to remove the nitrogen-containing protective layer.

[0064] For example, when the nitrogen-containing protective layer is a silicon oxynitride protective layer, wet dilute hydrofluoric acid can be used to effectively remove the protective layer, or dry fluorine-based plasma etching can be used to remove the nitrogen-containing protective layer. These removal processes can efficiently remove the nitrogen-containing protective layer without damaging other structures, such as the gate sidewall, low-resistance contact layer, and substrate.

[0065] See the structure obtained after completing M7. Figure 13 After etching, the gate dielectric layer 210 is exposed.

[0066] M8. Fill the trench with a metal grid; the metal grid can be made using existing technologies and can be a single-layer or multi-layer structure, with no specific limitation.

[0067] The structure obtained after completing M8 is shown in the figure. Figure 14 The groove is filled with the metal grid 1000.

[0068] The gate structure prepared in Example 3 is a high dielectric constant metal gate, wherein the metal gate 1000 includes a metal work function layer and a metal conductive material layer stacked sequentially.

[0069] In summary, Example 3, combined with the method for reducing semiconductor structural defects provided in Example 1, presents a method for preparing a gate structure. Example 3 utilizes a nitrogen-containing protective layer to ensure that polysilicon can be successfully etched open during the removal of dummy gates, ultimately resulting in a high-yield gate structure.

[0070] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for reducing defects in semiconductor structures, characterized in that, After the dummy gate structure and gate sidewall are fabricated, but before the metal silicide formation process, a nitrogen-containing protective layer is formed at the voids or cracks in the gate sidewall by reacting a reactive gas containing silicon and nitrogen sources with the exposed polysilicon gate in the dummy gate structure.

2. The method for reducing semiconductor structural defects according to claim 1, characterized in that, The reaction gas containing silicon and nitrogen sources uses a single-source precursor, which is one of hexamethyldisilazane or divinyltetramethyldisilazane; when the single-source precursor is used, the nitrogen-containing protective layer formed is a silicon carbonitride protective layer.

3. The method for reducing semiconductor structural defects according to claim 1, characterized in that, The reaction gas containing silicon and nitrogen sources is an oxygen-free mixed gas, which is one of the following combinations: silane and ammonia, silane and nitrogen, disilane and ammonia, or trimethylsilane and ammonia. When any one of the following combinations is used, the nitrogen-containing protective layer formed is a silicon nitride protective layer; when the combination of trimethylsilane and ammonia is used, the nitrogen-containing protective layer formed is a carbon-containing silicon nitride protective layer.

4. The method for reducing semiconductor structural defects according to claim 1, characterized in that, The reaction gas containing silicon and nitrogen sources is an oxygen-containing mixed gas, which is one of the following: a combination of silane and nitrous oxide, a combination of tetraethoxysilane and nitrous oxide, or a combination of trimethylsilane and nitrous oxide. When a combination of silane and nitrous oxide is used, the nitrogen-containing protective layer formed is a silicon oxynitride protective layer. When a combination of tetraethoxysilane and nitrous oxide is used, the nitrogen-containing protective layer formed is a carbon-doped silicon oxynitride protective layer. When a combination of trimethylsilane and nitrous oxide is used, the nitrogen-containing protective layer formed is a silicon carbonitride protective layer.

5. The method for reducing semiconductor structural defects according to claim 2 or 4, characterized in that, The silicon carbonitride protective layer SiC x N y The range of x / y is 0.1 to 0.

3.

6. The method for reducing semiconductor structural defects according to claim 1, characterized in that, The reaction energy is provided by plasma immersion to form the nitrogen-containing protective layer.

7. The method for reducing semiconductor structural defects according to claim 6, characterized in that, When plasma immersion is used to provide reaction energy, the temperature range is 300°C to 500°C, the radio frequency power range is 200W to 1000W, and the immersion time is 10 seconds to 60 seconds.

8. The method for reducing semiconductor structural defects according to claim 1, characterized in that, Ultraviolet light is used to provide reaction energy to form the nitrogen-containing protective layer.

9. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, on which a dummy gate structure is formed, the dummy gate structure comprising at least a gate dielectric layer, a polysilicon layer and a mask layer stacked sequentially from bottom to top, and the sidewalls of the dummy gate structure are formed with gate sidewalls. Source and drain regions are formed; At the voids or cracks in the gate sidewall, a nitrogen-containing protective layer is formed by reacting a reactive gas containing silicon and nitrogen sources with the exposed polysilicon gate. A low-resistivity contact layer is formed in the source region and the drain region using a metal silicide process.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The reaction gas containing silicon and nitrogen sources is a single-source precursor, an oxygen-free mixed gas, or an oxygen-containing mixed gas.

11. The method for preparing a semiconductor structure according to claim 9, characterized in that, The nitrogen-containing protective layer is formed by using plasma immersion or ultraviolet light to provide reaction energy.

12. A method for fabricating a gate structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, on which a dummy gate structure is formed, the dummy gate structure comprising at least a gate dielectric layer, a polysilicon layer and a mask layer stacked sequentially from bottom to top, and the sidewalls of the dummy gate structure are formed with gate sidewalls. Source and drain regions are formed; At the voids or cracks in the gate sidewall, a nitrogen-containing protective layer is formed by reacting a reactive gas containing silicon and nitrogen sources with the exposed polysilicon gate. A low-resistivity contact layer is formed in the source region and the drain region using a metal silicide formation process; An interlayer dielectric layer is fabricated to fill the periphery of the pseudo-gate structure and the gate sidewall; A thinning process is employed to stop the process at the top of the polycrystalline silicon layer; The polysilicon layer and at least a portion of the nitrogen-containing protective layer are removed by an etching process to expose the bottom gate dielectric layer, forming a trench for filling the metal gate; The trench is filled with a metal grid.

13. The method for fabricating the gate structure according to claim 12, characterized in that, When the nitrogen-containing protective layer is a silicon carbonitride protective layer, the nitrogen-containing protective layer is removed by wet hot phosphoric acid etching or dry fluorine-based plasma etching.

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