Semiconductor structure and method of fabrication

Abstract

The application relates to the technical field of semiconductors, and provides a semiconductor structure and a preparation method. The semiconductor structure comprises a semiconductor substrate and a plurality of LDMOSs. The plurality of LDMOSs are arranged on the semiconductor substrate, so that the plurality of LDMOSs can share one semiconductor substrate. A corresponding semiconductor substrate does not need to be arranged for each LDMOS, the number of semiconductor substrates is reduced, and the preparation cost of the semiconductor structure is reduced. Effective channel lengths of the plurality of LDMOSs are different, so that the electrical properties of the plurality of LDMOSs are different, and thus the threshold voltage, the drain voltage and the electrical property speed of the plurality of LDMOSs are different. When the electrical property bias experiment is carried out on the semiconductor structure, the plurality of LDMOSs with different channel lengths can match four process angles under different voltage grades in the electrical property bias experiment, the number of semiconductor substrates can be reduced, and the cost can be reduced.

Description

Technical Field

[0001] This application relates to a semiconductor structure and its fabrication method, belonging to the field of semiconductor technology. Background Technology

[0002] In semiconductor manufacturing, electrical biasing experiments are conducted after the initial production rate and reliability verification are passed, and before small-batch production. These experiments verify whether the electrical effects on the semiconductor structure's yield and reliability meet design expectations. Power management chips consist of multiple laterally diffused metal-oxide-semiconductor (LDMOS) modules at different voltage levels. During electrical biasing experiments on power management chips, the process corners in four directions need to be verified for each voltage level of the LDMOS.

[0003] Currently, when conducting electrical biasing experiments on power management chips, it is necessary to fabricate multiple LDMOS chips with different voltage levels. Each LDMOS chip occupies a wafer, resulting in a huge amount of wafer usage. Consequently, the electrical biasing experiment for power management chips is costly and inefficient. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for fabricating the semiconductor structure through multiple embodiments, in order to solve the problems of high cost and low efficiency in electrical biasing experiments.

[0005] One embodiment of this application provides a semiconductor structure, including: a semiconductor substrate; Multiple LDMOS are formed on the surface of the semiconductor substrate; the multiple LDMOS are used for electrical process corner verification; wherein each of the LDMOS includes a channel region; In the plurality of LDMOS, at least two LDMOS have different effective channel lengths in their channel regions to enable testing of different electrical process angles.

[0006] Optionally, the LDMOS includes a drift region, a drain, a gate, and a source. The drift region includes a well region formed within the semiconductor substrate. The gate is located on the surface of the semiconductor substrate, and at least a portion of the gate coincides with the well region along the thickness direction of the semiconductor substrate. Wherein, along the second direction, the length of the portion where the gate and the well region overlap is the effective channel length, and the second direction is perpendicular to the thickness direction of the semiconductor substrate.

[0007] Optionally, along the second direction, the gate lengths of the plurality of LDMOS are consistent, and the well regions of at least a portion of the LDMOS have different lengths.

[0008] Optionally, along the second direction, the well region has a first end and a second end, and the portion of the well region adjacent to the first end coincides with the gate.

[0009] Optionally, the well region is an N-type well region, and the semiconductor structure further includes a shallow trench isolation region and a P-type lightly doped drain region. The shallow trench isolation region is located within the drift region, and the P-type lightly doped drain region is located between the source and the well region.

[0010] Secondly, based on the semiconductor structure described above, this application also provides a method for fabricating a semiconductor structure, comprising: Provide semiconductor substrates; At least two ion implantation processes are performed on the semiconductor substrate to form a plurality of LDMOS within the semiconductor substrate; during the performance of the at least two ion implantation processes, there are at least two ion implantation sites that are different; Each of the LDMOS includes a channel region; among the plurality of LDMOS, at least two LDMOS have different effective channel lengths of their channel regions to enable testing at different electrical process angles.

[0011] Optionally, forming a plurality of LDMOS includes: A plurality of first mask layers are formed, and the plurality of first mask layers are respectively disposed on one side surface of the semiconductor substrate. The first mask layer has a first mask hole extending along the thickness direction of the semiconductor substrate. First ions are implanted into the surface of the semiconductor substrate through the first mask holes of multiple first mask layers to form multiple first layers; Second ions are implanted into the side of the first layer opposite to the semiconductor substrate through the first mask holes of multiple first mask layers to form multiple second layers; Multiple first mask layers are removed and multiple second mask layers are formed. The multiple second mask layers are respectively disposed on one side surface of the semiconductor substrate. The second mask layer has a second mask hole extending along the thickness direction of the semiconductor substrate. At least a portion of the second mask hole is misaligned with the first mask hole along the thickness direction of the semiconductor substrate. Third ions are injected into the second layer through the second mask holes of multiple second mask layers to the side of the second layer opposite to the first layer, forming a third layer; The second mask layer is offset from the corresponding first mask hole, and the multiple offsets are different. The energy of the first ion is greater than the energy of the second ion, and the energy of the second ion is greater than the energy of the third ion.

[0012] Optionally, the second mask aperture is offset relative to the first mask aperture along the thickness direction of the semiconductor substrate.

[0013] Optionally, along the thickness direction of the semiconductor substrate, the first mask hole is located inside the second mask hole, or the second mask hole is located inside the first mask hole.

[0014] Optionally, among the plurality of first mask layers, at least a portion of the first mask layers have a plurality of first mask holes, and the second mask layer corresponding to the first mask layer having a plurality of first mask holes has a plurality of second mask holes; The plurality of first mask holes in the first mask layer are the same, and the plurality of second mask holes in the second mask layer are the same.

[0015] In the semiconductor structure provided in this application, multiple LDMOS transistors are disposed on a semiconductor substrate, allowing them to share a single substrate. The different effective channel lengths of the multiple LDMOS transistors result in different electrical properties, leading to variations in threshold voltage, drain voltage, and electrical velocity. Unexpected benefits include: eliminating the need for a separate semiconductor substrate for each LDMOS transistor, reducing the number of substrates and lowering the fabrication cost of the semiconductor structure. During electrical biasing experiments on the semiconductor structure, the multiple LDMOS transistors with different channel lengths can be matched to the four process corners at multiple voltage levels. This allows for electrical biasing experiments on LDMOS transistors at multiple different voltage levels to be completed using only a single semiconductor substrate. Therefore, the cost of electrical biasing experiments on the semiconductor structure can be reduced, and the electrical biasing efficiency can be improved.

[0016] The semiconductor structure preparation method provided in this application can prepare the above-mentioned semiconductor structure, thereby reducing the preparation cost of the semiconductor structure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of an LDMOS semiconductor structure provided in an embodiment of this application.

[0020] Figure 3 A schematic diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application. Figure 1 .

[0021] Figure 4 A schematic diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application. Figure 2 .

[0022] Figure 5 A schematic diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application. Figure 3 .

[0023] Figure 6 A schematic diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application. Figure 4 .

[0024] Figure 7 A schematic diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application. Figure 5 .

[0025] Figure 8 A schematic diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application. Figure 6 .

[0026] Figure 9 A schematic diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application. Figure 7 .

[0027] Figure 10 A schematic diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application. Figure 8 .

[0028] Figure 11 A schematic diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application. Figure 9 .

[0029] Figure 12 This is a schematic flowchart illustrating the method for fabricating a semiconductor structure according to an embodiment of this application.

[0030] Explanation of reference numerals in the attached figures: 100 - Semiconductor substrate; 200 - LDMOS; 210 - Drift region; 211 - Well region; 212 - P-type drift dual conduction path; 220 - Body region; 230 - Drain; 240 - Gate; 250 - Source; 260 - Shallow trench isolation region; 270 - P-type lightly doped drain region; 300 - First mask layer; 310 - First mask aperture; 400 - Second mask layer; 410 - Second mask aperture; 510 - First layer; 520 - Second layer; 530 - Third layer. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] In semiconductor manufacturing, after the initial production rate and reliability verification are passed, and before small-batch production, electrical biasing experiments are conducted to verify whether the impact of electrical properties on the semiconductor structure's yield and reliability meets design expectations. Power management chips include multiple laterally diffused metal-oxide-semiconductor (LDMOS) modules at different voltage levels. When conducting electrical biasing experiments on power management integrated circuits (PMICs), the process corners in four directions need to be verified for each voltage level of the LDMOS.

[0033] Currently, when conducting electrical biasing experiments on power management chips, it is necessary to fabricate multiple LDMOS chips with different voltage levels. Each LDMOS chip occupies a wafer, resulting in a huge amount of wafer usage. Consequently, the electrical biasing experiment for power management chips is costly and inefficient.

[0034] In the semiconductor structure proposed in this application, multiple LDMOS transistors are disposed on a semiconductor substrate, allowing them to share a single substrate. The different effective channel lengths of the multiple LDMOS transistors result in different electrical properties, leading to variations in threshold voltage, drain voltage, and electrical velocity. Unexpected benefits include: eliminating the need for a separate semiconductor substrate for each LDMOS transistor, reducing the number of substrates and thus lowering the fabrication cost of the semiconductor structure. During electrical biasing experiments on the semiconductor structure, the multiple LDMOS transistors with different channel lengths can be matched to the four process corners at multiple voltage levels. This allows for electrical biasing experiments on LDMOS transistors at multiple different voltage levels to be completed using only a single semiconductor substrate. Therefore, the cost of electrical biasing experiments on the semiconductor structure can be reduced, and the electrical biasing efficiency can be improved.

[0035] The method for preparing the semiconductor structure proposed in this application can prepare the above-mentioned semiconductor structure, thereby reducing the preparation cost of the semiconductor structure.

[0036] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] This application provides a semiconductor structure, with reference to... Figure 1 and Figure 2 As shown, it includes a semiconductor substrate 100 and multiple LDMOS 200s. This semiconductor structure can be applied in power management chips.

[0038] In this embodiment, the semiconductor substrate 100 is the basic component of the semiconductor structure of this application. Specifically, the semiconductor substrate 100 can be a P-type semiconductor, and it can be made of lightly doped silicon. The semiconductor substrate 100 is a core component of the semiconductor structure of this application for achieving high-voltage isolation, optimizing electric field distribution, and ensuring device reliability.

[0039] Multiple LDMOS 200s are disposed on one side surface of the semiconductor substrate 100. Specifically, the multiple LDMOS 200s are disposed on the semiconductor substrate 100 along a first direction, wherein the first direction is the thickness direction of the semiconductor substrate 100. Figure 2 The X-direction is shown in the diagram. Multiple LDMOS 200s are stacked along the thickness direction of the semiconductor substrate 100 on one side of the substrate 100, allowing them to share a single substrate 100. At least a portion of the LDMOS 200s have different effective channel lengths, resulting in different electrical characteristics. For example, when there are three LDMOS 200s, at least two will have different electrical characteristics, leading to differences in threshold voltage, drain voltage, and electrical velocity between them.

[0040] Specifically, when the LDMOS 200 of this application is a laterally double-diffused metal-oxide semiconductor, i.e., when the LDMOS 200 is an LDMOS, the longer the channel of the LDMOS 200, the higher the threshold voltage, the longer the leakage current, and the slower the electrical speed. Conversely, the shorter the channel of the LDMOS 200, the lower the threshold voltage, the shorter the leakage current, and the faster the electrical speed. During the electrical pull-biasing experiment of the semiconductor structure of this application, multiple LDMOS 200s with different channel lengths can be matched to the four process corners at different voltage levels during the electrical pull-biasing experiment, namely FF, FS, SF, and SS. Thus, with only one semiconductor substrate 100, the electrical pull-biasing experiment of the LDMOS 200 at multiple different voltage levels of the semiconductor structure can be completed. This reduces the cost of the electrical pull-biasing experiment of the semiconductor structure of this application and improves the efficiency of the electrical pull-biasing experiment.

[0041] In some implementations, reference Figure 2 As shown, the LDMOS 200 of this application may include a drift region 210, a drain 230, a gate 240, and a source 250. The drift region 210 includes a well region 211. The well region 211 is stacked on the semiconductor substrate 100. The drain 230 is formed in the drift region 210 by ion implantation, the source 250 is formed in the well region 211, and the gate 240 is located on the side of the well region 211 facing away from the semiconductor substrate 100. The well region 211 can be an N-type well region 211. When the N-type well region 211 is stacked on the semiconductor substrate 100, and the semiconductor substrate 100 is a P-type substrate, the N-type well region 211 and the underlying P-type substrate can form a vertical PN junction. By optimizing the doping concentration of the N-type well region 211, the surface electric field of the semiconductor structure of this application can be adjusted.

[0042] Along the thickness direction of the semiconductor substrate 100, at least a portion of the gate 240 overlaps with the well region 211. The well region 211 is located below the gate 240, and the gate 240 covers at least a portion of the well region 211. The portion of the well region 211 covered by the gate 240 can form a channel. Accordingly, the effective channel length is determined by the size of the portion of the well region 211 that overlaps with the gate 240. The effective channel length is... Figure 2 The length represented by line segment D in the middle.

[0043] Specifically, along the second direction, the length of the portion where the gate 240 overlaps with the well region 211 is the effective channel length. The second direction is perpendicular to the first direction, meaning it is parallel to one side of the semiconductor substrate 100 along its thickness direction. Figure 2The effective channel length is determined by the length of the portion of the well region 211 overlapping with the gate 240 in the second direction. Conversely, the effective channel length is determined by the length of the portion of the well region 211 overlapping with the gate 240 in the second direction. Therefore, by adjusting the length of the portion of the well region 211 overlapping with the gate 240 in the second direction of each LDMOS 200, the effective channel length of each LDMOS 200 can be adjusted accordingly.

[0044] In some implementations, reference Figure 1 As shown, the plurality of LDMOS 200s of this application can be distributed on the semiconductor substrate 100 along the second direction and the third direction. The third direction is perpendicular to both the first and second directions, and the third direction is... Figure 1 and Figure 2 The Z direction in the equation.

[0045] Specifically, multiple LDMOS 200s can be arranged in a rectangular array on the semiconductor substrate 100 to fully utilize the space on one side surface of the semiconductor substrate 100 in the first direction, thereby increasing the number of LDMOS 200s that can be disposed on the semiconductor substrate 100. This allows for more thorough electrical biasing experiments on the semiconductor structure of this application and further reduces experimental costs.

[0046] In some implementations, along the second direction, reference Figure 2 As shown, the gate 240 of the plurality of LDMOS 200s in this application has the same length, while the well region 211 of at least a portion of the LDMOS 200s has a different length. Specifically, among the plurality of LDMOS 200s, the well region 211 of a portion of the LDMOS 200s has a longer length in the second direction, while the well region 211 of a portion of the LDMOS 200s has a shorter length in the second direction. The portion of the relatively longer well region 211 overlapping with the corresponding gate 240 can be set to have a relatively longer length in the second direction, while the portion of the relatively shorter well region 211 overlapping with the corresponding gate 240 has a relatively shorter length in the second direction. Thus, by adjusting the length of the well region 211 of each LDMOS 200 in the second direction, the channel length of each LDMOS 200 can be adjusted accordingly, and ultimately the electrical properties of each LDMOS 200 can be adjusted.

[0047] In some implementations, reference Figure 2 As shown, along the second direction, the well regions 211 of the plurality of LDMOS 200s in this application each have a first end and a second end. The portion of the well region 211 adjacent to its first end coincides with the gate 240 to form a channel. Correspondingly, the portion of the well region 211 adjacent to its second end may be misaligned with the gate 240.

[0048] In order to make the effective channel lengths of the various LDMOS 200s in this application different, along the second direction, the second end of the well region 211 of at least a portion of the LDMOS 200s has the same or different spacing from the corresponding gate 240.

[0049] Specifically, when the second end of the well region 211 of multiple LDMOS 200s is the same as the corresponding gate spacing, when the well region 211 is formed by ion implantation, the length of the well region 211 in the second direction can be adjusted by controlling the diffusion degree of ions in the direction from the second end to the first end, thereby adjusting the length of the part of the well region 211 that overlaps with the gate 240 in the second direction, and finally adjusting the effective channel length of the LDMOS 200.

[0050] When the spacing between the first and second ends of the well regions 211 of at least a portion of the LDMOS 200 is different, then when the well regions 211 are formed by ion implantation, the diffusion degree of ions in the direction from the second end to the first end and the diffusion degree of ions in the direction from the first end to the second end can be controlled to make the well regions 211 expand or contract in the second direction and in the opposite direction of the second direction, thereby adjusting the length of the portion of the well regions 211 that overlaps with the gate 240 in the second direction, and finally adjusting the effective channel length of the LDMOS 200.

[0051] In some implementations, reference Figure 2 As shown, the semiconductor structure of this application also includes a body region 220, a shallow trench isolation region 260, a lightly doped P-type drain region 270, and a barrier layer 280. The body region 220 is disposed within the drift region 210, the shallow trench isolation region 260 is located within the drift region 210, the lightly doped P-type drain region 270 is located between the source 250 and the well region 211, and the barrier layer 280 is stacked on the side of the drift region 210 facing away from the semiconductor substrate 100. The shallow trench isolation region 260 is a silicon dioxide-filled trench within the drift region 210, used for device isolation and electric field modulation. The lightly doped P-type drain region 270 can enhance the vertical depletion effect, allowing the N-type doping concentration within the drift region 210 to increase by 50%, significantly reducing resistance.

[0052] The barrier layer 280 has insulating properties, which force the depletion layer of the drift region 210 to extend longitudinally and form a RESURF (reduced surface field) effect with the semiconductor substrate 100, making the electric field distribution more uniform and avoiding local avalanche breakdown at the drain end.

[0053] Based on the semiconductor structure described above, this application also proposes a method for fabricating the semiconductor structure described above, referring to... Figure 2 and Figure 12As shown, the preparation method includes steps S100 and S200.

[0054] S100 provides a semiconductor substrate, wherein the thickness direction of the semiconductor substrate is a first direction.

[0055] The semiconductor substrate 100 is the fundamental component of the semiconductor structure of this application. Specifically, the semiconductor substrate 100 can be a P-type semiconductor, and it can be made of lightly doped silicon. The semiconductor substrate 100 is a core component of the semiconductor structure of this application for achieving high-voltage isolation, optimizing electric field distribution, and ensuring device reliability.

[0056] S200, performing at least two ion implantation processes on a semiconductor substrate to form multiple LDMOS within the semiconductor substrate; during the performance of at least two ion implantation processes, there are at least two ion implantation sites that are different.

[0057] S300, based on each well region, forms multiple LDMOS; wherein, each LDMOS includes a well region; within the well region, an active region, a drain region, and a channel region between the source and drain regions are formed.

[0058] Each LDMOS includes a channel region; among multiple LDMOS, at least two LDMOS have different effective channel lengths in their channel regions to enable testing of different electrical process angles.

[0059] Multiple LDMOS 200s are stacked along the thickness direction of the semiconductor substrate 100 on one side of the semiconductor substrate 100, allowing the multiple LDMOS 200s to share a single semiconductor substrate 100. At least a portion of the multiple LDMOS 200s have different effective channel lengths, resulting in different electrical characteristics among at least a portion of the LDMOS 200s. For example, when there are three LDMOS 200s, at least two LDMOS 200s have different electrical characteristics, thereby resulting in different threshold voltages, drain voltages, and electrical speeds among at least two LDMOS 200s.

[0060] Specifically, when the LDMOS 200 of this application is a laterally double-diffused metal-oxide semiconductor, i.e., when the LDMOS 200 is an LDMOS, the longer the channel of the LDMOS 200, the higher the threshold voltage, the longer the leakage current, and the slower the electrical speed. Conversely, the shorter the channel of the LDMOS 200, the lower the threshold voltage, the shorter the leakage current, and the faster the electrical speed. During the electrical pull-biasing experiment of the semiconductor structure of this application, multiple LDMOS 200s with different channel lengths can be matched to the four process corners at different voltage levels in the electrical pull-biasing experiment. Thus, with only one semiconductor substrate 100, the electrical pull-biasing experiment of the LDMOS 200 at multiple different voltage levels of the semiconductor structure can be completed. Therefore, when fabricating the semiconductor structure of this application, the number of semiconductor substrates 100 can be reduced, thereby lowering the fabrication cost of the semiconductor structure. Correspondingly, the cost of conducting electrical biasing experiments on semiconductor devices prepared by the semiconductor structure preparation method of this application can be reduced, and the efficiency of electrical biasing experiments can be improved.

[0061] In some embodiments, references are made to this application. Figures 3 to 11 As shown, the LDMOS 200 is formed through the following steps: S210, a first mask layer 300 is formed. The first mask layer 300 is disposed on the semiconductor substrate 100 along a first direction. The first mask layer 300 has a first mask hole 310 that extends along the first direction.

[0062] The first mask layer 300 can be a photoresist. The photoresist material of the first mask layer 300 can be formed on one side of the semiconductor substrate 100 in the thickness direction by spin coating, and the first mask hole 310 is formed by photolithography. The first mask hole 310 penetrates the first mask layer 300, so that the first mask layer 300 covers part of the surface of the semiconductor substrate 100 on the first direction side, and the part of the semiconductor substrate 100 on the first direction side side corresponding to the first mask hole 310 is exposed.

[0063] S220, high-energy ions are injected into the surface of the semiconductor substrate 100 through the first mask hole 310 to form the first layer 510.

[0064] It should be understood that the well region 211 in the LDMOS is formed by three ion implantations. The first implantation is the implantation of high-energy ions into the surface of the semiconductor substrate 100 through the first mask hole 310. The first layer 510 formed is stacked on one side surface of the semiconductor substrate 100 in the first direction, such that the first layer 510 is located in the bottom region of the well region 211 in the first direction.

[0065] S230, second ions are injected into the side of the first layer 510 facing away from the semiconductor substrate 100 through the first mask hole 310 to form the second layer 520.

[0066] The second ion is implanted into the surface of the semiconductor substrate 100 through the first mask hole 310, which is called the second implantation, so that the second layer 520 is located in the middle region of the well region 211 in the first direction.

[0067] S240, the first mask layer 300 is removed, and a second mask layer 400 is formed. The second mask layer 400 is disposed on the semiconductor substrate 100 along a first direction, and the second mask layer 400 has a second mask hole 410 that extends along the first direction. Along the first direction, at least a portion of the second mask hole 410 is misaligned with the first mask hole 310.

[0068] The second mask layer 400 can be a photoresist. The photoresist material of the second mask layer 400 can be formed on one side of the semiconductor substrate 100 in the thickness direction by spin coating, and a second mask hole 410 is formed by photolithography. The second mask hole 410 penetrates the second mask layer 400, so that the second mask layer 400 covers a portion of the semiconductor substrate 100 on the surface of the semiconductor substrate 100 on the surface of the semiconductor substrate 100 on the surface of the semiconductor substrate 100 in the first direction, and the portion of the semiconductor substrate 100 on the surface of the semiconductor substrate 100 on the surface of the semiconductor substrate 100 in the first direction corresponding to the second mask hole 410 is exposed.

[0069] S250, third ions are injected into the second layer 520 on the side opposite to the first layer 510 through the second mask hole 410 to form the third layer 530.

[0070] The third ion is implanted into the surface of the semiconductor substrate 100 through the second mask hole 410, which is called the third implantation, so that the third layer 530 is located in the top region of the well region 211 in the first direction. Since the energy of the third implanted ion is low, the implanted ion remains in the shallow region, that is, at the top of the well region 211 in the first direction, which can determine the diffusion degree of the well region 211 in the second direction.

[0071] Because the second mask aperture 410 is misaligned with the first mask aperture 310 in the first direction, the third layer 530 is also misaligned relative to the first layer 510 and the second layer 520 in the first direction. This allows the relative positions of the third layer 530 with the first layer 510 and the second layer 520 to be changed. When the relative positions of the gate 240 of the semiconductor structure with the first layer 510 and the second layer 520 remain unchanged, by adjusting the degree of misalignment between the second mask aperture 410 and the first mask aperture 310, the relative positions of the third layer 530 and the gate 240 can be adjusted accordingly, thereby controlling the diffusion degree of the well region 211 in the direction from the second end to the first end. This allows adjustment of the length of the portion of the well region 211 overlapping the gate 240 in the second direction, thereby adjusting the effective channel length of the LDMOS 200.

[0072] In forming multiple LDMOS 200s, each LDMOS 200 can be fabricated according to the above method, and the second mask aperture 410 of the second mask layer 400 used in the formation of at least a portion of the LDMOS 200s differs in the degree of misalignment with the corresponding first mask aperture 310. This results in different diffusion degrees of each well region 211 in the direction from the second end to the first end, allowing adjustment of the length of the portion of each well region 211 overlapping with the corresponding gate 240 in the second direction, thereby adjusting the effective channel length of the LDMOS 200 accordingly.

[0073] In some implementations, reference Figure 5 and Figure 7 As shown, in order to at least partially misalign the first mask aperture 310 and the second mask aperture 410, the second mask aperture 410 is offset relative to the first mask aperture 310 along a first direction. This allows the second mask aperture 410 to be misaligned relative to the first mask aperture 310, such that a portion of the second mask aperture 410 is opposite to the first mask aperture 310, while another portion of the second mask aperture 410 is misaligned with the first mask aperture 310.

[0074] In some implementations, reference Figure 5 and Figure 10 As shown, in order to make the first mask hole 310 and the second mask hole 410 at least partially misaligned, along the second direction, the first mask hole 310 is located inside the second mask hole 410, or the second mask hole 410 is located inside the first mask hole 310.

[0075] Specifically, if the first mask hole 310 and the second mask hole 410 are circular holes, their inner diameters can be set to be different, such that the first mask hole 310 can completely cover the second mask hole 410, or the second mask hole 410 can completely cover the first mask hole 310. This difference in the diffusion of the third layer 530 along the second direction results in different channel lengths for the multiple LDMOS 200s.

[0076] If the first mask aperture 310 and the second mask aperture 410 are rectangular apertures, at least one of the length and width of the first mask aperture 310 and the second mask aperture 410 can be set differently, such that the first mask aperture 310 can completely cover the second mask aperture 410, or the second mask aperture 410 can completely cover the first mask aperture 310. This difference in the diffusion of the third layer 530 along the second direction results in different channel lengths for the multiple LDMOS 200s.

[0077] Therefore, after forming the third layer 530 through a third ion implantation, a complete structure of the well region 211 can be formed. The well regions 211 of different LDMOS 200 diffuse outward at different distances on both sides in the second direction, so that the channel lengths of the multiple LDMOS 200s are different.

[0078] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0079] Generally speaking, terms should be understood at least in part by their use in context. For example, at least in part by context, the term "one or more" as used in the text can be used to describe any feature, structure, or characteristic of the singular meaning, or a combination of features, structures, or characteristics of the plural meaning. Similarly, at least in part by context, terms such as "a" or "the" can also be understood to convey either singular or plural usage.

[0080] It should be readily understood that the terms “on,” “above,” and “on top of” in this application should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “on something” but also “on something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0081] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90° or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate; Multiple LDMOS formed on the surface of the semiconductor substrate; The plurality of LDMOS are used for electrical process corner verification; wherein each of the LDMOS includes a channel region; In the plurality of LDMOS, at least two LDMOS have different effective channel lengths in their channel regions to enable testing of different electrical process angles; The plurality of said LDMOS are formed by the following method: A plurality of first mask layers are formed, and the plurality of first mask layers are respectively disposed on one side surface of the semiconductor substrate. The first mask layer has a first mask hole extending along the thickness direction of the semiconductor substrate. First ions are implanted into the surface of the semiconductor substrate through the first mask holes of multiple first mask layers to form multiple first layers; Second ions are implanted into the side of the first layer opposite to the semiconductor substrate through the first mask holes of multiple first mask layers to form multiple second layers; Multiple first mask layers are removed and multiple second mask layers are formed. The multiple second mask layers are respectively disposed on one side surface of the semiconductor substrate. The second mask layer has a second mask hole extending along the thickness direction of the semiconductor substrate. At least a portion of the second mask hole is misaligned with the first mask hole along the thickness direction of the semiconductor substrate. Third ions are injected into the second layer through the second mask holes of multiple second mask layers to the side of the second layer opposite to the first layer, forming a third layer; The second mask layer is offset from the corresponding first mask hole, and the multiple offsets are different. The energy of the first ion is greater than the energy of the second ion, and the energy of the second ion is greater than the energy of the third ion.

2. The semiconductor structure according to claim 1, characterized in that, The LDMOS includes a drift region, a drain, a gate, and a source. The drift region includes a well region formed within the semiconductor substrate. The gate is located on the surface of the semiconductor substrate, and at least a portion of the gate coincides with the well region along the thickness direction of the semiconductor substrate. Wherein, along the second direction, the length of the portion where the gate and the well region overlap is the effective channel length, and the second direction is perpendicular to the thickness direction of the semiconductor substrate.

3. The semiconductor structure according to claim 2, characterized in that, Along the second direction, the gate lengths of the plurality of LDMOS are consistent, and the well regions of at least a portion of the LDMOS have different lengths.

4. The semiconductor structure according to claim 3, characterized in that, Along the second direction, the well region has a first end and a second end, and the portion of the well region adjacent to the first end coincides with the gate.

5. The semiconductor structure according to any one of claims 2-4, characterized in that, The well region is an N-type well region. The semiconductor structure also includes a shallow trench isolation region and a P-type lightly doped drain region. The shallow trench isolation region is located within the drift region, and the P-type lightly doped drain region is located between the source and the well region.

6. A method for fabricating a semiconductor structure, characterized in that, include: Provide semiconductor substrates; Multiple LDMOS are formed within the semiconductor substrate; The formation of multiple LDMOS within the semiconductor substrate includes: A plurality of first mask layers are formed, and the plurality of first mask layers are respectively disposed on one side surface of the semiconductor substrate. The first mask layer has a first mask hole extending along the thickness direction of the semiconductor substrate. First ions are implanted into the surface of the semiconductor substrate through the first mask holes of multiple first mask layers to form multiple first layers; Second ions are implanted into the side of the first layer opposite to the semiconductor substrate through the first mask holes of multiple first mask layers to form multiple second layers; Multiple first mask layers are removed and multiple second mask layers are formed. The multiple second mask layers are respectively disposed on one side surface of the semiconductor substrate. The second mask layer has a second mask hole extending along the thickness direction of the semiconductor substrate. At least a portion of the second mask hole is misaligned with the first mask hole along the thickness direction of the semiconductor substrate. Third ions are injected into the second layer through the second mask holes of multiple second mask layers to the side of the second layer opposite to the first layer, forming a third layer; The second mask layer is offset from the corresponding first mask hole, and the multiple offsets are different. The energy of the first ion is greater than the energy of the second ion, and the energy of the second ion is greater than the energy of the third ion. Each of the LDMOS includes a channel region; among the plurality of LDMOS, at least two LDMOS have different effective channel lengths of their channel regions to enable testing of different electrical process angles.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, Along the thickness direction of the semiconductor substrate, the second mask aperture is offset relative to the first mask aperture.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that, Along the thickness direction of the semiconductor substrate, the first mask hole is located inside the second mask hole, or the second mask hole is located inside the first mask hole.

9. The method for preparing a semiconductor structure according to any one of claims 6-8, characterized in that, In a plurality of first mask layers, at least a portion of the first mask layers have a plurality of first mask holes, and the second mask layer corresponding to the first mask layer having a plurality of first mask holes has a plurality of second mask holes; The plurality of first mask holes in the first mask layer are the same, and the plurality of second mask holes in the second mask layer are the same.

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