Back contact cell and method of manufacturing, manufacturing apparatus and photovoltaic module thereof

Abstract

The application belongs to the technical field of solar cells, and particularly relates to a back contact cell, a preparation method and a preparation device thereof, and a photovoltaic module, which can reduce the risk of leakage, wherein the preparation method of the back contact cell comprises the following steps: providing a semiconductor substrate, the semiconductor substrate comprises a first surface and a second surface arranged oppositely, the first surface comprises a first region, a second region and a third region, the third region is located between the first region and the second region, and the first region comprises a first sub-region and a second sub-region; forming a first doped layer on the first region and the third region of the first surface; depositing a mask layer on the first surface; and removing the first doped layer of the third region and the second sub-region at least partially by using a laser.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a back contact cell, its preparation method, preparation equipment, and photovoltaic module. Background Technology

[0002] Photovoltaic modules are mainly composed of photovoltaic cells, photovoltaic glass, encapsulating film, backsheet, and frame.

[0003] Back-contact solar cells, as a type of photovoltaic cell, reduce the shading of light by grid lines by placing both the positive and negative electrodes on the back side of the cell, thereby increasing the light-receiving area and improving its performance. Summary of the Invention

[0004] Based on this, it is necessary to propose a back-contact battery that can reduce the risk of leakage, and also to propose a method for preparing the back-contact battery, preparation equipment, and photovoltaic module.

[0005] The first aspect of this application discloses a method for fabricating a back-contact battery. The method includes: providing a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, the first surface including a first region, a second region and a third region, the third region being located between the first region and the second region, and the first region including a first sub-region and a second sub-region; forming a first doped stack on the first region and the third region of the first surface; depositing a mask layer on the first surface; and using a laser to at least partially remove the first doped stack in the third region and the second sub-region.

[0006] In some embodiments, the mask layer is an aluminum oxide layer.

[0007] In some embodiments, an aluminum oxide layer is simultaneously formed on the second surface while a mask layer is deposited on the first surface.

[0008] In some embodiments, a laser is used to at least partially remove the first doped stack in the third region and the second sub-region, and a second doped stack is formed in the second sub-region and the third region; the thickness D1 of the first doped stack satisfies 50nm < D1 ≤ 250nm, and / or the thickness D2 of the second doped stack satisfies D2 ≤ 50nm.

[0009] In some embodiments, forming a first doped stack in a first region and a third region of the first surface includes: forming a tunneling layer and a doped silicon layer on the first surface; depositing a barrier layer; removing the tunneling layer, the doped silicon layer, and the barrier layer in the second region; and removing the barrier layer in the first region and the third region.

[0010] In some embodiments, using a laser to at least partially remove the first doped stack of the third region and the second sub-region includes: alternating between a first pulsed laser and a second pulsed laser, wherein the frequency of the first pulsed laser is less than the frequency of the second pulsed laser.

[0011] In some embodiments, the single-shot duration of the first pulsed laser is 1 to 5 times that of the single-shot duration of the second pulsed laser.

[0012] In some embodiments, the frequency of the first pulsed laser is 200-500 Hz; the frequency of the second pulsed laser is 700-1500 Hz.

[0013] In some embodiments, the method further includes: wet chemical cleaning to remove the mask layer on the first surface; depositing a passivation layer and a doped layer on the first surface; removing the passivation layer and the doped layer in the first region; depositing a conductive film on the first surface; removing a portion of the conductive film in the third region to form an isolation region; and forming electrodes in the first sub-region and the second region, respectively.

[0014] A second aspect of this application provides an apparatus for fabricating a back-contact battery, comprising: a film deposition apparatus for depositing a first doped stack on the surface of a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, the first surface including a first region, a second region and a third region, the third region being located between the first region and the second region, the first region including a first sub-region and a second sub-region, the first region and the third region of the first surface forming the first doped stack; and a laser etching apparatus for removing at least partially the first doped stack of the third region and the second sub-region using a laser.

[0015] In a third aspect, this application proposes a back contact battery, which is obtained by the aforementioned method for preparing a back contact battery.

[0016] In a fourth aspect, this application provides a photovoltaic module, including a cover plate; at least one battery string, the battery string including back contact batteries obtained by the above-described back contact battery preparation method; and a back plate, which is located on both sides of the battery string, respectively, as described above.

[0017] In this application, the first doped stack in the third region and the second sub-region is at least partially removed. This results in a thinner doped layer in the second and third regions, which suppresses the lateral diffusion of the doped layer and prevents it from extending into other structural layers and causing excessive contact. This leads to a lower leakage risk in the back contact battery and reduces parasitic absorption in the second sub-region, improving the bifaciality of the back contact battery and thus increasing its power generation. Furthermore, this application uses laser removal of the first doped stack in the third and second sub-regions, resulting in a simple and low-cost process. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a back contact battery according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the structure of a back contact battery according to another embodiment of this application.

[0020] Figure 3 This is a schematic flowchart of a back contact battery preparation method according to an embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the structure after preparation method S20 of this application.

[0022] Figure 5 This is a schematic diagram of the structure after preparation method S30 of this application.

[0023] Figure 6 This is a schematic diagram of the structure after preparation method S40 of this application.

[0024] Figure 7 This is a schematic diagram of another structure after preparation method S40 of this application.

[0025] Figure 8 for Figure 1 A schematic diagram of the back contact battery after S21.

[0026] Figure 9 for Figure 1 A schematic diagram of the back contact battery structure after S22.

[0027] Figure 10 for Figure 1 A schematic diagram of the back contact battery structure after S51.

[0028] Figure 11 for Figure 1 A schematic diagram of the back contact battery structure after S52.

[0029] Figure 12 for Figure 1 A schematic diagram of the back contact battery structure after S53.

[0030] Figure 13 for Figure 1 A schematic diagram of the back contact battery structure after S54.

[0031] Figure 14 for Figure 1 A schematic diagram of the back contact battery structure in the S55.

[0032] Figure label:

[0033] 100. Back contact battery; 10. Semiconductor substrate; 101. First surface; 102. Second surface; 1021. Passivation structure; 1022. Antireflection layer; S1. First region; S11. First sub-region; S12. Second sub-region; S2. Second region; S3. Third region; 103. Substrate doped layer; 20. First doped stack; 210. Tunneling layer; 220. Doped silicon layer; 230. Mask layer; 240. Barrier layer; 30. Second doped stack; 40. Passivation layer; 50. Doped layer; 60. Conductive film; 610. Isolation region; 70. Electrode. Detailed Implementation

[0034] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0036] In this application, when numerical intervals (i.e., numerical ranges) are involved, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, etc.

[0037] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by one of ordinary skill in the art.

[0038] Additionally, unless the context otherwise indicates, the material removal described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, abrasive planarization (e.g., chemical mechanical planarization (CMP)) or other known methods.

[0039] As used herein, the term "semiconductor" can refer to, for example, a material layer, substrate, wafer, or substructure, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon sapphire (SOS) technology, silicon-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art.

[0040] In the accompanying drawings, the thicknesses of layers, films, regions, substrates, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals refer to the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0041] Firstly, reference Figures 1 to 6 As shown in the embodiment of this application, a method for preparing a back contact battery 100 is provided, the method comprising:

[0042] S10. A semiconductor substrate 10 is provided, the semiconductor substrate 10 including a first surface 101 and a second surface 102 disposed opposite to each other, the first surface 101 including a first region S1, a second region S2 and a third region S3. The third region S3 is located between the first region S1 and the second region S2, and the first region S1 includes a first sub-region S11 and a second sub-region S12.

[0043] S20, a first doped stack 20 is formed on the first region S1 and the third region S3 of the first surface 101.

[0044] S30, deposit mask layer 230 on the first surface 101.

[0045] S40, using a laser to at least partially remove the first doped stack 20 of the third region S3 and the second sub-region S12.

[0046] The semiconductor substrate 10 may be, for example, silicon, germanium, germanium-silicon, or silicon on an insulator, and various doped silicon materials, including, but not limited to, boron-doped, phosphorus-doped, gallium-doped, antimony-doped, or mixed-doped silicon. The material of the semiconductor substrate 10 may include, for example, at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0047] The first region S1 can be an N-type doped region, and the second region S2 can be a P-type doped region, or vice versa. In S40, the first doped stack 20 of the third region S3 and the second sub-region S12 can be partially removed. In this case, a second doped stack 30 is formed on the third region S3 and the second sub-region S12, and a first doped stack 20 is formed on the first sub-region S11, as shown below. Figure 1 As shown. The first doped stack 20 in the third region S3 and the second sub-region S12 can be completely removed. In this case, there is no doped stack in the third region S3 and the second sub-region S12, and the first doped stack 20 is formed in the first sub-region S11, as shown. Figure 2 , Figure 7 As shown.

[0048] In this application, the first doped stack 20 on the first sub-region S11 is used for electrical contact with the electrode 70. The first doped stack 20 in the third region S3 and the second sub-region S12 is at least partially removed, resulting in thinner doped layers in the second sub-region S12 and the third region S3. This suppresses the lateral (parallel to the first surface 101) diffusion of the doped layers in the second sub-region S12 and the third region S3, preventing them from extending to other structural layers and causing excessive contact. This results in a lower leakage risk for the back contact battery 100 and reduces parasitic absorption in the second sub-region S12, increasing the bifaciality of the back contact battery 100 and thus improving its power generation. Furthermore, in this application, laser removal of the first doped stack 20 in the third region S3 and the second sub-region S12 is employed, resulting in a simple and low-cost process.

[0049] In some embodiments, the mask layer 230 is an aluminum oxide layer. In some embodiments, while the mask layer 230 is deposited on the first surface 101, an aluminum oxide layer is simultaneously formed on the second surface 102.

[0050] A passivation structure 1021 is formed on the second surface 102 of the back contact battery 100. Aluminum oxide is a commonly used material for the passivation structure 1021. Therefore, in this application, the mask layer 230 is an aluminum oxide layer, allowing aluminum oxide layers to be formed simultaneously on both the first surface 101 and the second surface 102. The aluminum oxide layer on the first surface 101 serves as the mask layer 230 for removing the first doped stack 20 of the third region S3 and the second sub-region S12. The aluminum oxide layer on the second surface 102 can then be used as the passivation structure 1021, on which an antireflection layer 1022 can be further disposed. The material of the antireflection layer 1022 is, for example, silicon nitride, silicon oxide, or silicon oxynitride.

[0051] In some embodiments, a second doped stack 30 is formed in the second sub-region S12 and the third region S3 by using a laser to at least partially remove the first doped stack 20 of the third doped stack S3 and the third sub-region S12; the thickness D1 of the first doped stack 20 satisfies 50nm < D1 ≤ 250nm, and / or the thickness D2 of the second doped stack 30 satisfies D2 ≤ 50nm.

[0052] In the thickness direction of the semiconductor substrate 10, a portion of the thickness of the first doped stack 20 on the third region S3 and the second sub-region S12 is removed using a laser, and the remaining first doped stack 20 on the third region S3 and the second sub-region S12 forms a second doped stack 30. The first doped stack 20 and the second doped stack 30 are N-type doped layers, and the dopant can be, for example, phosphorus, arsenic, antimony, etc. The first doped stack 20 and the second doped stack 30 can be, for example, a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, or a doped amorphous silicon layer.

[0053] In this embodiment, the thickness D1 of the first doped stack 20 can be 60nm, 100nm, 150nm, 200nm, 250nm, etc., to reduce the series resistance of the first doped stack 20, improve the photoelectric conversion efficiency of the back contact cell 100, and avoid increased carrier transport loss due to excessive thickness of the first doped stack 20. Meanwhile, the thickness D2 of the second doped stack 30 can be 5nm, 20nm, 30nm, 40nm, 50nm, etc., to reduce parasitic absorption of the second doped stack 30, improve the bifaciality of the back contact cell 100, and avoid excessively low carrier collection efficiency due to excessively thin thickness of the second doped stack 30.

[0054] In other embodiments, the thickness D1 of the first doped stack 20 and the thickness D2 of the second doped stack 30 may also be other values. In this application embodiment, the specific values ​​of the thickness of the first doped stack 20 and the thickness of the second doped stack 30 are not limited, and can be adjusted adaptively according to the actual situation.

[0055] In the above embodiments, the doping concentration W1 of the first doped stack 20 can satisfy 1E19cm. -3 ≤W1≤1E20cm -3 And / or, the doping concentration W2 of the second doped stack 30 can satisfy 1E20cm -3 <W2≤5E20cm -3 .

[0056] For example, the doping concentration of the first doped stack 20 can be 1E19cm. -3 3E19cm -3 5E19cm -3 7E19cm -3 1E20cm -3 The doping concentration of the second doped stack 30 can be 2E20cm. -3 3E20cm -3 4E20cm -3 5E20cm -3 The doping concentration of the first doped stack 20 is greater than that of the second doped stack 30, thereby improving the fill factor and open-circuit voltage of the first sub-region S11 and reducing the parasitic absorption and leakage risk of the overlapping region in the second sub-region S12, significantly improving the working performance of the 100 back contact cells.

[0057] refer to Figure 1 , Figure 8 and Figure 9 In some embodiments, S20 includes:

[0058] S21, A tunneling layer 210 and a doped silicon layer 220 are formed on the first surface 101.

[0059] S22, Deposition barrier layer 240;

[0060] S23, remove the tunneling layer 210, the doped silicon layer 220, and the barrier layer 240 of the second region S2, and remove the barrier layer 240 of the first region S1 and the third region S3.

[0061] The barrier layer 240 is made of, for example, SiOx / SiNx. The first doped stack 20 includes a tunneling layer 210 and a doped silicon layer 220 sequentially disposed on the first surface 101 along a direction away from the semiconductor substrate 10. Figure 1 As shown, during the formation of the first doped stack 20, a substrate doped layer 103 is also formed within the first surface 101. The substrate doped layer 103 and the semiconductor substrate 10 form a PN structure, creating an internal electric field to separate photogenerated carriers. Optionally, the tunneling layer 210 is made of silicon oxide.

[0062] In this application, a tunneling layer 210 and a doped silicon layer 220 are first formed on the first surface 101. Then, using a barrier layer 240 as a mask, the tunneling layer 210, the doped silicon layer 220, and the barrier layer 240 in the second region S2 are removed, as are the barrier layers 240 in the first region S1 and the third region S3. Optionally, wet chemical cleaning can be used to remove the tunneling layer, the doped silicon layer 220, and the barrier layer 240.

[0063] In some embodiments, S40 includes: alternating operation of a first pulse laser and a second pulse laser, wherein the frequency of the first pulse laser is less than the frequency of the second pulse laser.

[0064] The first pulse laser is a narrow pulse laser, and the second pulse laser is a wide pulse laser. The wide pulse laser ensures the etching depth, while the narrow pulse laser has high instantaneous energy, causing less damage to the semiconductor substrate 10 and preserving the original microstructure. In this way, by alternating between the first and second pulse lasers, the etching depth is ensured, the material is effectively removed, the damage to the semiconductor substrate 10 is minimized, and the original microstructure is preserved.

[0065] Furthermore, the single-shot duration of the first pulse laser is 1 to 5 times that of the second pulse laser. For example, the single-shot duration of the first pulse laser is 1, 2, 3, 4, or 5 times that of the second pulse laser.

[0066] With this setup, the first pulse laser plays a role multiple times during the etching process, and the total working time of the first pulse laser can be greater than that of the second pulse laser, resulting in less damage to the semiconductor substrate 10 and preserving the original microstructure.

[0067] Furthermore, the frequency of the first pulse laser is 200-500 Hz; the frequency of the second pulse laser is 700-1500 Hz.

[0068] In this embodiment, the first pulse laser is 200 Hz, 300 Hz, 400 Hz, or 500 Hz. The second pulse laser is 700 Hz, 800 Hz, 1000 Hz, 1200 Hz, 1400 Hz, or 1500 Hz. The laser wavelength can be, for example, 325 or 532 nm, the spot size is 100-300 μm, and the overlap rate is 0-70%.

[0069] In some embodiments, reference Figure 1 , Figure 6 , Figures 10 to 14 The method for preparing the back contact battery 100 of this application further includes the following steps:

[0070] S51, Wet chemical cleaning removes the mask layer 230 on the first surface 101.

[0071] S52, deposit a passivation layer 40 and a doped layer 50 on the first surface 101.

[0072] S53, Remove the passivation layer 40 and doped layer 50 from the first region S1.

[0073] S54. Deposit a conductive film 60 on the first surface 101.

[0074] S55. Remove part of the conductive film 60 in the third region S3 to form an isolation region 610.

[0075] S56, electrodes 70 are formed in the first sub-region S11 and the second region S2 respectively.

[0076] The passivation layer 40 is, for example, an a-Si:H(i) passivation layer. The doped layer 50 is, for example, an a-Si:H(p) doped layer. The conductive film 60 can be, for example, a single-layer or multilayer film made of materials such as ITO, IWO, ITiO, SnOx, or AZO.

[0077] In this embodiment, the above steps are used to prepare a complete back contact battery 100. A second aspect of this application also provides an apparatus for preparing the back contact battery 100, including a film deposition apparatus and a laser etching apparatus.

[0078] Among them, the film deposition device is used to... Figure 1 A first doped stack 20 is formed in the first region S1 and the third region S3 of the semiconductor substrate 10. The laser etching apparatus uses a laser to at least partially remove the first doped stack 20 from the third region S3 and the second sub-region S12.

[0079] Using the fabrication equipment (not shown) of the back contact battery 100 in this embodiment, a fabrication method for the back contact battery 100 can be implemented to obtain a back contact battery 100 with reduced parasitic absorption in the second sub-region S12 and high bifaciality, thereby increasing the power generation of the back contact battery 100. Furthermore, in this application, laser removal of the first doped stack 20 in the third region S3 and the second sub-region S12 is employed, resulting in a simple and low-cost process.

[0080] A third aspect of this application also proposes a back contact battery 100, which can be obtained by the aforementioned method for preparing a back contact battery 100. The second sub-region S12 of the back contact battery 100 exhibits low parasitic absorption and high bifaciality.

[0081] A fourth aspect of this application also provides a photovoltaic module (not shown), comprising a cover plate, at least one cell string, and a backsheet. The cell string includes back-contact cells 100 prepared by the method described in the above embodiments. The backsheet and the cover plate are located on opposite sides of the cell string. Further, a first encapsulating film is provided between the cover plate and the cell string, and a second encapsulating film is provided between the backsheet and the cell string.

[0082] The back contact battery obtained by using the preparation method of the above embodiments can improve the working performance of the back contact battery cell, increase power generation, and improve the working efficiency of the photovoltaic module.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for preparing a back-contact battery, characterized in that, The method for preparing the back contact battery includes: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, the first surface including a first region, a second region and a third region, the third region being located between the first region and the second region, and the first region including a first sub-region and a second sub-region. A first doped stack is formed on the first region and the third region of the first surface; A mask layer is deposited on the first surface; The first doped stack in the third region and the second sub-region is removed at least partially using a laser; a second doped stack is formed in the second sub-region and the third region; the thickness D1 of the first doped stack satisfies 50nm < D1 ≤ 250nm, and / or the thickness D2 of the second doped stack satisfies D2 ≤ 50nm; Removing at least partially the first doped stack of the third region and the second sub-region using a laser includes: The system employs alternating operation of a first pulse laser and a second pulse laser, with the frequency of the first pulse laser being lower than that of the second pulse laser; the single-operation time of the first pulse laser is 1 to 5 times that of the single-operation time of the second pulse laser.

2. The method for preparing a back contact battery according to claim 1, characterized in that, The mask layer is an aluminum oxide layer.

3. The method for preparing a back contact battery according to claim 2, characterized in that, While depositing a mask layer on the first surface, an aluminum oxide layer is simultaneously formed on the second surface.

4. The method for preparing a back contact battery according to claim 1, characterized in that, A first doped stack is formed on the first and third regions of the first surface, including: A tunneling layer and a doped silicon layer are formed on the first surface; Depositional barrier layer; Remove the tunneling layer and doped silicon layer and the barrier layer in the second region, and remove the barrier layers in the first and third regions.

5. The method for preparing a back contact battery according to claim 4, characterized in that, Wet chemical cleaning was used to remove the tunneling layer, doped silicon layer and barrier layer.

6. The method for preparing a back contact battery according to claim 4, characterized in that, The tunneling layer is made of silicon dioxide.

7. The method for preparing a back contact battery according to claim 1, characterized in that, The frequency of the first pulsed laser is 200-500 Hz; the frequency of the second pulsed laser is 700-1500 Hz.

8. The method for preparing a back contact battery according to claim 1, characterized in that, Also includes: Wet chemical cleaning removes the mask layer on the first surface; A passivation layer and a doped layer are deposited on the first surface; Remove the passivation layer and doped layer from the first region; A conductive film is deposited on the first surface; A portion of the conductive film in the third region is removed to form an isolation region; Electrodes are formed in the first sub-region and the second region, respectively.

9. An apparatus for manufacturing a back contact battery, characterized in that, The method for manufacturing a back contact battery as described in claim 1 includes: A film deposition apparatus is used to deposit a first doped stack on the surface of a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, the first surface including a first region, a second region and a third region, the third region being located between the first region and the second region, the first region including a first sub-region and a second sub-region, and the first doped stack being formed on the first region and the third region of the first surface. A laser etching apparatus is used to remove at least partially the first doped stack in the third region and the second sub-region using a laser to form a second doped stack in the second sub-region and the third region; the thickness D1 of the first doped stack satisfies 50 nm < D1 ≤ 250 nm, and / or the thickness D2 of the second doped stack satisfies D2 ≤ 50 nm; the laser etching apparatus is configured to operate alternately with a first pulse laser and a second pulse laser, the frequency of the first pulse laser being less than the frequency of the second pulse laser; the single operating time of the first pulse laser is 1 to 5 times the single operating time of the second pulse laser.

10. A back-contact battery, characterized in that, The back contact battery is prepared by the method described in any one of claims 1-8.

11. A photovoltaic module, characterized in that, include: Cover plate; At least one battery string, the battery string comprising a back contact battery obtained by the method for preparing a back contact battery according to any one of claims 1-8; as well as The backplate and the cover plate are located on opposite sides of the battery string, respectively.

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