Micro LED micro display chip

Abstract

The application provides a MicroLED micro display chip, a pixel layer of which comprises pixel units arranged in an array, each pixel unit comprising a first doped semiconductor, an active layer and a second doped semiconductor, the part of the first doped semiconductor, the active layer and the second doped semiconductor of each pixel unit close to the active layer forming a first step, and the rest part of the second doped semiconductor laterally protruding to form a second step; a first contact and a second contact are arranged on a driving substrate; the first contact is located below the pixel unit and connected with the bottom of the first step through a first metal layer; the second contact is located between two adjacent pixel units and the periphery of the array and connected with the bottom of the second step through a third metal layer. The chip has a simple structure, reduces the process difficulty and manufacturing cost, replaces the semiconductor material with the metal material for current transmission, reduces the common electrode terminal transmission resistance, enhances the current expansion of the common electrode, and is beneficial to improving the uniformity of the display effect and the luminous efficiency.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of semiconductor fabrication technology, and in particular to a MicroLED microdisplay chip. Background Technology

[0002] Existing MicroLED microdisplay chips typically employ a common electrode design, meaning all LEDs share a single P or N electrode. The common electrode carries a relatively large current and is usually located around the periphery of the effective display area. Figure 1 As shown; the other electrode is led out separately.

[0003] In existing technologies, the pixel common electrode current is transmitted to the peripheral common electrode area through the doped semiconductor layer, and then conducted to the driving substrate through the bonding metal to form a loop. Because the distance from the pixel to the common electrode varies at different locations in the effective display area, and the sheet resistance of the semiconductor material is relatively large, the transmission resistance at the common electrode is high, resulting in a severe IR drop (Current-related Resistance Voltage Drop, i.e., the voltage drop caused by the current (I) flowing through the resistance (R)) phenomenon, causing uneven brightness and a decrease in device luminous efficiency.

[0004] In view of this, the embodiments in this specification are intended to provide a MicroLED microdisplay chip. Summary of the Invention

[0005] In view of the problems existing in the prior art, such as different degrees of IR drop in pixels located at different positions in the effective display area, and the resulting high transmission resistance at the common electrode, which leads to uneven brightness and reduced luminous efficiency of the device, the purpose of the embodiments in this specification is to provide a MicroLED microdisplay chip.

[0006] To solve the above-mentioned technical problems, the specific technical solutions of the embodiments in this specification are as follows:

[0007] This specification provides an embodiment of a MicroLED microdisplay chip, including a pixel layer and a driving substrate:

[0008] The pixel layer includes a plurality of pixel units arranged in an array. Each pixel unit includes a first doped semiconductor, an active layer and a second doped semiconductor arranged sequentially in a direction away from the driving substrate. The portion of the first doped semiconductor, the active layer and the second doped semiconductor of each pixel unit that is close to the active layer forms a first step, and the portion of the second doped semiconductor that is far from the active layer protrudes laterally from the first step to form a second step.

[0009] The driving substrate is provided with a plurality of first contacts and a plurality of second contacts; the first contacts are connected to the bottom of the first step of the corresponding pixel unit through a first metal layer, and the second contacts are connected to the bottom of the second step of the corresponding pixel unit through a third metal layer.

[0010] By adopting the above technical solution, the MicroLED microdisplay chip provided in the embodiments of this specification uses metal materials instead of semiconductor materials for current transmission, which reduces the transmission resistance of the common electrode, enhances the current spread of the common electrode, helps to optimize the IR drop problem, and improves the uniformity of the display effect and the luminous efficiency.

[0011] To make the above and other objects, features and advantages of the embodiments of this specification more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This diagram illustrates the structure of a microdisplay chip employing a common-polarity design in the prior art.

[0014] Figure 2 This specification shows a schematic diagram of the structure of a MicroLED microdisplay chip provided in an embodiment.

[0015] Figure 3 A schematic diagram of the structure of the first and second steps of a single pixel unit is shown;

[0016] Figure 4 for Figure 2 Enlarged view of point a in the middle;

[0017] Figure 5 for Figure 2 Enlarged view of point b in the middle;

[0018] Figures 6a to 6k A schematic diagram illustrating the steps of the fabrication method of the MicroLED microdisplay chip provided in the embodiment is shown.

[0019] Explanation of reference numerals in the attached figures:

[0020] 10. Pixel layer; 11. Pixel unit; 12. First doped semiconductor; 13. Active layer; 14. Second doped semiconductor; 15. Conductive layer; 16. First step; 17. Second step;

[0021] 20. Driver substrate; 21. First contact; 22. Second contact;

[0022] 31. First metal layer; 32. Second metal layer; 33. Third metal layer; 34. Fourth metal layer; 35. Fifth metal layer; 36. Sixth metal layer;

[0023] 41. First passivation layer; 42. Second passivation layer; 43. Third passivation layer; 44. Fourth passivation layer;

[0024] 51. First opening; 52. Second opening; 53. Third opening; 54. Fourth opening; 55. Fifth opening; 56. Sixth opening;

[0025] 60. Substrate. Detailed Implementation

[0026] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0027] It should be noted that the terms "first," "second," etc., used in this specification, claims, and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0028] To address the issues in existing technologies where pixels at different locations within the effective display area have varying distances from the common electrode, resulting in different degrees of IR drop, and where the large sheet resistance of semiconductor materials leads to high transmission resistance at the common electrode, causing uneven brightness and reduced device luminous efficiency, this specification provides a MicroLED microdisplay chip.

[0029] like Figures 1 to 5 As shown in the embodiments of this specification, a MicroLED microdisplay chip includes a pixel layer 10 and a driving substrate 20:

[0030] The pixel layer 10 includes a plurality of pixel units 11 arranged in an array. Each pixel unit 11 includes a first doped semiconductor 12, an active layer 13, and a second doped semiconductor 14 sequentially disposed along a direction away from the driving substrate 20. That is, the first doped semiconductor 12 is located on the side of the active layer 13 closer to the driving substrate 20, and the second doped semiconductor 14 is located on the side of the active layer 13 away from the driving substrate 20. In the embodiments of this specification, the first doped semiconductor 12 can be a P-type semiconductor, and the second doped semiconductor 14 can be an N-type semiconductor, so that the P-type semiconductor and the N-type semiconductor are located at the bottom and top of the active layer 13, respectively.

[0031] The driving substrate 20 is provided with a plurality of first contacts 21 and a plurality of second contacts 22, wherein the first contacts 21 and the second contacts 22 have opposite polarities. The first contacts 21 correspond one-to-one with each pixel unit 11 and are located below the corresponding pixel unit 11. The second contacts 22 are located in the interval area between two adjacent pixel units 11 and in the outer periphery of the array. The first contacts 21 are connected to the bottom of the first doped semiconductor 12 of the corresponding pixel unit 11 through a first metal layer 31, and the second contacts 22 are connected to the bottom of the second doped semiconductor 14 of the corresponding pixel unit 11 through a third metal layer 33.

[0032] In this embodiment, the driving substrate 20 can be a CMOS or TFT substrate. The first contact 21 can be an addressing driving electrode, and the second contact 22 can be a common electrode; thus, the first contact 21 is located within the effective display area of ​​the pixel layer 10; a portion of the second contact 22 is located within the effective display area, and another portion is located outside the effective display area. Subsequently, the pixel layer 10 and the driving substrate 20 are aligned and bonded using processes such as hot pressing or hybrid bonding to achieve electrical connection and driving of each pixel unit 11.

[0033] The MicroLED microdisplay chip provided in this specification uses a first metal layer to electrically connect to the first doped semiconductor of each pixel unit and a third metal layer to electrically connect to the second doped semiconductor of each pixel unit. This replaces traditional semiconductor materials for current transmission, which helps reduce the transmission resistance of the common electrode and enhances the current spread of the common electrode, greatly optimizing the IR drop problem and improving the uniformity of the display effect and luminous efficiency. Furthermore, the first and second contacts are electrically connected to the first and second doped semiconductors from the bottom, respectively, which reduces light obstruction to the pixel units.

[0034] To facilitate the explanation of the structural features of the MicroLED microdisplay chip provided in this specification, a first step 16 is defined in the portion of the first doped semiconductor 12, the active layer 13, and the second doped semiconductor 14 of each pixel unit 11 that is closer to the active layer 13, and the remaining portion of the second doped semiconductor 14 that protrudes laterally forms a second step 17. The size of the second step 17 is larger than the size of the first step 16, i.e., as shown... Figure 3 As shown, the boundary line between the first step 16 and the second step 17 is indicated by a dashed line. The second step 17 is above the boundary line, and the first step 16 is below it. The two sides of the second step 17 (referring to the part of the upper end of the second doped semiconductor 14 that is far away from the active layer 13) protrude from the first step 16.

[0035] In this embodiment of the specification, each first contact 21 is connected to the bottom of the first step 16 of the corresponding pixel unit 11 through the first metal layer 31; each second contact 22 is connected to the bottom of the second step 17 of the corresponding pixel unit 11 through the third metal layer 33.

[0036] Specifically, the first step can be obtained by using a dry etching process to etch away the first doped semiconductor 12, the active layer 13, and a portion of the second doped semiconductor 14 near the driving substrate 20 in the spacing region between some pixel units; the second step can be formed by using a dry etching process to etch away another portion of the second doped semiconductor 14 away from the driving substrate 20 in the spacing region.

[0037] Specifically, the first metal layer 31 is located in the central region of the bottom surface of each first step 16.

[0038] The first metal layer 31 can be prepared by metal stripping or dry etching processes, and can be made from a single layer of Ag or Al, or by stacking at least one of Ag or Al with other metals (e.g., Ni, Ti, Cr, Pt, Au). The first metal layer 31 can form an ODR (Omni-Directional Reflector) structure with the first passivation layer 41 at the bottom of the first step, or form a hybrid reflector structure of high reflectivity metal + DBR, thereby improving light extraction efficiency.

[0039] The third metal layer 33 is located in the outer region of the bottom of each first step 16, the sidewall of the first step 16, the second step 17 protruding laterally from the bottom surface of the first step 16, the interval region between two adjacent pixel units 11, and the outer region of the array. The third metal layer 33 is electrically isolated from the first metal layer 31.

[0040] The third metal layer 33 can be manufactured by a metal stripping process. The third metal layer 33 can be obtained by alternating layers of one or more metal materials such as Cr, Al, Ni, Rh, Ti, Au, Pt, and Ag.

[0041] The third metal layer 33 serves as the connection material between the second contact 22 and the second doped semiconductor 14 of the pixel unit 11, and also as the contact layer of the second doped semiconductor 14. The first metal layer in the third metal layer 33 is preferably a metal material with a work function similar to that of the second doped semiconductor 14, such as Cr, Ti, Al, Rh, Ag, Au, Ge or Ni, in order to improve the quality of the formed ohmic contact.

[0042] In this embodiment of the specification, the projection of the first metal layer 31 covers the opening of the third metal layer 33 at the bottom of the first step.

[0043] That is, Figure 2 As shown, the portion of the third metal layer 33 corresponding to the bottom of the first step 16 has an opening. The size of this opening is smaller than the size of the first metal layer 31, so that the projection of the first metal layer 31 completely covers the area where the opening is located. This results in the first metal layer 31 and the third metal layer 33 together forming a fully enclosed reflective structure at the first step 16 (i.e., the bottom and side of the first step), which helps to reduce optical crosstalk between pixel units and improve light extraction efficiency.

[0044] Preferably, the MicroLED microdisplay chip further includes a second metal layer 32;

[0045] The second metal layer 32 is disposed at the bottom of the first metal layer 31, and the size of the second metal layer 32 is smaller than or equal to the size of the first metal layer 31 at the corresponding first step. Thus, each first contact 21 is electrically connected to the first doped semiconductor 12 of the corresponding pixel unit 11 via the second metal layer 32 and the first metal layer 31 in sequence.

[0046] Specifically, the second metal layer 32 can be made of one or more materials such as Cr, Pt, Ti, Ni, and TiW. Preferably, the second metal layer 32 is made of a metal material with high selectivity for F-based gases, such as Cr or Pt. The second metal layer 32 has a low reflectivity. In the embodiments of this specification, the size of the second metal layer 32 is limited to be smaller than the size of the first metal layer 31, so that the projection of the second metal layer 32 is completely located within the projection of the first metal layer 31. This avoids the second metal layer 32 extending beyond the first metal layer 31, where the extended portion replaces the first metal layer 31 and forms a fully enclosed reflective structure with the third metal layer 33, thereby reducing the light reflection efficiency in that area.

[0047] In the embodiments described in this specification, the second metal layer 32 is located below the first step of each pixel unit 11 and is electrically connected to the first metal layer 31. It can serve as an electrode thickening layer of the first metal layer 31 to increase current expansion, and at the same time, it serves as an etching barrier layer for the subsequent fourth opening 54 in this area.

[0048] Furthermore, in this embodiment of the specification, the fourth metal layer 34 is disposed at the bottom of the second metal layer 32, and the first contact 21 is electrically connected to the first doped semiconductor 12 of the corresponding pixel unit 11 via the fourth metal layer 34 at the bottom of the second metal layer 32.

[0049] The bottom of the third metal layer 33 is also provided with the fourth metal layer 34, and the second contact 22 is electrically connected to the second doped semiconductor 14 of the corresponding pixel unit 11 via the fourth metal layer 34 at the bottom of the third metal layer 33.

[0050] That is, the first contact 21 and the second contact 22 are both electrically connected to the first doped semiconductor 12 and the second doped semiconductor 14 of the corresponding pixel unit through the fourth metal layer 34, respectively.

[0051] Furthermore, the MicroLED microdisplay chip provided in the embodiments of this specification also includes a fifth metal layer 35, which is located in the pixel spacing region between two adjacent pixel units 11 and the peripheral region of the array (e.g., Figure 2 (as shown)

[0052] The fifth metal layer 35 electrically connects a portion of the second step sidewall of the pixel unit 11 to the second contact 22, which helps to enhance current injection, thereby reducing current injection congestion and improving the device's luminous efficiency; the fifth metal layer 35 forms a metal mesh structure connected to the common electrode at the periphery of the effective display area.

[0053] Taking GaN as an example, the second doped semiconductor has an N-polarity plane (i.e., as shown in the image). Figure 2 As shown, the top surface of the second-doped semiconductor (the surface where the second-doped semiconductor contacts the active layer) has an opposite polarization electric field to the Ga polarization surface due to polarity. This results in the N-plane Schottky barrier being approximately 1 eV higher than that of the Ga surface, making it difficult to form an ohmic contact. Furthermore, the N-plane of GaN has a complex surface state due to surface dangling bonds, leading to the adsorption of impurities such as oxygen. Additionally, various donor or acceptor level defects caused by processes such as etching can also cause device stability issues.

[0054] In the embodiments described in this specification, the fifth metal layer contacts a portion of the sidewall of the second step (i.e., the second doped semiconductor), rather than contacting its top N-polar surface. This avoids the problem of difficulty in forming a good ohmic contact on the N-polar surface due to the aforementioned reasons. The fifth metal layer contacts the side of the second doped semiconductor at a non-polar surface, which eliminates the distortion of the interface energy band by the polarization electric field. This allows the potential barrier height between the metal and semiconductor to return to the intrinsic properties of the material, making it easier to achieve low-resistance ohmic contacts using conventional metal systems. Furthermore, the side region typically avoids nucleation interfaces with high defect density and is relatively controllable by the process, resulting in a more stable contact interface with lower leakage current. This significantly improves the long-term reliability and process yield of the device.

[0055] A fifth metal layer 35 can be obtained by depositing one or more materials such as Ti, Cr, Al, Au, Pt, Rh, and Ni using a metal stripping process, and the height of the top surface of the fifth metal layer 35 is higher than or equal to the height of the top surface of the second step 17, so as to form a metal reflector between pixel units and reduce optical crosstalk between pixel units.

[0056] As shown in the figure, the MicroLED microdisplay chip also includes a sixth metal layer 36, which is disposed in the interval region between two adjacent pixel units 11 and the outer region of the array. The size of the sixth metal layer 36 located in the interval region is smaller than the size of the corresponding pixel interval region.

[0057] The sixth metal layer 36 electrically connects the second contact 22 to the fifth metal layer 35.

[0058] By using a multilayer metal layer consisting of a sixth metal layer, a fifth metal layer, and a third metal layer, the bottom and / or sides of the second doped semiconductor 14 of the pixel unit can be connected to the common electrode region, effectively reducing the transmission resistance of the common electrode and enhancing the current spread of the common electrode layer.

[0059] It should be noted that in the embodiments of this specification, the second metal layer 32 and the sixth metal layer 36 are prepared using the same material in the same metal stripping process.

[0060] Furthermore, the MicroLED microdisplay chip provided in the embodiments of this specification also includes a first passivation layer 41;

[0061] The first passivation layer 41 is deposited at the bottom of the pixel layer 10. The first passivation layer 41 is provided with a plurality of through first openings 51, and the first openings 51 are located at the bottom of the first step (e.g., Figure 5 (As shown).

[0062] In the embodiments described in this specification, the first passivation layer 41 can be made of one or more alternating layers of materials with different refractive indices, such as SiO2, SiN, Al2O3, and TiO2, to form a DBR (multilayer interference mirror) structure. The first opening 51 can be formed after removing the first passivation layer 41 at the corresponding position using a wet or dry etching process.

[0063] The first metal layer 31 is disposed on the side of the first passivation layer 41 facing the driving substrate 20; the first metal layer 31 covers the first opening 51 to electrically connect the first contact 21 to the first doped semiconductor 12 of the corresponding pixel unit 11.

[0064] The first passivation layer 41 is also provided with a plurality of through third openings 53, the third openings 53 being located at the bottom of the second step 17 (e.g., Figure 4 (As shown). The third opening 53 can be formed by removing the first passivation layer 41 at the corresponding position using a wet or dry etching process.

[0065] The third metal layer 33 is disposed on the side of the first passivation layer 41 facing the driving substrate 20, and the third metal layer 33 covers the third opening 53 to electrically connect the second contact 22 to the second doped semiconductor 14 of the corresponding pixel unit 11.

[0066] In this embodiment, a first opening 51 is formed in the first passivation layer 41 at the first doped semiconductor 12 of the pixel unit 11, so that the first metal layer 31 covers the first opening 51 to electrically connect to the P-type semiconductor of the pixel unit; and a third opening 53 is formed in the first passivation layer 41 at the second doped semiconductor 14 of the pixel unit 11, so that the third metal layer 33 covers the third opening 53 to electrically connect to the N-type semiconductor of the pixel unit 11; thus, electrical conduction between the first contact 21 and the second contact 22 and the corresponding pixel unit electrode is achieved. Furthermore, using a metal material instead of a traditional semiconductor material as the common electrode current transmission material helps to reduce the transmission resistance at the common electrode, thereby helping to optimize the IR drop problem.

[0067] In some preferred embodiments, after etching to form the third opening 53 to expose the second doped semiconductor 14 at the bottom of the second step 17, the surface of the second doped semiconductor 14 can be treated with Cl-based plasmas such as CL2, BCl3, and SiCl4 to optimize the ohmic contact between the second doped semiconductor 14 and the third metal layer 33.

[0068] Furthermore, the first passivation layer 41 is provided with a through fifth opening 55, which is located in the pixel spacing region between two adjacent pixel units 11 (e.g., Figure 4 (as shown) and the outer region of the array;

[0069] The fifth metal layer 35 covers the fifth opening 55 (i.e., the fifth opening 55 corresponds to the fifth metal layer 35) to electrically connect a portion of the sidewall of the second step 17 to the second contact 22.

[0070] In this embodiment of the specification, the second contact 22 can be connected to the bottom side of the second step of each pixel unit 11 via the third metal layer 33 at the third opening 53, and can also be connected to a portion of the sidewall of the second step of each pixel unit 11 via the fifth metal layer 35 at the fifth opening 55, thereby expanding the contact area with the second doped semiconductor 14 of the pixel unit 11, which is beneficial to reduce current injection congestion and improve the uniformity of the display effect.

[0071] like Figure 2 As shown, the MicroLED microdisplay chip also includes a second passivation layer 42;

[0072] The second passivation layer 42 is disposed at the bottom of the first passivation layer 41 and covers the first metal layer 31. That is, the second passivation layer 42 is located between the first metal layer 31 and the third metal layer 33. The third metal layer 33 is electrically isolated from the first metal layer 31 through the second passivation layer 42, thus ensuring electrical isolation between the first contact 21 and the second contact 22.

[0073] In the embodiments described in this specification, the second passivation layer 42 may be made of one or more materials such as SiO2, SiN, Al2O3, and HfO2.

[0074] The second passivation layer 42 has a through-hole 52, which is located in the gap between two adjacent pixel units (e.g., Figure 4 (as shown) and the outer region of the array;

[0075] The third metal layer 33 covers the second opening 52 to connect the second contact 22 to a portion of the sidewall of the second step 17 of the pixel unit via the sixth metal layer 36 and the fifth metal layer 35.

[0076] It should be noted that when a second passivation layer 42 is deposited at the bottom of the first passivation layer 41, the third opening 53 needs to correspondingly penetrate the second passivation layer 42 located at the bottom of the second step (e.g., Figure 4 (As shown).

[0077] In this embodiment, the sixth metal layer 36 serves as a connecting intermediate layer, connecting the third, fourth, and fifth metal layers through the second opening 52 of the second passivation layer 42 and the fifth opening of the first passivation layer 41. It also acts as an etching barrier layer for the fifth opening 55, protecting the third metal layer 33 in the area of ​​the fifth opening 55. Thus, by connecting the bottom or side of the second doped semiconductor 14 of the pixel unit to the common electrode region through multiple metal layers, the transmission resistance of the common electrode is effectively reduced, and the current spread of the common electrode layer is enhanced.

[0078] like Figure 2 As shown, it also includes a third passivation layer 43;

[0079] The third passivation layer 43 is disposed at the bottom of the first metal layer 31 and the third metal layer 33. The third passivation layer 43 is provided with a through fourth opening 54, which corresponds to each first contact 21 and each second contact 22. That is, a part of the fourth opening 54 is located at the bottom of the first step of each pixel unit 11 to correspond to each first contact 21; another part of the fourth opening 54 is located in the pixel spacing area between two adjacent pixel units 11 and the outer area of ​​the array to correspond to each second contact 22.

[0080] Specifically, the third passivation layer 43 can be obtained by depositing an inorganic passivation material or spin-coating an organic passivation material onto the bottom of the pixel layer 10 on which the first, second, and third metal layers are deposited, and then planarizing it using chemical mechanical polishing. The inorganic passivation material may include one or more of SiO2, PSG, and BPSG, while the organic passivation material may include one or more of polyimide, styrene-cyclobutene resin, and epoxy resin.

[0081] The fourth opening 54 can be formed by dry etching to remove the third passivation layer 43 at the corresponding position, and then the fourth metal layer 34 is deposited and filled into each fourth opening 54 to bond the pixel layer 10 and the driving substrate 20.

[0082] Specifically, the fourth metal layer 34 can be filled in the fourth opening 54 by means of electroplating, electron beam evaporation, thermal evaporation, magnetron sputtering, etc., and then the surface of the fourth metal layer 34 can be planarized by means of chemical mechanical polishing, etc. The height of the fourth metal layer 34 after treatment can be higher or lower than the height of the third passivation layer 43 or flush with the third passivation layer 43.

[0083] like Figure 2 As shown, the MicroLED microdisplay chip provided in the embodiments of this specification also includes a fourth passivation layer 44;

[0084] The fourth passivation layer 44 covers the top and side surfaces of the second step and the fifth metal layer 35.

[0085] The fourth passivation layer 44 can be deposited from alkali-resistant corrosion-resistant materials such as SiO2 and SiN. The fourth passivation layer 44 can passivate and protect the fifth metal layer 35 and the top and sides of each pixel unit 11, so that it will not be contacted by the etching solution in the subsequent wet etching process or by the plasma in the subsequent dry etching process.

[0086] Specifically, the fourth passivation layer 44 is provided with a through sixth opening 56;

[0087] The sixth opening 56 is located on the top surface of the second step of each pixel unit 11 and is used for light emission from each pixel unit 11. The surface of the second doped semiconductor 14 exposed at the sixth opening 56 is a rough surface.

[0088] Specifically, alkaline solutions such as KOH, NaOH, TMAH, NH4OH, and NH4OH:H2O2 can be used for wet etching, or acidic solutions such as HF or aqua regia can be used for red light or dry etching to roughen the top region of the second step exposed at the sixth opening of the fourth passivation layer 44, thereby roughening the second doped semiconductor 14 in this region to improve the light extraction efficiency.

[0089] Furthermore, the position and size of the sixth opening 56 correspond to the position and size of the first step to ensure that the light-emitting area corresponds to the roughened surface, thereby reducing the probability of light being transmitted to the non-roughened area and further improving the light extraction efficiency.

[0090] Furthermore, such as Figure 2 As shown, the MicroLED microdisplay chip provided in the embodiments of this specification further includes a conductive layer 15, which is disposed between the first doped semiconductor 12 and the first passivation layer 41 of each pixel unit 11; the size of the conductive layer 15 is greater than or equal to the size of the first metal layer 31 at the corresponding pixel unit 11.

[0091] In the embodiments of this specification, the conductive layer 15 may be obtained by annealing one or more of transparent conductive oxides such as SnO2, ITO, and ZnO and patterning them using wet etching or dry etching to form ohmic contacts.

[0092] To further illustrate the MicroLED microdisplay chip provided in the embodiments of this specification, the fabrication method of the display chip is briefly described below.

[0093] The fabrication method of this MicroLED display chip may include the following steps:

[0094] 1. Multiple first steps are etched on the LED epitaxial wafer with a deposited conductive layer.

[0095] like Figure 6a As shown, the LED epitaxial wafer includes at least a substrate 60, a first doped semiconductor 12 (P-type semiconductor), an active layer 13, and a second doped semiconductor 14 (N-type semiconductor). The second doped semiconductor 14 is located on the side of the active layer 13 closest to the substrate 60, and the first doped semiconductor 12 is located on the other side of the active layer 13.

[0096] The conductive layer 15 can be formed by annealing one or more transparent conductive oxide materials such as SnO2, ITO, and ZnO and patterning them using wet etching or dry etching to form ohmic contacts. The first doped semiconductor 12, the active layer 13, and part of the second doped semiconductor 14 are removed by dry etching to form the first step 16 of each pixel unit 11.

[0097] 2. The first passivation layer is deposited and etched to obtain the first opening.

[0098] like Figure 6b As shown, the first passivation layer 41 can be made of one or more alternating layers of materials with different refractive indices, such as SiO2, SiN, Al2O3, and TiO2, to form a DBR (multilayer interference mirror) structure. The first opening 51 can be formed by removing the first passivation layer 41 on the surface of the first step and exposing the conductive layer 15 through a wet or dry etching process.

[0099] 3. Fabricate the first and second metal layers.

[0100] The first metal layer 31 can be prepared using a metal stripping process, positioned at the first step 16 and covering the first opening 51. The size of the first metal layer 31 is less than or equal to the size of the conductive layer 15 (e.g., ...). Figure 6c (As shown).

[0101] The first metal layer 31 can be prepared by a single layer of Ag or Al, or by a stack of at least one of Ag or Al with one or more of Ni, Ti, Cr, Pt, and Au. The first metal layer 31 can form an ODR structure with the first passivation layer 41 at the bottom of the first step 16, or form a hybrid reflective mirror structure of high reflectivity metal + DBR, thereby improving the light extraction efficiency.

[0102] A second metal layer 32 is deposited on the first metal layer 31 at the first step 16, and the size of the second metal layer 32 is less than or equal to the size of the first metal layer 31. A second metal layer 32 is deposited on the first passivation layer 41 in the spacing region between two adjacent pixel units 11 and in the peripheral region of the array (for ease of distinction, the second metal layer in the above region is referred to as the sixth metal layer 36), and the size of the sixth metal layer 36 located in the pixel spacing region is smaller than the size of the corresponding pixel spacing region.

[0103] The sixth metal layer 36, located in the pixel spacing region, forms a metal mesh structure connected to the common electrode region. The second metal layer (sixth metal layer) is preferably made of a metal material with high selectivity for F-based gases, such as Cr or Pt.

[0104] 4. Deposit a second passivation layer and etch to obtain the second and third openings.

[0105] like Figure 6d As shown, the second passivation layer 42 can be made of one or more materials such as SiO2, SiN, Al2O3, and HfO2. A portion of the second passivation layer 42 at the sixth metal layer 36 is removed using dry etching to form a second opening 52. At least a portion of the first and second passivation layers between the first steps is then etched away to form a third opening 53, exposing the second doped semiconductor 14. Preferably, after etching to obtain the third opening 53, the surface of the second doped semiconductor 14 can be treated with Cl-based plasmas such as Cl2, BCl3, and SiCl4 to optimize the subsequent ohmic contact between the second doped semiconductor 14 and the third metal layer 33.

[0106] 5. Fabricate the third metal layer

[0107] like Figure 6e As shown, a third metal layer 33 can be formed by a metal stripping process, and it is located in the outer region at the bottom of each first step, the sidewall of the first step, the region between two adjacent first steps, and the outer region of the array.

[0108] The third metal layer 33 is connected to the second doped semiconductor 14 through the third opening 53 to form an ohmic contact, and will subsequently be connected to the common electrode through the second opening 52. The opening of the third metal layer 33 at the first step 16 is smaller than the size of the first metal layer 31, so that the first metal layer 31 and the third metal layer 33 cover the entire first step 16 to form a fully enclosed reflective structure.

[0109] The third metal layer 33 can be obtained by alternating layers of one or more metals. Preferably, the first metal in the third metal layer 33 is Cr, Ti, Al, Rh, Ag, Au, Ge, etc., which has a work function similar to that of the second doped semiconductor 14, which is beneficial to improving the quality of the formed ohmic contact.

[0110] 6. Deposit the third passivation layer and etch to obtain the fourth opening.

[0111] like Figure 6fAs shown, the third passivation layer 43 is obtained by depositing an inorganic passivation material or spin-coating an organic passivation material, and then planarizing it using chemical mechanical polishing. The inorganic passivation material may include one or more of SiO2, PSG, and BPSG, while the organic passivation material may include one or more of polyimide, styrene-cyclobutene resin, and epoxy resin.

[0112] The third passivation layer 43 is etched away, removing at least a portion located at the center of the first step 16, between two adjacent first steps 16, and in the outer region of the array, to obtain a fourth opening 54 corresponding to each first contact 21 and second contact 22. It should be noted that the fourth opening 54 located at the first step 16 must also penetrate the second passivation layer 42 on the top surface of the first step 16, so that the fourth opening 54 can expose the second metal layer 32.

[0113] 7. Deposit the fourth metal layer and connect it to the driving substrate.

[0114] like Figure 6g As shown, the fourth metal layer 34 is filled in the fourth opening 54 by means of electroplating, electron beam evaporation, thermal evaporation, magnetron sputtering, etc., and then the surface of the fourth metal layer 34 is planarized by means of chemical mechanical polishing, so that the height of the fourth metal layer 34 after treatment is higher than or lower than the height of the third passivation layer 43, or flush with the third passivation layer 43.

[0115] The flip device is connected to the driving substrate 20, which can be a CMOS or TFT substrate.

[0116] The driving substrate 20 includes multiple first contacts 21 and multiple second contacts 22. The first contacts 21 are addressing driving electrodes located within the effective display area of ​​the pixel layer 10; the second contacts 22 are common electrodes located within the effective area and the periphery of the display area. The fourth metal layer 34 of the LED is aligned and bonded to the multiple contacts of the driving substrate 20 by hot pressing or hybrid bonding, thereby achieving electrical connection between the driving substrate and the LED.

[0117] 8. Remove the LED substrate and etch to form the second step.

[0118] like Figure 6h As shown, the LED substrate 60 is removed using laser lift-off, dry etching, or wet etching.

[0119] The second step 17 is formed by etching away another part of the second doped semiconductor 14 away from the driving substrate 20 in the pixel spacing area using a dry etching process, and the size of the second step 17 is larger than the size of the first step 16, that is, the two sides of the second step 17 protrude from the first step 16.

[0120] 9. Etching to form the fifth opening

[0121] like Figure 6i As shown, the portion of the first passivation layer 41 located in the pixel spacing region and the outer region of the array above the second contact point is etched to form a fifth opening 55, so that the fifth opening 55 subsequently corresponds to the fifth metal layer 35, and the second metal layer 32 at each common electrode is exposed at the fifth opening 55.

[0122] 10. Deposit the fifth metal layer and deposit the fourth passivation layer.

[0123] like Figure 6j As shown, a fifth metal layer 35 is deposited in the pixel spacing region and the outer region of the array to cover the fifth opening 55. The fifth metal layer 35 forms a metal mesh structure connected to the common electrode region around the effective display area.

[0124] The bottom portion of the fifth metal layer 35 is made in contact with at least a portion of the sidewall of the second step 17 to enhance current injection. The height of the fifth metal layer 35 is greater than or equal to the height of the second step 17 to form an inter-pixel metal reflector and reduce inter-pixel optical crosstalk. The fifth metal layer 35 can be prepared from one or more materials such as Ti, Cr, Al, Au, Pt, Rh, and Ni.

[0125] A fourth passivation layer 44 is deposited on the top and side surfaces of the second step 17 and the fifth metal layer 35. The fourth passivation layer 44 may be obtained by depositing alkali-resistant materials such as SiO2 and SiN.

[0126] 11. The sixth opening was obtained by etching and then passivated.

[0127] like Figure 6k As shown, the fourth passivation layer 44 is etched to at least a portion of the top surface of the second step 17 of each pixel unit 11 to obtain a sixth opening 56, such that the position and size of the sixth opening 56 correspond to the position and size of the first step 16, so as to ensure that the light-emitting area corresponds to the roughened surface, thereby reducing the probability of light being transmitted to the non-roughened area and further improving the light extraction efficiency.

[0128] The top region of the second step 17 exposed at the sixth opening 56 can be roughened by wet processing with alkaline solutions such as KOH, NaOH, TMAH, NH4OH, and NH4OH:H2O2, or by red light or dry processing with acidic solutions such as HF or aqua regia, to improve the light extraction efficiency.

[0129] Thus, the MicroLED display chip provided in the embodiments of this specification can be obtained. It should be noted that the above preparation method is only one feasible method, and those skilled in the art can adjust it according to actual needs to obtain other methods different from the above preparation method, and prepare the MicroLED display chip as provided in the embodiments of this specification.

[0130] It should be noted that, in the embodiments of this specification, the use of the terms "comprising" or "including" to describe combinations of elements, components, parts, or steps herein also contemplates embodiments essentially composed of these elements, components, parts, or steps. The use of the term "may" herein is intended to indicate that any described attribute "may" include is optional. Multiple elements, components, parts, or steps can be provided by a single integrated element, component, part, or step. Alternatively, a single integrated element, component, part, or step can be divided into multiple separate elements, components, parts, or steps. The use of "a" or "an" to describe an element, component, part, or step does not imply exclusion of other elements, components, parts, or steps.

[0131] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from the others. Similar or identical parts between embodiments can be referred to interchangeably. The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made according to the spirit and essence of the present invention should be included within the scope of protection of the present invention.

Claims

1. A Microled microdisplay chip, characterized in that, Includes pixel layer and driving substrate: The pixel layer includes a plurality of pixel units arranged in an array. Each pixel unit includes a first doped semiconductor, an active layer and a second doped semiconductor arranged sequentially in a direction away from the driving substrate. The portion of the first doped semiconductor, the active layer and the second doped semiconductor of each pixel unit that is close to the active layer forms a first step, and the portion of the second doped semiconductor that is far from the active layer protrudes laterally from the first step to form a second step. The driving substrate is provided with a plurality of first contacts and a plurality of second contacts; the first contacts are connected to the bottom of the first step of the corresponding pixel unit through a first metal layer, and the second contacts are connected to the bottom of the second step of the corresponding pixel unit through a third metal layer. The first metal layer is located in the central region of the bottom surface of each first step, and the third metal layer is located in the outer region of the bottom of each first step, the side wall of the first step, the second step that protrudes laterally from the bottom surface of the first step, the interval region between two adjacent pixel units, and the outer region of the array; the portion of the third metal layer corresponding to the bottom of the first step is provided with an opening, and the projection of the first metal layer covers the opening of the third metal layer at the bottom of the first step.

2. The Microled microdisplay chip according to claim 1, characterized in that, The first contact point corresponds one-to-one with each pixel unit and is located below the corresponding pixel unit. The second contact point is located in the interval area between two adjacent pixel units and in the outer area of ​​the array.

3. The Microled microdisplay chip according to claim 2, characterized in that, The third metal layer is electrically isolated from the first metal layer.

4. The Microled microdisplay chip according to claim 3, characterized in that, It also includes a fifth metal layer, which is disposed in the spacing region between two adjacent pixel units and the peripheral region of the array; The fifth metal layer electrically connects a portion of the sidewall of the second step of the pixel unit to the second contact.

5. The Microled microdisplay chip according to claim 4, characterized in that, The height of the top surface of the fifth metal layer is higher than or equal to the height of the top surface of the second step.

6. The Microled microdisplay chip according to claim 3, characterized in that, It also includes a second metal layer; The second metal layer is disposed at the bottom of the first metal layer, and the size of the second metal layer is less than or equal to the size of the first metal layer at the corresponding first step.

7. The Microled microdisplay chip according to claim 6, characterized in that, A fourth metal layer is disposed at the bottom of the second metal layer, and the first contact is electrically connected to the first doped semiconductor of the corresponding pixel unit via the fourth metal layer at the bottom of the second metal layer. A fourth metal layer is disposed at the bottom of the third metal layer, and the second contact is electrically connected to the second doped semiconductor of the corresponding pixel unit via the fourth metal layer at the bottom of the third metal layer.

8. The Microled microdisplay chip according to claim 4, characterized in that, It also includes a sixth metal layer, which is disposed in the interval region between two adjacent pixel units and the outer region of the array. The size of the sixth metal layer located in the interval region is smaller than the size of the corresponding pixel unit interval. The sixth metal layer electrically connects the third metal layer and the fifth metal layer.

9. The Microled microdisplay chip according to claim 4, characterized in that, It also includes a first passivation layer, which is deposited at the bottom of the pixel layer. The first passivation layer is provided with a plurality of through first openings, which are located at the bottom of the first step. The first metal layer is located on the side of the first passivation layer facing the driving substrate and covers the first opening. The first metal layer at the first opening electrically connects the first contact to the first doped semiconductor of the corresponding pixel unit.

10. The Microled microdisplay chip according to claim 9, characterized in that, The first passivation layer is also provided with a plurality of through third openings, the third openings being located at the bottom of the second step; The third metal layer is located on the side of the first passivation layer facing the driving substrate and covers the third opening. The third metal layer at the third opening electrically connects the second contact to the second doped semiconductor of the corresponding pixel unit.

11. The Microled microdisplay chip according to claim 9, characterized in that, The first passivation layer has a through fifth opening, which is located in the spacing region between two adjacent pixel units and in the peripheral region of the array; The fifth metal layer covers the fifth opening, electrically connecting a portion of the sidewall of the second step to the second contact.

12. The Microled microdisplay chip according to claim 9, characterized in that, It also includes a second passivation layer; The second passivation layer is disposed at the bottom of the first passivation layer and located between the first metal layer and the third metal layer, wherein the third metal layer is electrically isolated from the first metal layer through the second passivation layer.

13. The Microled microdisplay chip according to claim 12, characterized in that, The second passivation layer has a through second opening, which is located in the spacing region between two adjacent pixel units and the outer region of the array; The third metal layer covers the second opening to be electrically connected to the fifth metal layer.

14. The Microled microdisplay chip according to claim 7, characterized in that, It also includes a third passivation layer; The third passivation layer is disposed at the bottom of the first metal layer and the third metal layer, and the third passivation layer is provided with a through fourth opening, which corresponds to each first contact and each second contact. The fourth metal layer covers each of the fourth openings to bond the pixel layer to the driving substrate.

15. The Microled microdisplay chip according to claim 4, characterized in that, It also includes a fourth passivation layer; The fourth passivation layer covers the top and side surfaces of the second step and the fifth metal layer.

16. The Microled microdisplay chip according to claim 15, characterized in that, The fourth passivation layer is provided with a penetrating sixth opening; The sixth opening is located on the top surface of the second step of each pixel unit, and the surface of the second doped semiconductor exposed at the sixth opening is a rough surface.

17. The Microled microdisplay chip according to claim 16, characterized in that, The position and size of the sixth opening correspond to the position and size of the first step.

18. The Microled microdisplay chip according to claim 9, characterized in that, It also includes a conductive layer disposed between the first doped semiconductor and the first passivation layer of each pixel unit; The size of the conductive layer is greater than or equal to the size of the first metal layer at the corresponding pixel unit.

Images