Display device and display panel

Abstract

The present application relates to display devices and display panels. The present disclosure can provide a display device including a display panel in which an optical electronic device is disposed within a display area, wherein the display area includes a normal area in which a plurality of sub-pixels including a light-emitting layer are disposed, a through hole in which the optical electronic device is located, and a peripheral area between the normal area and the through hole in which one or more light-emitting layer disconnection patterns are formed.

Description

Technical Field

[0001] Embodiments of this disclosure relate to display devices and display panels, and more specifically, for example, but not limited to, display devices and display panels capable of effectively forming light-emitting layer break patterns to reduce, minimize, or prevent moisture penetration through through-holes where optoelectronic devices are located. Background Technology

[0002] As examples of display devices used to display images using digital data, there are liquid crystal displays (LCDs) that use liquid crystals and organic light-emitting displays (OLEDs) that use organic light-emitting diodes.

[0003] In display devices, organic light-emitting diodes (OLEDs) utilize self-emissive light-emitting diodes (LEDs), which offer fast response times and advantages in contrast, luminous efficiency, brightness, and viewing angle. In this case, the LEDs can be made of inorganic or organic materials.

[0004] An organic light-emitting display device may include an organic light-emitting diode in each of a plurality of sub-pixels arranged on a display panel, and the brightness of each sub-pixel may be controlled by controlling the voltage flowing to the organic light-emitting diode to emit light, thereby displaying an image.

[0005] With advancements in technology, these display devices can offer image capture and various sensing functions in addition to displaying images. For this purpose, display devices can be equipped with optical electronics or components (also known as light receiving devices or sensors) such as cameras and sensing sensors.

[0006] Since optoelectronic devices need to receive light from the front of the display device, they must be mounted in a location that facilitates light reception. Therefore, research is underway to form through-holes in the effective area forming sub-pixels and place the optoelectronic devices within these through-holes.

[0007] In this way, the configuration of having through holes in the display area for placing optical electronic devices can be called display area through-hole (HiAA).

[0008] The descriptions provided in this Background section should not be assumed to be prior art simply because they are mentioned in or associated with this section. The Background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0009] However, if moisture enters the vias where the optical electronics are located, there is a problem of performance degradation of the light-emitting elements that constitute the sub-pixels.

[0010] Therefore, the inventors of this disclosure recognized the above-mentioned limitations and other limitations associated with the related art, and conducted various experiments to realize a display device and display panel that can effectively form a light-emitting layer break pattern to prevent or reduce the inflow of moisture through the through-holes where the optical electronics are located.

[0011] Embodiments of this disclosure may provide a display device and a display panel having a light-emitting layer break pattern formed to effectively block or reduce the inflow of moisture from the sides and bottom through through-holes.

[0012] Embodiments of this disclosure provide a display device and display panel that can effectively block or reduce moisture flowing in through the through-holes, even when the display panel is performing flexible operation.

[0013] To achieve these and other aspects of the inventive concept, as implemented and broadly described herein, a display device according to embodiments of the present disclosure may include a display panel, wherein optical electronics are disposed within a display area, wherein the display area includes a normal area in which a plurality of sub-pixels including a light-emitting layer are disposed, a via in which the optical electronics are located, and a peripheral area between the normal area and the via in which one or more light-emitting layer break patterns are formed.

[0014] In another aspect, a display panel according to an embodiment of the present disclosure may include a normal area in which a plurality of sub-pixels including a light-emitting layer are disposed, a via in which an optical electronic device is located, and a peripheral area between the normal area and the via in which one or more light-emitting layer break patterns are formed.

[0015] In another aspect, a display device according to an embodiment of the present disclosure may include a display panel, wherein optical electronics are disposed in a display area, wherein the display area includes a normal area in which a plurality of sub-pixels including a light-emitting layer are disposed, a via in which the optical electronics are located, and a peripheral area between the normal area and the via, and wherein the light-emitting layer is physically divided into two portions spaced apart from each other in the peripheral area.

[0016] According to embodiments of this disclosure, it is possible to effectively form a light-emitting layer break pattern that can reduce, minimize, or prevent moisture from entering through the vias where the optical electronics are located.

[0017] According to embodiments of this disclosure, process optimization can be achieved during the formation of a light-emitting layer disconnect pattern that effectively blocks moisture from flowing in from the sides and bottom through the through-holes.

[0018] According to embodiments of this disclosure, even in the case of a display panel that performs flexible operation, it is possible to effectively reduce or block moisture flowing in through the through-holes.

[0019] The effects of this disclosure are not limited to those described above, and other effects will become apparent to those skilled in the art from the following detailed description.

[0020] It should be understood that both the above general description and the following detailed description are illustrative and explanatory, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0021] The accompanying drawings may be included to provide a further understanding of the present disclosure and may be incorporated into and constitute a part of the present disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the various principles of the present disclosure.

[0022] Figure 1 A system diagram of a display device according to an exemplary embodiment of the present disclosure is illustrated schematically.

[0023] Figure 2 An equivalent circuit of a sub-pixel in a display panel according to an exemplary embodiment of the present disclosure is illustrated as an example.

[0024] Figure 3 An example embodiment of the present disclosure illustrates the arrangement of sub-pixels in three regions included in the display area of ​​a display panel.

[0025] Figure 4 A cross-section of a display area in a display panel according to an exemplary embodiment of the present disclosure is illustrated.

[0026] Figure 5 The planar structure of the optical region in a display panel according to an exemplary embodiment of the present disclosure is illustrated.

[0027] Figure 6 Cross-sections of the normal area and optical area in a display panel according to an exemplary embodiment of the present disclosure are illustrated.

[0028] Figures 7 to 13 These are cross-sectional views illustrating the manufacturing process of a display panel according to an exemplary embodiment of the present disclosure.

[0029] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, and convenience, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0030] In the following description, some embodiments of this disclosure will be described in detail with reference to exemplary accompanying drawings. In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings in which specific examples or embodiments that can be implemented are illustrated, and in the drawings, the same reference numerals and symbols may be used to designate the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein may obscure the subject matter of some embodiments of this disclosure. Unless more restrictive terms such as “only” are used, terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of other components. As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that necessarily occur in a particular order. Similar reference numerals designate similar elements throughout. The names of the corresponding components used in the following description may have been chosen for ease of writing the instruction manual only, and therefore may differ from the names used in the actual product.

[0031] The advantages and features of this disclosure, and its implementation methods, will become clear from the following exemplary embodiments described in conjunction with the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is defined only by the scope of the claims. Any implementation described herein as an "example" is not necessarily to be construed as preferred or advantageous over other implementations.

[0032] The shapes, dimensions, scales, angles, quantities, etc., illustrated in the accompanying drawings to describe various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. Unless otherwise stated, the same or similar elements are indicated by the same reference numerals throughout the specification. In the following description, detailed descriptions of relevant well-known functions or configurations may be omitted where such detailed descriptions may unnecessarily obscure the essential points of this disclosure.

[0033] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0034] When referring to the first element as "connected to or linked to," "in contact with," or "overlapping" with the second element, it should be understood that not only can the first element be "directly connected to or linked to" or "directly in contact with or overlapping" the second element, but a third element is also "inserted" between the first and second elements, or the first and second elements can be "connected to or linked to," "in contact with," or "overlapping" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected to or linked to," "in contact with," or "overlapping" with each other.

[0035] When time-related terms such as “after,” “follow,” “next,” “before,” etc., are used to describe a process or operation of an element or structure, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation unless used with more restrictive terms such as “direct” or “immediate.”

[0036] When describing positional relationships, such as using terms like "on," "above," "below," "above," "under," "below," "near," "close to," "adjacent to," "beside," or "next to" to describe the positional relationship between two components, one or more other components may be placed between the two components unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when a structure is described as being "above," "below," "on top," "below," "below," "near," "close to," "adjacent to," "beside," or "next to" another structure, this description should be interpreted to include situations where these structures are in contact with each other and situations where a third structure is placed or inserted between them. Furthermore, the terms "left," "right," "top," "bottom," "down," "up," "upper," "lower," etc., refer to any frame of reference.

[0037] The term “at least one” should be understood to include any and all combinations of one or more of the related listed items. For example, “at least one of the first element, the second element and the third element” means all combinations of the three listed elements, any combination of any two of the three elements, and each individual element, the first element, the second element or the third element.

[0038] Furthermore, when referring to any size, relative dimensions, etc., it should be considered that, even without a specific description, the numerical values ​​of components or features, or corresponding information (e.g., levels, ranges, etc.), include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.). In addition, the term "can" fully encompasses all the meanings of the term "able to".

[0039] Features of the various embodiments of this disclosure may be linked or combined with each other in part or in whole, and may be technically driven and interoperable with each other in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other, or may be implemented together in an interdependent relationship.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant field, and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined herein. For example, the terms “component” or “unit” may be applied, for example, to a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions as would be understood by one of ordinary skill in the art.

[0041] In the following, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. All components of each display panel and each display device including it, according to all embodiments of the present disclosure, are operatively connected and configured.

[0042] Figure 1 A system diagram of a display device according to an embodiment of the present disclosure is illustrated schematically.

[0043] Reference Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110 for displaying images and one or more optical electronic devices (not shown).

[0044] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images. In this case, the display area DA may be referred to as the effective area.

[0045] Multiple sub-pixels can be arranged in the display area DA, and various signal lines for driving the multiple sub-pixels can be arranged.

[0046] The non-display area NDA can be the area outside the display area DA. Various signal lines can be arranged in the non-display area NDA, and various drive circuits can be connected to various signals. The non-display area NDA can be bent to make it invisible from the front, or it can be covered by a housing (not shown). The non-display area NDA can also be called a border or border area.

[0047] In the display device 100 according to an embodiment of the present disclosure, one or more optical electronic devices may be electronic components located below the display panel 110 (e.g., opposite to the viewing surface).

[0048] Light can enter the front of the display panel 110 (e.g., the viewing surface), pass through the display panel 110, and be transmitted to one or more optical electronics located below the display panel 110 (e.g., opposite the viewing surface).

[0049] One or more optical electronic devices may be means of receiving light passing through the display panel 110 and performing a predetermined function based on the received light. For example, one or more optical electronic devices may include one or more of an imaging device such as a camera (or image sensor), a detection sensor such as a proximity sensor, and an illuminance sensor, but this disclosure is not limited thereto.

[0050] In the display panel 110 according to an embodiment of the present disclosure, the display area DA may include a normal area NA and one or more optical areas OA1 and OA2.

[0051] One or more optical regions OA1 and OA2 may be regions that overlap with one or more optoelectronic devices.

[0052] The display area DA may include a normal area NA and a first optical area OA1. Here, at least a portion of the first optical area OA1 may overlap with a first optical electronic device.

[0053] In the display device 100 according to the embodiments of the present disclosure, if the first optical electronic device that is not exposed to the outside and is hidden under the display panel 110 is a camera, then the display device 100 according to the embodiments of the present disclosure may be referred to as a display that applies under-display camera (UDC) technology.

[0054] Therefore, in the case of the display device 100 according to the embodiments of the present disclosure, since it is not necessary to form a notch or camera hole for camera exposure in the display panel 110, the area of ​​the display area DA may not be reduced.

[0055] Therefore, since it is not necessary to form a notch or camera hole in the display panel 110 for camera exposure, the size of the bezel area can be reduced and design constraints can be eliminated, thereby increasing design freedom.

[0056] In the display device 100 according to the embodiments of the present disclosure, even if one or more optical electronic devices are hidden and positioned behind the display panel 110, one or more optical electronic devices still need to receive light normally and perform their respective functions normally.

[0057] Furthermore, in the display device 100 according to the embodiments of the present disclosure, even if one or more optical electronic devices are hidden behind the display panel 110 and overlap with the display area DA, normal image display can still be performed in one or more optical areas OA1 and OA2 that overlap with one or more optical electronic devices in the display area DA.

[0058] Furthermore, the display device 100 according to embodiments of the present disclosure may include a display panel 110 and a display driving circuit as components for image display.

[0059] The display driving circuit may include a gating driving circuit 120, a data driving circuit 130, and a display controller 140 as circuits for driving the display panel 110.

[0060] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. In addition, the display panel 110 may also include various types of signal lines for driving the plurality of sub-pixels SP.

[0061] The display device 100 according to the embodiments of the present disclosure may be a liquid crystal display device, or it may be a self-emissive display device in which the display panel 110 emits its own light. In the case where the display device 100 according to the embodiments of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0062] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting element is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting element is implemented as an inorganic-based light-emitting diode. As yet another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which the light-emitting element is implemented as a quantum dot, where a quantum dot is a self-emissive semiconductor crystal.

[0063] The structure of each subpixel in the plurality of subpixels SP may vary depending on the type of display device 100. For example, if the display device 100 is a self-emissive display device in which the subpixels SP emit their own light, each subpixel SP may include a self-emissive light-emitting element, one or more transistors, and one or more capacitors.

[0064] For example, various types of signal lines may include multiple data lines DL that transmit data signals (also known as data voltages or image signals) and multiple gating lines GL that transmit gating signals (also known as scan signals).

[0065] Multiple data lines DL and multiple gating lines GL can intersect each other. Each of the multiple data lines DL can be arranged while extending along a first direction. Each of the multiple gating lines GL can be arranged while extending along a second direction.

[0066] Here, the first direction can be the column direction and the second direction can be the row direction. Alternatively, the first direction can be the row direction and the second direction can be the column direction. For ease of description, the following describes an example in which each of the plurality of data lines DL is set along the column direction and each of the plurality of strobe lines GL is set along the row direction, but this disclosure is not limited thereto.

[0067] The data driving circuit 130 can be a circuit for driving multiple data lines DL, and can output data signals to the multiple data lines DL. The gating driving circuit 120 can be a circuit for driving multiple gating lines GL, and can output gating signals to the multiple gating lines GL.

[0068] The display controller 140 is a device for controlling the data drive circuit 130 and the gating drive circuit 120, and can control the driving timing of multiple data lines DL and multiple gating lines GL.

[0069] The display controller 140 can provide a data drive control signal DCS to the data drive circuit 130 to control the data drive circuit 130, and can provide a gating drive control signal GCS to the gating drive circuit 120 to control the gating drive circuit 120.

[0070] The display controller 140 can receive input image data from the host system 200 and can provide image data Data to the data drive circuit 130 based on the input image data.

[0071] The data drive circuit 130 can provide data signals to multiple data lines DL according to the drive timing control of the display controller 140.

[0072] The data drive circuit 130 can receive digital image data Data from the display controller 140, convert the received image data Data into analog data signals, and output the converted data signals to multiple data lines DL.

[0073] The gating drive circuit 120 can provide gating signals to multiple gating lines GL according to the timing control of the display controller 140. The gating drive circuit 120 can receive a first gating voltage corresponding to the on-level voltage and a second gating voltage corresponding to the off-level voltage together with various gating drive control signals GCS, generate gating signals (e.g., scan signals or light emission control signals), and provide the generated gating signals to the multiple gating lines GL.

[0074] For example, the data drive circuit 130 can be connected to the display panel 110 via tape auto-bonding (TAB), connected to the bonding pads of the display panel 110 via chip on glass (COG) or chip on panel (COP), or implemented and connected to the display panel 110 via chip on film (COF).

[0075] The gate drive circuit 120 can be connected to the display panel 110 via the tape automatic bonding (TAB) method, to the bonding pads of the display panel 110 via the chip on glass (COG) or chip on panel (COP) method, or to the display panel 110 via the chip on film (COF) method.

[0076] Alternatively, the gate drive circuit 120 may be formed in the non-display area NDA of the display panel 110 via a gate-in-panel (GIP) type. The gate drive circuit 120 may be disposed on or connected to the substrate. For example, if the gate drive circuit 120 is of the GIP type, it may be disposed in the non-display area NDA of the substrate. If the gate drive circuit 120 is of the chip-on-glass (COG) type, chip-on-film (COF) type, etc., it may be connected to the substrate.

[0077] Furthermore, at least one of the data driving circuit 130 and the gating driving circuit 120 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 130 and the gating driving circuit 120 may be configured not to overlap with the sub-pixel SP, or may be configured to partially or completely overlap with the sub-pixel SP.

[0078] The data driving circuit 130 may be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method, panel design method, etc., the data driving circuit 130 may be connected to both sides of the display panel 110 (e.g., the top and bottom sides), or may be connected to two or more of the four sides of the display panel 110.

[0079] The gating drive circuit 120 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method, panel design method, etc., the gating drive circuit 120 can be connected to both sides of the display panel 110 (e.g., the left and right sides), or it can be connected to two or more of the four sides of the display panel 110.

[0080] The display controller 140 can be implemented as a component separate from the data drive circuit 130, or it can be implemented as an integrated circuit by integrating it with the data drive circuit 130.

[0081] The display controller 140 may be a timing controller used in conventional display technologies, or a control device capable of performing other control functions, including a timing controller, or a control device other than a timing controller or circuitry within a control device. The display controller 140 may be implemented as various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0082] The display controller 140 can be mounted on a printed circuit board or flexible printed circuit and can be electrically connected to the data drive circuit 130 and the gating drive circuit 120 via the printed circuit board or flexible printed circuit.

[0083] The display controller 140 can send and receive signals with the data drive circuit 130 via one or more predefined interfaces. Here, for example, the interface may include a low-voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI) interface, a serial peripheral (SP) interface, etc.

[0084] The display device 100 according to embodiments of the present disclosure may include a touch sensor and a touch circuit, the touch circuit sensing the touch sensor to detect the occurrence of a touch by a touch object such as a finger or a pen or to detect the touch position, so as to provide touch sensing functionality in addition to image display functionality.

[0085] The touch circuit may include a touch drive circuit 160 that drives and senses touch sensors to generate and output touch sensing data, and a touch controller 170 that uses the touch sensing data to detect the occurrence or location of a touch.

[0086] The touch sensor may include multiple touch electrodes. The touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes to the touch driving circuitry 160.

[0087] The touch sensor may exist on the exterior of the display panel 110 in the form of a touch panel, or it may exist inside the display panel 110. If the touch sensor exists on the exterior of the display panel 110 in the form of a touch panel, the touch sensor may be referred to as an external type. If the touch sensor is external type, the touch panel and the display panel 110 may be manufactured separately and combined during the assembly process. An external type touch panel may include a substrate for the touch panel and a plurality of touch electrodes on the substrate for the touch panel.

[0088] If the touch sensor is present inside the display panel 110, the touch sensor can be formed on the substrate SUB together with the signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0089] The touch driving circuit 160 can provide a touch driving signal to at least one of a plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0090] Touch circuits can perform touch sensing using either self-capacitance sensing or mutual capacitance sensing.

[0091] If the touch circuit performs touch sensing in a self-capacitance sensing manner, the touch circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.).

[0092] According to the self-capacitance sensing method, each of the multiple touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 160 can drive all or some of the multiple touch electrodes and sense all or some of the multiple touch electrodes.

[0093] If the touch circuit performs touch sensing using mutual capacitance sensing, then the touch circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0094] Based on the mutual capacitance sensing method, multiple touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 160 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0095] The touch driving circuit 160 and touch controller 170 included in the touch circuit can be implemented as separate devices or as a single device. Furthermore, the touch driving circuit 160 and data driving circuit 130 can be implemented as separate devices or as a single device.

[0096] The display device 100 may also include a power supply circuit that provides various types of power to the display driving circuit and / or touch circuit.

[0097] The display device 100 according to the embodiments of this disclosure may be a mobile terminal such as a smartphone or tablet, or a monitor or television (TV) of various sizes, and may be a display of various types and sizes capable of displaying information or images, but is not limited thereto.

[0098] As described above, the display area DA in the display panel 110 may include a normal area NA and one or more optical areas OA1 and OA2.

[0099] The normal region NA and one or more optical regions OA1 and OA2 can be areas capable of displaying an image. However, the normal region NA can be a region where no light-transmitting structure is formed, and one or more optical regions OA1 and OA2 can be regions in which a light-transmitting structure is formed.

[0100] As described above, the display area DA in the display panel 110 may include one or more optical areas OA1 and OA2 and a normal area NA, but for ease of explanation, it is assumed that the display area DA includes both the first optical area OA1 and the second optical area OA2.

[0101] Figure 2 An equivalent circuit of a sub-pixel in a display panel according to an embodiment of the present disclosure is illustrated as an example.

[0102] Reference Figure 2 In the display panel 110 according to an embodiment of the present disclosure, each sub-pixel SP arranged in the normal area NA, the first optical area OA1 and the second optical area OA2 included in the display area DA may include a light-emitting element ED, a driving transistor DRT for driving the light-emitting element ED, a scanning transistor SCT for sending a data voltage Vdata to a first node N1 of the driving transistor DRT, and a storage capacitor Cst for maintaining a constant voltage during a frame.

[0103] The driving transistor DRT may include a first node N1 to which a data voltage Vdata can be applied, a second node N2 electrically connected to the light-emitting element ED, and a third node N3 to which a driving voltage ELVDD is applied from the driving voltage line DVL. In the driving transistor DRT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node.

[0104] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The anode electrode AE ​​may be a pixel electrode disposed in each sub-pixel SP and may be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel SP. The cathode electrode CE may be a common electrode arranged together to multiple sub-pixels SP and may be supplied with a base voltage ELVSS.

[0105] For example, the anode electrode AE ​​can be a pixel electrode, and the cathode electrode CE can be a common electrode. Alternatively, the anode electrode AE ​​can be a common electrode, and the cathode electrode CE can be a pixel electrode. In the following description, for ease of explanation, it is assumed that the anode electrode AE ​​is a pixel electrode and the cathode electrode CE is a common electrode, but this disclosure is not limited thereto.

[0106] For example, the light-emitting element ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting element. In this case, if the light-emitting element ED is an organic light-emitting diode, the light-emitting layer EL in the light-emitting element ED may include an organic light-emitting layer containing organic materials.

[0107] The scanning transistor SCT can be turned on and off by the scanning signal SCAN, which is a gating signal applied by the gating line GL. The scanning transistor SCT can be electrically connected between the first node N1 of the driving transistor DRT and the data line DL.

[0108] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0109] like Figure 2 As shown, each sub-pixel SP can have a 2T1C structure including two transistors (e.g., DRT and SCT) and one capacitor Cst, and may also include one or more transistors or one or more capacitors depending on the situation. For example, a sub-pixel can have an 8T1C structure including 8 transistors and 1 capacitor. For another example, a sub-pixel can have a 6T2C structure including 6 transistors and 2 capacitors. For yet another example, a sub-pixel can have a 7T1C structure including 7 transistors and 1 capacitor.

[0110] The storage capacitor Cst can be an external capacitor intentionally designed outside the driving transistor DRT, rather than a parasitic capacitor (e.g., Cgs, Cgd) that may exist between the first node N1 and the second node N2 of the driving transistor DRT.

[0111] Each of the driving transistor DRT and the scanning transistor SCT can be an n-type transistor or a p-type transistor. Depending on the structure of the sub-pixel circuit SPC, the type and number of gating lines or gating signals provided to the sub-pixel SP may vary.

[0112] Since the circuit elements (specifically, the light-emitting elements ED) in each sub-pixel SP are susceptible to external moisture or oxygen, an encapsulation layer ENCAP can be provided on the display panel 110 to prevent or reduce the penetration of external moisture or oxygen into the circuit elements (specifically, the light-emitting elements ED). The encapsulation layer ENCAP can be configured to cover the light-emitting elements ED.

[0113] Figure 3 An example is illustrated of the arrangement of sub-pixels in three regions included in the display area of ​​a display panel according to an embodiment of the present disclosure.

[0114] Reference Figure 3 In the display panel 110 according to an embodiment of the present disclosure, a plurality of sub-pixels SP may be disposed in each of the normal area NA, the first optical area OA1 and the second optical area OA2 included in the display area DA.

[0115] For example, multiple sub-pixels SP may include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light.

[0116] Therefore, each of the normal region NA, the first optical region OA1, and the second optical region OA2 may include the light-emitting region EA of the red sub-pixel, the light-emitting region EA of the green sub-pixel, and the light-emitting region EA of the blue sub-pixel.

[0117] The normal region NA may not include light-transmitting structures, but may include the light-emitting region EA.

[0118] However, the first optical region OA1 and the second optical region OA2 may include not only the light-emitting region EA, but also the light-transmitting structure.

[0119] Therefore, the first optical region OA1 may include the light-emitting region EA and the first light-transmitting region TA1, and the second optical region OA2 may include the light-emitting region EA and the second light-transmitting region TA2.

[0120] The luminescent region EA and the translucent regions TA1 and TA2 can be distinguished based on whether they are translucent or not. For example, the luminescent region EA can be an opaque region, while the translucent regions TA1 and TA2 can be translucent regions.

[0121] Furthermore, the light-emitting region EA and the light-transmitting regions TA1 and TA2 can be distinguished based on whether a specific metal layer is formed. For example, if the specific metal layer is a cathode electrode CE, the cathode electrode CE can be formed in the light-emitting region EA, while the cathode electrode CE may not be formed in the light-transmitting regions TA1 and TA2. In another example, if the specific metal layer is a light-shielding layer, the light-shielding layer can be formed in the light-emitting region EA, while the light-shielding layer may not be formed in the light-transmitting regions TA1 and TA2.

[0122] Since the first optical region OA1 includes the first light-transmitting region TA1 and the second optical region OA2 includes the second light-transmitting region TA2, both the first optical region OA1 and the second optical region OA2 are regions through which light can pass.

[0123] The transmittance (e.g., light transmittance level) of the first optical region OA1 and the transmittance of the second optical region OA2 can be the same.

[0124] In this case, the first light-transmitting region TA1 of the first optical region OA1 and the second light-transmitting region TA2 of the second optical region OA2 may have the same shape or size. Alternatively, even if the first light-transmitting region TA1 of the first optical region OA1 and the second light-transmitting region TA2 of the second optical region OA2 have different shapes or sizes, the proportion of the first light-transmitting region TA1 in the first optical region OA1 and the proportion of the second light-transmitting region TA2 in the second optical region OA2 may be the same.

[0125] Alternatively, the transmittance (e.g., light transmittance or light transmittance degree) of the first optical region OA1 and the transmittance of the second optical region OA2 may be different from each other.

[0126] In this case, the first light-transmitting region TA1 of the first optical region OA1 and the second light-transmitting region TA2 of the second optical region OA2 may have different shapes or sizes. Alternatively, even if the first light-transmitting region TA1 of the first optical region OA1 and the second light-transmitting region TA2 of the second optical region OA2 have the same shape or size, the proportion of the first light-transmitting region TA1 in the first optical region OA1 and the proportion of the second light-transmitting region TA2 in the second optical region OA2 may be different from each other.

[0127] For example, if the first optical electronic device overlapping with the first optical region OA1 is a camera and the second optical electronic device overlapping with the second optical region OA2 is a detection sensor, then the camera may require a greater amount of light than the detection sensor.

[0128] Therefore, the transmittance or light transmittance of the first optical region OA1 can be higher than that of the second optical region OA2.

[0129] In this case, the size of the first light-transmitting area TA1 of the first optical region OA1 can be larger than the size of the second light-transmitting area TA2 of the second optical region OA2. Alternatively, even if the first light-transmitting area TA1 of the first optical region OA1 and the second light-transmitting area TA2 of the second optical region OA2 have the same size, the proportion of the first light-transmitting area TA1 in the first optical region OA1 can be greater than the proportion of the second light-transmitting area TA2 in the second optical region OA2.

[0130] In the following description, for ease of explanation, the case in which the transmittance or light transmittance of the first optical region OA1 is higher than that of the second optical region OA2 will be used as an example.

[0131] Furthermore, in the embodiments of this disclosure, the light-transmitting areas TA1 and TA2 may also be referred to as transparent areas, and the light transmittance or light transmittance may also be referred to as transparency.

[0132] Furthermore, in the embodiments of this disclosure, it is assumed that the first optical region OA1 and the second optical region OA2 are located above the display region DA of the display panel 110 and are arranged side by side.

[0133] The horizontal display area with a first optical region OA1 and a second optical region OA2 is called the first horizontal display area HA1, and the horizontal display area without a first optical region OA1 and a second optical region OA2 is called the second horizontal display area HA2.

[0134] The first horizontal display area HA1 may include a normal area NA, a first optical area OA1, and a second optical area OA2. The second horizontal display area HA2 may include only the normal area NA.

[0135] Figure 4 An example of a cross-section of a display area in a display panel according to an embodiment of the present disclosure is shown.

[0136] Here, the normal region NA is shown, excluding the optical region OA where the optoelectronic devices are located.

[0137] Reference Figure 4 According to embodiments of the present disclosure, the display panel 110 may include a substrate SUB, a driving transistor DRT, a planarization layer PLN, a light-emitting element ED, an encapsulation layer ENCAP, and a touch layer.

[0138] The substrate SUB may include a first substrate SUB1, a substrate insulating film IPD, and a second substrate SUB2. The substrate insulating film IPD may be located between the first substrate SUB1 and the second substrate SUB2.

[0139] By configuring the substrate SUB to have a first substrate SUB1, a substrate insulating film IPD, and a second substrate SUB2, moisture penetration can be prevented or reduced.

[0140] For example, the first substrate SUB1 and the second substrate SUB2 can be polyimide (PI) substrates. The first substrate SUB1 can be referred to as a primary PI substrate, and the second substrate SUB2 can be referred to as a secondary PI substrate.

[0141] Various patterns (e.g., ACT, SD1, and GATE) for forming transistors such as driving transistors DRT, various insulating films (e.g., MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, and PAS0), and various metal patterns (e.g., TM, GM, ML1, and ML2) can be disposed on the substrate SUB.

[0142] The multi-buffer layer MBUF can be disposed on the second substrate SUB2, and the first active buffer layer ABUF1 can be disposed on the multi-buffer layer MBUF.

[0143] The first metal layer ML1 and the second metal layer ML2 can be disposed on the first active buffer layer ABUF1. Here, the first metal layer ML1 and the second metal layer ML2 can be a light-shielding layer LS for shielding light.

[0144] The second active buffer layer ABUF2 can be disposed on the first metal layer ML1 and the second metal layer ML2. The active layer ACT for driving the transistor DRT can be disposed on the second active buffer layer ABUF2.

[0145] The gate insulating film GI can be configured to simultaneously cover the active layer ACT.

[0146] The gate electrode (GATE) of the driving transistor (DRT) can be disposed on the gate insulating film (GI). In this case, at a location different from where the driving transistor (DRT) is formed, the gate material layer (GM) can be disposed together with the gate electrode (GATE) of the driving transistor (DRT) on the gate insulating film (GI).

[0147] The first interlayer insulating film ILD1 can be configured to cover the gate electrode GATE and the gate material layer GM. A metal pattern TM can be formed on the first interlayer insulating film ILD1. The metal pattern TM can be located at a different position than the formation location of the driving transistor DRT.

[0148] The second interlayer insulating film ILD2 can be configured to simultaneously cover the metal pattern TM on the first interlayer insulating film ILD1.

[0149] Two first source-drain electrode patterns SD1 can be disposed on the second interlayer insulating film ILD2. One of the two first source-drain electrode patterns SD1 is the source node of the driving transistor DRT, and the other is the drain node of the driving transistor DRT.

[0150] The two first source-drain electrode patterns SD1 can be electrically connected to one side and the other side of the active layer ACT through the contact holes of the second interlayer insulating film ILD2, the first interlayer insulating film ILD1 and the gate insulating film GI, respectively.

[0151] Furthermore, the second interlayer insulating film ILD2 may include a 2-1 interlayer insulating film ILD2-1 and a 2-2 interlayer insulating film ILD2-2. The 2-1 interlayer insulating film ILD2-1 may be configured to simultaneously cover the metal pattern TM. The 2-2 interlayer insulating film ILD2-2 may be located on the 2-1 interlayer insulating film ILD2-1.

[0152] The portion of the active layer ACT that overlaps with the gate electrode GATE can be a channel region. One of the two first source / drain electrode patterns SD1 can be connected to one side of the channel region in the active layer ACT, and the other of the two first source / drain electrode patterns SD1 can be connected to the other side of the channel region in the active layer ACT.

[0153] The passivation layer PAS0 can be configured to simultaneously cover both first source / drain electrode patterns SD1. The planarization layer PLN can be disposed on the passivation layer PAS0.

[0154] The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2. The planarization layer PLN may be formed from an organic insulating material such as acrylic resin.

[0155] The first planarization layer PLN1 can be disposed on the passivation layer PAS0.

[0156] The second source / drain electrode pattern SD2 can be disposed on the first planarization layer PLN1. The second source / drain electrode pattern SD2 can be connected to one of the two first source / drain electrode patterns SD1 (corresponding to) through the contact holes of the first planarization layer PLN1. Figure 3 The second node N2 of the driving transistor DRT in the sub-pixel SP.

[0157] The second planarization layer PLN2 can be configured to simultaneously cover the second source / drain electrode pattern SD2. The light-emitting element ED can be disposed on the second planarization layer PLN2.

[0158] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE.

[0159] The anode electrode AE ​​can be disposed on the second planarization layer PLN2. The anode electrode AE ​​can be electrically connected to the second source / drain electrode pattern SD2 through the contact holes of the second planarization layer PLN2.

[0160] The dam can be configured to simultaneously cover a portion of the anode electrode AE. The portion of the dam corresponding to the light-emitting area EA of the sub-pixel SP can be opened or removed.

[0161] A portion of the anode electrode AE ​​may be exposed to the opening (or portion of the opening) of the dam BANK.

[0162] The luminescent layer (EL) may be located on the side of the bank and on the opening (or portion of the opening) of the bank. All or part of the luminescent layer (EL) may be located between adjacent banks. The luminescent layer (EL) may include an organic membrane.

[0163] In the opening of the dam BANK, the light-emitting layer EL can contact the anode electrode AE. The cathode electrode CE can be disposed on the light-emitting layer EL.

[0164] The encapsulation layer ENCAP can be set on the light-emitting element ED.

[0165] The encapsulation layer ENCAP can have a single-layer structure or a multi-layer structure. For example, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

[0166] For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 can be inorganic films, and the second encapsulation layer PCL can be an organic film. Among the first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2, the second encapsulation layer PCL can be the thickest. Therefore, the second encapsulation layer PCL can be used as a planarization layer.

[0167] The first encapsulation layer PAS1 can also be called the first inorganic encapsulation layer, the second encapsulation layer PCL can also be called the organic encapsulation layer, and the third encapsulation layer PAS2 can also be called the second inorganic encapsulation layer.

[0168] The first encapsulation layer PAS1 can be disposed on the cathode electrode CE and can be positioned closest to the light-emitting element ED. The first encapsulation layer PAS1 can be formed of an inorganic insulating material capable of low-temperature deposition. For example, the first encapsulation layer PAS1 can be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Because the first encapsulation layer PAS1 is deposited in a low-temperature atmosphere, it can prevent or reduce damage to the light-emitting layer EL, including organic materials susceptible to high-temperature atmospheres, during the deposition process.

[0169] The second encapsulation layer PCL can be formed to have a smaller area than the first encapsulation layer PAS1. In this case, the second encapsulation layer PCL can be formed to expose both ends of the first encapsulation layer PAS1. The second encapsulation layer PCL can serve as a buffer to alleviate the stress between the layers caused by the bending of the display device 100, and can also be used to enhance planarization performance.

[0170] For example, the second encapsulation layer PCL can be formed from acrylic resin, epoxy resin, polyimide, polyethylene, or silicon carbide (SiOC), and can also be formed from organic insulating materials. For example, the second encapsulation layer PCL can be formed by inkjet printing.

[0171] A third encapsulation layer, PAS2, may be formed on the second encapsulation layer, PCL, to cover the upper and side surfaces of the second encapsulation layer, PCL, and the first encapsulation layer, PAS1. The third encapsulation layer, PAS2, may reduce, minimize, or block external moisture or oxygen from penetrating into the first encapsulation layer, PAS1, and the second encapsulation layer, PCL.

[0172] For example, the third encapsulation layer PAS2 can be formed from an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0173] Furthermore, the display device 100 of this disclosure may have a touch sensor TS formed on the encapsulation layer ENCAP to detect the touch of a user's finger or pen.

[0174] If the touch sensor TS is the type built into the display panel 110, the touch sensor TS can be disposed on the encapsulation layer ENCAP. The touch sensor structure will be described in detail below.

[0175] The touch buffer film T-BUF can be set on the encapsulation layer ENCAP.

[0176] The touch sensor TS can be set on the touch buffer membrane T-BUF.

[0177] The touch sensor TS may include a touch sensor metal TSM and a bridging metal BRG located in different layers.

[0178] The touch sensor metal TSM and bridging metal BRG can be formed from a three-layer structure of Ti / Al / Ti.

[0179] The interlayer insulating film (T-ILD) can be placed between the touch sensor metal (TSM) and the bridging metal (BRG).

[0180] The touch interlayer insulating film (T-ILD) can be formed from inorganic materials such as silicon nitride (SiNx) or silicon oxide (SiOx). In this case, the touch interlayer insulating film (T-ILD) can be formed from inorganic materials such as silicon oxide (SiOx) to improve touch performance.

[0181] For example, a touch sensor TS may include a first touch sensor metal, a second touch sensor metal, and a third touch sensor metal positioned adjacent to each other.

[0182] If a third touch sensor metal exists between the first touch sensor metal and the second touch sensor metal, and the first touch sensor metal and the second touch sensor metal are to be electrically connected to each other, then the first touch sensor metal and the second touch sensor metal can be electrically connected to each other through bridging metals BRG in different layers.

[0183] The bridging metal BRG can be insulated from the third touch sensor metal via the interlayer insulating film T-ILD.

[0184] When a touch sensor TS is formed on a display panel 110, chemical solutions (e.g., developer or etchant) or moisture used in the process may be generated from the outside.

[0185] Because the touch sensor TS is mounted on the touch buffer film T-BUF, chemical solutions or moisture can be prevented or reduced from penetrating into the light-emitting layer EL, which contains organic matter, during the manufacturing process of the touch sensor TS.

[0186] Therefore, the touch buffer film T-BUF can prevent or reduce damage to the light-emitting layer EL, which is susceptible to liquids or moisture.

[0187] The touch buffer film (T-BUF) can be formed at low temperatures (e.g., 100°C) or lower, and can be formed from organic insulating materials with low dielectric constants to prevent or reduce damage to the light-emitting layer (EL), which includes organic materials susceptible to high temperatures. For example, the touch buffer film (T-BUF) can be formed from acrylic, epoxy, or siloxane-based materials.

[0188] If the display device 100 is bent, the encapsulation layer ENCAP may be damaged due to bending, and the touch sensor metal TSM located on the touch buffer film T-BUF may break. Even if the display device 100 is bent, the touch buffer film T-BUF, which has planarization properties by using organic insulating materials, can prevent or reduce damage to the encapsulation layer ENCAP, or prevent or reduce breakage of the touch sensor metal TSM or bridging metal BRG.

[0189] The protective layer PAC can be arranged to simultaneously cover the touch sensor TS. The protective layer PAC can be an organic insulating film.

[0190] In the display panel 110, the light-emitting element ED may be damaged by moisture flowing into the light-emitting layer EL through the through-hole TH.

[0191] Furthermore, moisture generated during the process of forming the touch sensor TS or flowing in from the outside may flow into the encapsulation layer ENCAP through the upper interlayer insulating film T-ILD and touch buffer film T-BUF, damaging the light-emitting element ED.

[0192] The display panel 110 disclosed herein can prevent moisture from flowing in through the through-hole TH by forming a light-emitting layer break pattern that breaks the light-emitting layer EL between the through-hole TH and the normal area NA.

[0193] Figure 5 The planar structure of the optical region in a display panel according to an embodiment of the present disclosure is illustrated.

[0194] Reference Figure 5 According to embodiments of the present disclosure, the display panel 110 may include an optical region OA within the display area DA.

[0195] The optical region OA can be one of the first optical region OA1 or the second optical region OA2 described above.

[0196] The optical region OA may include the through hole TH and the surrounding area SA around the through hole TH.

[0197] The light-emitting layer disconnect pattern ECP used to prevent or reduce moisture penetration can be located in the peripheral area SA.

[0198] Through-holes (TH) can be formed by removing substrate along trim lines. The shape of a through-hole (TH) can be circular, but it can also have various shapes such as ellipse, square, hexagon, or octagon.

[0199] The light-emitting layer disconnect pattern ECP can include one or more patterns in the surrounding area SA to block the moisture penetration path along the light-emitting layer EL.

[0200] In addition, an inner dam can be additionally formed between the light-emitting layer disconnect pattern ECP and the via TH to separate the light-emitting layer disconnect pattern ECP from the via TH.

[0201] An outer dam (not shown) may be further positioned outside the first light-emitting layer break pattern ECP1 within the normal region NA. The outer dam may be configured to prevent or reduce the overflow of the encapsulation layer ENCAP outside the normal region NA.

[0202] The light-emitting layer disconnect pattern (ECP) can have a closed curve shape corresponding to and surrounding the via TH. The ECP can have a different closed curve shape than the via TH, or it can have the same shape but a different size.

[0203] Here, an example is shown where the light-emitting layer disconnect pattern ECP and the via TH have the same shape and are arranged at a certain interval.

[0204] The optical region OA may include the through-hole TH and the peripheral region SA, and the normal region NA may be located outside the peripheral region SA.

[0205] Optical electronics may be located in a through hole TH below the display panel 110, and the optical electronics may be configured to overlap with at least a portion of the through hole TH.

[0206] Figure 6 This is a cross-sectional view of the normal area and the optical area in a display panel according to an embodiment of the present disclosure.

[0207] Reference Figure 6 According to embodiments of the present disclosure, the display panel 110 may include a light-emitting layer disconnect pattern ECP to prevent or reduce moisture from flowing from the via TH where the optical electronics 11 is located to the normal area NA where sub-pixels are formed.

[0208] The light-emitting layer disconnect pattern ECP can be formed at least once between the via TH and the normal region NA.

[0209] The light-emitting layer disconnect pattern ECP may include sidewall structures (e.g., two sidewall structures) and recessed regions between the sidewall structures that separate them.

[0210] The luminescent layer EL formed in the optical region OA can be physically divided into a luminescent layer located on the sidewall structure and a luminescent layer located in the recessed region through the recessed region of the luminescent layer disconnect pattern ECP. For example, as Figure 6 As shown, the light-emitting layer located on the sidewall structure and the light-emitting layer located on the recessed region are spaced apart from each other and electrically separated by the recessed region of the light-emitting layer disconnect pattern ECP.

[0211] Therefore, moisture flowing in through the through-hole TH can be blocked by the recessed area of ​​the light-emitting layer disconnected pattern ECP, so as not to be transmitted to the normal area NA.

[0212] In this case, the light-emitting layer disconnected pattern ECP may include a first shielding layer SM1 for preventing or reducing moisture penetration in the lower direction, a second shielding layer SM2 for preventing or reducing moisture penetration in the lateral direction, and a third shielding layer SM3 for preventing or reducing moisture penetration in the upper direction.

[0213] The first shielding layer SM1 may be formed of the same material as the gate electrode GATE of the transistor constituting the normal region NA. For example, the first shielding layer SM1 may be formed of titanium (Ti). In addition, the first shielding layer SM1 may have protrusions formed on its outer surface to support the second shielding layer SM2.

[0214] The second shielding layer SM2 may be formed of the same material as the first source-drain electrode pattern SD1 of the transistor constituting the normal region NA. The second shielding layer SM2 may be formed of a titanium / aluminum / titanium (Ti / Al / Ti) laminated metal structure.

[0215] The third shielding layer SM3 may be formed of the same material as the second source-drain electrode pattern SD2 of the transistor constituting the normal region NA. The third shielding layer SM3 may be formed of a titanium / aluminum / titanium (Ti / Al / Ti) laminated metal structure.

[0216] Furthermore, the light-emitting layer disconnect pattern ECP may include an undercut insulating layer IM formed inside the second shielding layer SM2 and below the third shielding layer SM3 for effective disconnect insulation of the light-emitting layer EL. The disconnect insulating layer IM may be formed of the same material as the first planarization layer PLN1 of the normal region NA.

[0217] In this case, the outer side of the light-emitting layer disconnected pattern ECP can be formed by a double-layer structure of the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2.

[0218] In this case, the first interlayer insulating film ILD1 can be formed of an inorganic material such as silicon oxide or silicon nitride, and the second interlayer insulating film ILD2 located on the upper side of the first interlayer insulating film ILD1 can be formed of an organic material.

[0219] Since the via TH where the optoelectronic device 11 is located is adjacent to the outer area of ​​the display panel 110, flexibility may be required. In this case, the thickness of the inorganic interlayer insulating film is limited because it is relatively fragile in terms of flexibility and there is a risk of conductivity if its thickness is too large.

[0220] Therefore, by forming a first interlayer insulating film ILD1 with inorganic materials and laminating a second interlayer insulating film ILD2 with a thickness greater than that of the first interlayer insulating film ILD1, the flexibility properties can be effectively ensured.

[0221] The thickness of the second interlayer insulating film ILD2, which has organic materials, can be 1 to 5 times the thickness of the first interlayer insulating film ILD1, which has inorganic materials, thereby improving flexibility and preventing or reducing conductive defects.

[0222] In this way, the display panel 110 of this disclosure can improve the moisture barrier effect and flexibility by forming the light-emitting layer disconnect pattern ECP along the peripheral area SA outside the through hole TH.

[0223] Figures 7 to 13 These are cross-sectional views illustrating the manufacturing process of a display panel according to embodiments of the present disclosure.

[0224] First, refer to Figure 7 In the display panel 110 according to an embodiment of the present disclosure, a buffer layer BUF may be formed on the substrate SUB.

[0225] The substrate SUB may include a first substrate, a substrate insulating film, and a second substrate, and the substrate insulating film may be located between the first substrate and the second substrate.

[0226] An active layer ACT can be set on the buffer layer BUF to form transistors such as driving transistors DRT.

[0227] The gate insulating film GI can be configured to simultaneously cover the active layer ACT.

[0228] The gate electrode (GATE) of the driving transistor (DRT) can be disposed on the gate insulating film (GI) in the normal region NA. In this case, a gate material layer (GM) of the same material as the gate electrode (GATE) can be disposed on the gate insulating film (GI) in the peripheral region SA of the via TH.

[0229] The gate material layer GM of the peripheral region SA can be a layer used to form the first shielding layer SM1 to prevent or reduce the penetration of moisture in the downward direction.

[0230] A first interlayer insulating film ILD1 can be provided to cover the gate electrode GATE in the normal region NA and the gate material layer GM in the peripheral region SA.

[0231] In addition, a second interlayer insulating film ILD2 can be disposed on the first interlayer insulating film ILD1.

[0232] In this case, the first interlayer insulating film ILD1 can be made of inorganic materials such as silicon oxide or silicon nitride, and the second interlayer insulating film ILD2 can be made of organic materials.

[0233] Since the via TH where the optoelectronic device 11 is located is adjacent to the outer area of ​​the display panel 110, flexibility may be required. In this case, the inorganic interlayer insulating film is relatively fragile in terms of flexibility, and if its thickness is too large, it may become conductive, thus limiting its thickness.

[0234] Therefore, by forming the thickness of the second interlayer insulating film ILD2 of the organic material to be greater than the thickness of the first interlayer insulating film ILD1 of the inorganic material, the flexibility properties can be effectively ensured.

[0235] The thickness of the second interlayer insulating film ILD2 of organic materials can be formed to be 1 to 5 times the thickness of the first interlayer insulating film ILD1 of inorganic materials.

[0236] Reference Figure 8 A portion of the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 can be etched to form contact holes CNT1 and CNT2.

[0237] The first contact hole CNT1 may be a contact hole for forming the first source / drain electrode pattern SD1 that contacts the active layer ACT in the normal region NA.

[0238] In addition, the second contact hole CNT2 may be a contact hole for forming a second shielding layer SM2 on the first shielding layer SM1 in the peripheral area SA.

[0239] In this case, during the process of forming the second contact hole CNT2 in the peripheral region SA, a portion of the gate material layer GM can be etched together. As a result, the first shielding layer SM1 can be formed as a structure with both ends protruding upwards.

[0240] The first shielding layer SM1, which protrudes upward at both ends, can support the second shielding layer SM2 formed thereon and can effectively prevent moisture from leaking out from the contact portion with the second shielding layer SM2.

[0241] Reference Figure 9 A first source / drain electrode pattern SD1 can be formed on the second interlayer insulating film ILD2 to fill the first contact hole CNT1 in the normal region NA. One of the two first source / drain electrode patterns SD1 can be the source electrode of the driving transistor DRT, and the other can be the drain electrode of the driving transistor DRT.

[0242] The two first source-drain electrode patterns SD1 can be electrically connected to one side and the other side of the active layer ACT through the first contact hole CNT1 of the second interlayer insulating film ILD2, the first interlayer insulating film ILD1 and the gate insulating film GI.

[0243] The portion of the active layer ACT that overlaps with the gate electrode GATE can be a channel region. One of the two first source / drain electrode patterns SD1 can be connected to one side of the channel region in the active layer ACT, and the other of the two first source / drain electrode patterns SD1 can be connected to the other side of the channel region in the active layer ACT.

[0244] In addition, a second shielding layer SM2 can be formed in the surrounding area SA to make contact with a portion of the first shielding layer SM1 through the second contact hole CNT2.

[0245] The first source / drain electrode pattern SD1 and the second shielding layer SM2 can be formed by applying the first source / drain material onto the second interlayer insulating film ILD2 and performing an etching process.

[0246] Therefore, the same material as the first source / drain electrode pattern SD1 can be used and the second shielding layer SM2 can be formed in the same process.

[0247] In this case, the second shielding layer SM2 can be formed as a structure in which the central part is opened by the second contact hole CNT2.

[0248] Reference Figure 10 A first planarization layer PLN1 can be provided to cover the first source / drain electrode pattern SD1 and the second contact hole CNT2.

[0249] The first planarization layer PLN1 is configured to cover the first source / drain electrode pattern SD1 in the normal region NA.

[0250] In addition, the first planarization layer PLN1 may be disposed inside the second contact hole CNT2 to cover the first shielding layer SM1 in the surrounding area SA.

[0251] Reference Figure 11 A second source / drain material SDM2 can be applied to cover the first planarization layer PLN1 in the normal region NA and the surrounding region SA.

[0252] The second source / drain material SDM2 is a metallic material used to form the second source / drain electrode pattern SD2 in the normal region NA and the third shielding layer SM3 in the peripheral region SA.

[0253] Reference Figure 12 A portion of the second source / drain material SDM2 can be etched in the normal region NA to form the second source / drain electrode pattern SD2.

[0254] The second source / drain electrode pattern SD2 can be connected to one of the first source / drain electrode patterns SD1 through the contact holes of the first planarization layer PLN1.

[0255] In addition, a portion of the second source / drain material SDM2 can be etched in the surrounding area SA to form a third shielding layer SM3.

[0256] In the surrounding area SA, the third shielding layer SM3 may be formed on the second interlayer insulating film ILD2 and may be located in the folded portion of the second shielding layer SM2.

[0257] In this case, during the process of etching the second source / drain material SDM2 to form the third shielding layer SM3, the first planarization layer PLN1 beneath the third shielding layer SM3 can be partially etched.

[0258] As a result, the third shielding layer SM3 can protrude into the inner groove above the first planarization layer PLN1, and the first planarization layer PLN1 can support the third shielding layer SM3 above, so that the third shielding layer SM3 and the first planarization layer PLN1 form an undercut structure.

[0259] In this manner, the light-emitting layer break pattern ECP formed in the peripheral area SA may include a first shielding layer SM1 for preventing or reducing moisture penetration in the downward direction, a second shielding layer SM2 for preventing or reducing moisture penetration in the horizontal direction, and a third shielding layer SM3 for preventing or reducing moisture penetration in the upward direction.

[0260] Reference Figure 13 When the surface is ashing while forming the second source / drain electrode pattern SD2 and the third shielding layer SM3, the first planarization layer PLN1 in the area where the third shielding layer SM3 is opened can be removed.

[0261] As a result, the first planarization layer PLN1 remaining below the third shielding layer SM3 can be formed as a disconnected insulating layer IM, which insulates the second shielding layer SM2 below the third shielding layer SM3.

[0262] In this configuration, the disconnected insulating layer IM can support the third shielding layer SM3 on top, thereby forming an undercut structure of the third shielding layer SM3. As a result, due to the undercut structure of the third shielding layer SM3 and the disconnected insulating layer IM, the light-emitting layer formed on the third shielding layer SM3 and the light-emitting layer formed inside the disconnected insulating layer IM can be effectively disconnected or separated.

[0263] Subsequently, the second planarization layer PLN2 can be configured to simultaneously cover the second source / drain electrode pattern SD2. A light-emitting element ED can be disposed on the second planarization layer PLN2.

[0264] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE.

[0265] The anode electrode AE ​​can be disposed on the second planarization layer PLN2. The anode electrode AE ​​can be electrically connected to the second source / drain electrode pattern SD2 through the contact holes of the second planarization layer PLN2.

[0266] The dam can be configured to simultaneously cover a portion of the anode electrode AE. The portion of the dam corresponding to the light-emitting area EA of the sub-pixel SP can be opened.

[0267] A portion of the anode electrode AE ​​may be exposed to the opening (or portion of the opening) of the dam BANK.

[0268] The luminescent layer (EL) may be located on the side of the bank and in the opening (or portion of the opening) of the bank. All or part of the luminescent layer (EL) may be located between adjacent banks. The luminescent layer (EL) may include an organic membrane.

[0269] In the opening of the dam BANK, the light-emitting layer EL can contact the anode electrode AE. The cathode electrode CE can be disposed on the light-emitting layer EL.

[0270] An encapsulation layer ENCAP can be set on the light-emitting element (ED).

[0271] The encapsulation layer ENCAP can have a single-layer structure or a multi-layer structure. For example, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

[0272] For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 can be inorganic films, and the second encapsulation layer PCL can be an organic film. Among the first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2, the second encapsulation layer PCL can be the thickest. Therefore, the second encapsulation layer PCL can be used as a planarization layer.

[0273] Furthermore, the display device 100 of this disclosure may have a touch sensor TS formed on the encapsulation layer ENCAP to detect the touch of a user's finger or pen.

[0274] In this way, the display panel 110 of this disclosure can improve its moisture resistance and flexibility by forming a light-emitting layer break pattern ECP along the peripheral area SA outside the through-hole TH. It should be noted that, although in Figures 7 to 13 The diagram illustrates a light-emitting layer break pattern (ECP) in the peripheral region SA between the normal region NA and the via TH, but the number and / or shape of the light-emitting layer break patterns (ECPs) arranged in the peripheral region SA are not limited to this. For example, two or more light-emitting layer break patterns may be arranged in the peripheral region SA, and the shape of each light-emitting layer break pattern is not limited to a circle, but may have various shapes such as ellipse, square, hexagon, or octagon.

[0275] The embodiments of this disclosure described above are summarized below.

[0276] A display device according to embodiments of the present disclosure may include a display panel, in which optical electronic devices are disposed within a display area. Furthermore, the display area may include a normal area having a plurality of sub-pixels including a light-emitting layer, a via where the optical electronic devices are located, and a peripheral area between the normal area and the via where one or more light-emitting layer break patterns are formed.

[0277] The surrounding area may include a substrate, a buffer layer formed on the substrate, a gate insulating film formed on the buffer layer, a first interlayer insulating film formed on the gate insulating film with a first thickness, a second interlayer insulating film formed on the first interlayer insulating film with a second thickness greater than the first thickness, and one or more light-emitting layer break patterns formed on the gate insulating film in contact holes in which the first interlayer insulating film and the second interlayer insulating film have been removed.

[0278] The first interlayer insulating film can be an inorganic material, and the second interlayer insulating film can be an organic material. The second thickness can be formed to be 1 to 5 times the first thickness.

[0279] The light-emitting layer break pattern may include a first shielding layer formed on a gate insulating film, a second shielding layer formed on the first shielding layer along the inner wall of the first interlayer insulating film and the second interlayer insulating film, a third shielding layer formed on the second shielding layer, and a break insulating layer formed below the third shielding layer along the inner wall of the second shielding layer.

[0280] The first shielding layer may be formed of the same material as the gate electrode in the normal region.

[0281] The first shielding layer can be formed into a structure that protrudes upwards at both ends.

[0282] The second shielding layer may be formed of the same material as the first source / drain electrode pattern in the normal region.

[0283] The first source-drain electrode pattern can form the source and drain electrodes of the driving transistor.

[0284] The third shielding layer may be formed of the same material as the second source / drain electrode pattern in the normal region.

[0285] The second source / drain electrode pattern can be a metal that connects the first source / drain electrode pattern and the light-emitting element.

[0286] The disconnected insulation layer can be formed from the same material as the planarization layer of the normal area.

[0287] Disconnecting the insulation layer can create an undercut structure below the third shielding layer.

[0288] A display panel according to an embodiment of the present disclosure may include a normal area in which a plurality of sub-pixels including a light-emitting layer are disposed, a via in which an optical electronic device is located, and a peripheral area between the normal area and the via in which one or more light-emitting layer break patterns are formed.

[0289] A display device according to an embodiment of the present disclosure may include a display panel, the display panel including a display area, wherein the display area includes: a normal area having a plurality of sub-pixels including a light-emitting layer; a through hole; and a peripheral area located between the normal area and the through hole, and wherein the light-emitting layer is physically divided into two portions spaced apart from each other in the peripheral area.

[0290] The above description has been presented to enable any person skilled in the art to make and use the technical concepts of this disclosure, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the technical concepts and scope of this disclosure. The above description and drawings provide examples of the technical concepts of this disclosure for illustrative purposes only. For example, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

[0291] Cross-references to related applications

[0292] This application claims the benefit and priority of Korean Patent Application No. 10-2024-0180808, filed in Korea on December 6, 2024, the entire disclosure of which is expressly incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel includes a display area. The display area includes: A normal region, wherein a plurality of sub-pixels, including an emissive layer, are disposed in the normal region; Through holes; and In the peripheral region between the normal region and the through hole, one or more light-emitting layer break patterns are formed in the peripheral region.

2. The display device according to claim 1, wherein, The surrounding area includes: substrate; A buffer layer is formed on the substrate; A gate insulating film, the gate insulating film being formed on the buffer layer; A first interlayer insulating film is formed on the gate insulating film with a first thickness; A second interlayer insulating film, wherein the second interlayer insulating film is formed on the first interlayer insulating film with a second thickness greater than the first thickness; and The one or more light-emitting layer disconnect patterns are formed on the gate insulating film in contact holes in which the first interlayer insulating film and the second interlayer insulating film have been removed.

3. The display device according to claim 2, wherein, The first interlayer insulating film is an inorganic material, and the second interlayer insulating film is an organic material. The second thickness is formed to be 1 to 5 times the first thickness.

4. The display device according to claim 2, wherein, The one or more light-emitting layer break pattern includes: A first shielding layer is formed on the gate insulating film; A second shielding layer is formed on the first shielding layer along the inner walls of the first interlayer insulating film and the second interlayer insulating film; A third shielding layer, the third shielding layer being formed on the second shielding layer; and The insulation layer is disconnected, and the disconnected insulation layer is formed along the inner wall of the second shielding layer below the third shielding layer.

5. The display device according to claim 4, wherein, The first shielding layer is formed of the same material as the gate electrode of the normal region.

6. The display device according to claim 4, wherein, The first shielding layer is formed with both ends protruding upwards.

7. The display device according to claim 4, wherein, The second shielding layer is formed of the same material as the first source / drain electrode pattern of the normal region.

8. The display device according to claim 7, wherein, The first source-drain electrode pattern forms the source and drain electrodes of the driving transistor.

9. The display device according to claim 7, wherein, The third shielding layer is formed of the same material as the second source / drain electrode pattern of the normal region.

10. The display device according to claim 9, wherein, The second source / drain electrode pattern is a metal that connects the first source / drain electrode pattern and the light-emitting element.

11. The display device according to claim 4, wherein, The disconnected insulating layer is formed of the same material as the planarization layer of the normal area.

12. The display device according to claim 4, wherein, The third shielding layer protrudes into the recess on the disconnected insulating layer and is formed as an undercut structure relative to the disconnected insulating layer.

13. The display device according to claim 1, further comprising: An optical electronic device, wherein the optical electronic device is disposed in the through hole.

14. A display panel, the display panel comprising: A normal region, wherein a plurality of sub-pixels, including an emissive layer, are disposed in the normal region; Through hole; as well as In the peripheral region between the normal region and the through hole, one or more light-emitting layer break patterns are formed in the peripheral region.

15. The display panel according to claim 14, wherein, The surrounding area includes: substrate; A buffer layer is formed on the substrate; A gate insulating film, the gate insulating film being formed on the buffer layer; A first interlayer insulating film is formed on the gate insulating film with a first thickness; A second interlayer insulating film, wherein the second interlayer insulating film is formed on the first interlayer insulating film with a second thickness greater than the first thickness; and The one or more light-emitting layer disconnect patterns are formed on the gate insulating film in contact holes in which the first interlayer insulating film and the second interlayer insulating film have been removed.

16. The display panel according to claim 15, wherein, The one or more light-emitting layer break pattern includes: A first shielding layer is formed on the gate insulating film; A second shielding layer is formed on the first shielding layer along the inner walls of the first interlayer insulating film and the second interlayer insulating film; A third shielding layer, the third shielding layer being formed on the second shielding layer; and The insulation layer is disconnected, and the disconnected insulation layer is formed along the inner wall of the second shielding layer below the third shielding layer.

17. The display panel according to claim 14, further comprising: An optical electronic device, wherein the optical electronic device is disposed in the through hole.

18. The display panel according to claim 14, wherein, Each of the one or more light-emitting layer break patterns includes a sidewall structure and a recessed region between the sidewall structures.

19. A display device, the display device comprising: A display panel in which optical and electronic devices are disposed within the display area. The display area includes: A normal region, wherein a plurality of sub-pixels, including an emissive layer, are disposed in the normal region; Through-hole, in which the optical electronic device is located; and In the peripheral region between the normal region and the through hole, one or more light-emitting layer break patterns are formed in the peripheral region.

20. A display device, the display device comprising: The display panel includes a display area. The display area includes: A normal region, wherein a plurality of sub-pixels, including an emissive layer, are disposed in the normal region; Through holes; and The surrounding area, which is between the normal area and the through hole, and The light-emitting layer is physically divided into two spaced-apart portions in the surrounding area.

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