Display panel and display device

Abstract

The application provides a display panel and a display device, the display panel has a display area and a binding area located at one side of the display area, and the display panel comprises a substrate, a plurality of binding electrodes arranged on the substrate, a planarization layer arranged on the substrate, and a touch structure layer. The plurality of binding electrodes are located in the binding area, at least part of the planarization layer is located in the display area, and the orthographic projection of the planarization layer on the substrate does not overlap with the orthographic projection of the binding electrodes on the substrate; the touch structure layer is located at the side of the planarization layer away from the substrate, and comprises a first touch layer, an insulating spacing layer, and a second touch layer arranged in sequence in the direction away from the substrate, at least part of the first touch layer and at least part of the second touch layer are located in the display area, and the insulating spacing layer is located outside the binding area. The structure of the binding electrodes and the touch structure layer is optimized and improved, so that the stress borne by the binding electrodes is significantly reduced, and the crack problem of the binding electrodes is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] With advancements in display technology, foldable OLED (Organic Light-Emitting Diode) displays have garnered significant attention due to their unique form factor. However, during the manufacturing process of foldable OLED displays, the bonding pin crack issue has become a key technical challenge affecting product yield and reliability. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display panel and display device. By optimizing and improving the structure of the bonding electrode and the touch structure layer, the stress borne by the bonding electrode during the bonding process is significantly reduced, fundamentally improving or eliminating the problem of bonding electrode cracks caused by structural, material and process stress, and improving product yield and reliability.

[0004] In a first aspect, the present invention provides a display panel having a display area and a bonding area located on one side of the display area, the display panel comprising:

[0005] Substrate;

[0006] A plurality of bonding electrodes are disposed on the substrate, the plurality of bonding electrodes being located in the bonding region;

[0007] A planarization layer is disposed on the substrate, at least a portion of the planarization layer is located in the display area, and the orthographic projection of the planarization layer on the substrate does not overlap with the orthographic projection of the bonding electrode on the substrate;

[0008] A touch structure layer is located on the side of the planarization layer away from the substrate, and includes a first touch layer, an insulating spacer layer, and a second touch layer sequentially disposed in a direction away from the substrate. At least a portion of the first touch layer and at least a portion of the second touch layer are located in the display area, and the insulating spacer layer is located outside the bonding area.

[0009] In some embodiments, the second touch layer includes a first portion located in the display area and a second portion located in the bonding area, the first portion and the second portion being spaced apart, the second portion being located on the side of the bonding electrode away from the substrate, and the orthogonal projection of the second portion on the substrate covering and extending beyond the orthogonal projection of the bonding electrode on the substrate.

[0010] In some embodiments, the bonding electrode includes multiple conductive layers arranged sequentially along a direction away from the substrate. In two adjacent conductive layers, the orthographic projection of the conductive layer away from the substrate on the substrate covers and exceeds the orthographic projection of the conductive layer close to the substrate on the substrate. The conductive layer furthest from the substrate is electrically connected to the second portion.

[0011] In some embodiments, the display panel further includes a thin-film transistor located in the display area, the thin-film transistor being located on the side of the planarization layer closer to the substrate, and the one of the multilayer conductive layers closest to the substrate being disposed in the same layer as the gate of the thin-film transistor.

[0012] In some embodiments, a gate insulating layer is disposed on the side of the gate of the thin-film transistor away from the substrate. The gate insulating layer extends from the display area to the bonding area. The multilayer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially in a direction away from the substrate. The first conductive layer is disposed on the same layer as the gate. The second conductive layer is located on the side of the gate insulating layer away from the substrate and is electrically connected to the first conductive layer through a via on the gate insulating layer.

[0013] In some embodiments, the display panel further includes, in sequence along a direction away from the substrate, a first insulating layer, a first transition electrode, a second insulating layer, and a second transition electrode located on the side of the thin-film transistor away from the substrate. The second transition electrode is electrically connected to the first transition electrode through a via in the second insulating layer, and the first transition electrode is electrically connected to the drain of the thin-film transistor through a via in the first insulating layer. The planarization layer is located on the side of the layer containing the second transition electrode away from the substrate.

[0014] The second conductive layer is disposed on the same layer as the source and drain of the thin-film transistor;

[0015] The third conductive layer is disposed in the same layer as the first transition electrode;

[0016] The fourth conductive layer is disposed in the same layer as the second transfer electrode.

[0017] In some embodiments, both the first insulating layer and the second insulating layer are located outside the bonding region.

[0018] In some embodiments, the bonding area is provided with multiple electrode groups, each electrode group including at least two bonding electrodes; the second portion corresponding to the bonding electrodes in the same electrode group is connected as a continuous protective layer.

[0019] In some embodiments, the bonding electrode comprises multiple conductive layers sequentially disposed along a direction away from the substrate.

[0020] In each bonded electrode of the same electrode group, the conductive layer furthest from the substrate is connected as a single structure, and the orthographic projection of the single structure on the substrate is within the orthographic projection range of the protective layer on the substrate.

[0021] In a second aspect, the present invention provides a display device comprising a display panel as described in any one of the embodiments of the first aspect. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of a structure where residues cause a short circuit between bonded electrodes, as provided in an embodiment of the present invention.

[0024] Figure 3 This is an overall electrode structure diagram of the bonding area of ​​the display panel provided in an embodiment of the present invention.

[0025] Figure 4 for Figure 3 Enlarged view of point A in the middle.

[0026] Figure 5 for Figure 4 A cross-sectional view along the BB line.

[0027] Figure 6 for Figure 3 A cross-sectional view of the CC line.

[0028] Figure 7 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present invention.

[0029] Figure 8 This is a physical sample image of the bonding area of ​​the display panel provided in an embodiment of the present invention.

[0030] Figure 9 A physical sample image of a continuous protective layer provided for an embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0032] It should be noted that although functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than the module division in the device or the order in the flowchart. In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features. Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "setting," and "arrangement," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0033] A foldable OLED display in related technologies has a display panel with a display area and a bonding area located on one side of the display area. The display panel includes a substrate, and disposed on the substrate: multiple bonding electrodes, multiple light-emitting devices, multiple pixel circuits, a planarization layer, and a touch structure layer. The pixel circuits and light-emitting devices are disposed in the display area. The light-emitting devices are disposed on the side of the pixel circuits away from the substrate and include a first electrode, a light-emitting layer, and a second electrode sequentially disposed in a direction away from the substrate. The first electrode is electrically connected to the pixel circuit. At least a portion of the planarization layer is located in the display area and is disposed between the pixel circuit layer and the light-emitting device, thereby providing a flat surface for the first electrode. Multiple bonding electrodes are located in the bonding area for bonding with a driver chip to receive drive signals provided by the driver chip. The orthographic projection of the planarization layer on the substrate overlaps with the orthographic projection of the bonding electrodes on the substrate. The sides of the bonding electrodes are covered by the planarization layer, thereby preventing over-etching of the bonding electrodes during the etching process of the first electrode of the light-emitting device. The touch structure layer is located on the side of the planarization layer away from the substrate, and includes a first touch layer, an insulating spacer layer, and a second touch layer sequentially disposed in a direction away from the substrate. At least a portion of the first touch layer and at least a portion of the second touch layer are located in the display area. A portion of the insulating spacer layer is located in the display area, and another portion is located in the bonding area. The insulating spacer layer in the bonding area is located on the side of the bonding electrode away from the substrate and covers a portion of the bonding electrode. The second touch layer includes a first portion located in the display area and a second portion located in the bonding area. The orthographic projection of the second portion on the substrate overlaps with the orthographic projection of the bonding electrode on the substrate. The insulating spacers on the side of adjacent bonding electrodes away from the substrate are continuous, and each bonding electrode is electrically connected to a corresponding second portion. The second portions corresponding to different bonding electrodes are spaced apart from each other.

[0034] Specifically, the bonding electrode includes multiple conductive layers arranged sequentially in a direction away from the substrate. The multiple conductive layers include a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged sequentially and electrically connected in a direction away from the substrate.

[0035] The structure of the aforementioned OLED display panel has the following shortcomings: First, the bonding electrodes use a multi-layer conductive layer stacking design, increasing the height difference between the bonding electrodes. During bonding, this increases the deformation stress between the bonding electrodes, making the insulating spacer layer prone to cracking at the bottom edge of the bonding electrodes. Second, during the etching process of the first electrode, to prevent the etching solution from over-etching the multi-layer conductive layers of the bonding electrodes and forming lateral grooves, and to avoid the multi-layer conductive layers reacting with the etching solution to generate metal particles, a planarization layer formed of organic material is used to surround the edges of the bonding electrodes. This also increases the height and width of the bonding electrodes to some extent, thereby increasing the stress between the bonding electrodes. Third, foldable OLED displays use low-modulus pressure-sensitive adhesive (U-film PSA) to form a back film on the side of the substrate away from the bonding electrodes. The back film deforms more intensely during the bonding process, further increasing the stress borne by the bonding electrodes. Fourth, during the manufacturing process, if there is internal stress in the insulating spacer layer of the touch structure layer, the stress direction is positive warping, but the multilayer conductive layer that binds the electrodes has a negative warping trend. Since the two warping trends are opposite, the insulating spacer layer is more prone to peeling and cracking.

[0036] In summary, based on the structure of the display panel described above, during the bonding process of foldable OLED display products, the insulating spacer layer between the bonding electrodes is prone to cracking and peeling, which may lead to the bonding electrodes breaking and causing poor bonding.

[0037] In view of the problems existing in the related technologies, the present invention aims to provide a display panel and display device that can significantly reduce the stress on the bonding electrodes, fundamentally improve or eliminate the cracking problem of the bonding electrodes caused by structural, material and process stress, and improve product yield and reliability.

[0038] In a first aspect, embodiments of the present invention provide a display panel having a display area and a bonding area located on one side of the display area. For example... Figure 1 As shown, the display panel includes a substrate 100 and a plurality of bonding electrodes 200 disposed on the substrate 100, the plurality of bonding electrodes 200 being located in a bonding region. Optionally, the substrate 100 may be a flexible substrate made of a material such as polyimide (PI).

[0039] Furthermore, the display panel also includes a planarization layer 700 disposed on the substrate 100, at least a portion of which is located in the display area, and the orthographic projection of the planarization layer 700 on the substrate 100 does not overlap with the orthographic projection of the bonding electrode 200 on the substrate 100.

[0040] The orthographic projection of the planarization layer 700 on the substrate 100 does not overlap with the orthographic projection of the bonding electrode 200 on the substrate 100, meaning that the side of the bonding electrode 200 is not edged with the planarization layer 700. This design reduces the overall height and width of the bonding electrode 200, thereby reducing the deformation stress between the bonding electrodes 200. This is because, firstly, the form of the planarization layer 700 on the side of the bonding electrode 200 directly increases the height and width of the side of the bonding electrode 200, creating a new stress point. When the pressure increases, this stress point will become a stress concentration point, leading to a sharp increase in deformation stress between adjacent bonding electrodes 200. Secondly, the material forming the planarization layer 700 has different mechanical properties, such as the coefficient of thermal expansion, compared to the conductive layer of the bonding electrode 200. During the bonding process, this material mismatch introduces additional stress. Therefore, by eliminating the edge of the planarization layer 700, this heterogeneous material interface is removed, simplifying the structure of the side of the bonding electrode 200 and making stress transmission more uniform.

[0041] Furthermore, the display panel also includes a touch structure layer 400, which is located on the side of the bonding electrode 200 away from the substrate 100. The touch structure layer 400 includes a first touch layer 410, an insulating spacer layer 420, and a second touch layer 430 sequentially disposed along a direction away from the substrate 100. At least a portion of the first touch layer 410 and at least a portion of the second touch layer 430 are located in the display area, and the insulating spacer layer 420 is located outside the bonding area.

[0042] The insulating spacer layer 420 is located outside the bonding area, indicating that no insulating spacer layer 420 is provided within the bonding area. This arrangement fundamentally avoids the risk of the insulating spacer layer 420 peeling off and cracks propagating to the bonding electrode 200 due to stress on the insulating spacer layer 420. This is because the insulating spacer layer 420 itself may have internal stress. When its internal stress is positive, the stress direction has a positive warping tendency, but the conductive layer of the bonding electrode 200 has a negative warping tendency. The two can easily form a stress counteraction. This stress counteraction will cause the insulating spacer layer 420 to be subjected to huge tensile or compressive stress, which can easily lead to the peeling of the insulating spacer layer 420. This peeling and cracking will be transmitted downward to the bonding electrode 200, causing cracks. Therefore, the absence of the insulating spacer layer 420 within the bonding area is equivalent to removing the stress counteraction layer, making the structural stress state of the bonding electrode 200 consistent, and fundamentally eliminating cracks caused by stress counteraction.

[0043] In this embodiment, the side of the bonding electrode 200 is not edged with a planarization layer 700, and the bonding area is not covered with an insulating spacer layer 420. The combination of these two methods significantly reduces the overall stress level borne by the bonding electrode 200, fundamentally improving or eliminating cracking problems caused by structural, material, and process stresses, and helping to improve product yield and reliability.

[0044] In some specific embodiments of the present invention, such as Figure 1 As shown, the second touch layer 430 includes a first portion 430a located in the display area and a second portion 430b located in the bonding area. The first portion 430a and the second portion 430b are spaced apart. The second portion 430b is located on the side of the bonding electrode 200 away from the substrate 100, and the orthogonal projection of the second portion 430b on the substrate 100 covers and extends the orthogonal projection of the bonding electrode 200 on the substrate 100.

[0045] In this embodiment, by optimizing the structure of the second touch layer 430, the bonding electrode 200 beneath the second touch layer 430 is protected from process damage, and the mechanical reliability of the bonding electrode 200 is improved, thereby preventing or reducing cracks in the bonding electrode 200. Specifically, while eliminating the edge covering of the planarization layer 700, the size of the second portion 430b of the second touch layer 430 is enlarged so that its orthogonal projection on the substrate 100 covers and extends beyond the orthogonal projection of the bonding electrode 200 on the substrate 100. This is equivalent to using the second portion 430b of the second touch layer 430 itself as a cover layer to protect the bonding electrode 200 beneath it, preventing the bonding electrode 200 from being over-etched by the etching solution and forming lateral grooves during subsequent etching processes. The expansion of the second portion 430b of the second touch layer 430 replaces part of the function of the original planarization layer 700's edge and reshapes the top contour of the bonding electrode 200. This helps the stress to be more evenly distributed or transmitted on the top of the bonding electrode 200, reducing local stress concentration caused by steep edges of the bonding electrode 200 or mismatch between the material of the planarization layer and the conductive layer material of the bonding electrode 200, thereby reducing the risk of cracking.

[0046] It should be noted that when the planarization layer 700 is removed and the second portion 430b of the second touch layer 430 is not expanded outward, that is, the orthogonal projection of the second portion 430b on the substrate 100 does not cover the orthogonal projection of the bonding electrode 200 on the substrate 100, due to the height difference of the bonding electrode 200 itself, etching residues of the second touch layer 430 material will remain at the bottom edge of the bonding electrode 200 (near the substrate 100) during the etching process. Some of these residual second touch layer 430 materials may be very small, with only a portion remaining connected to the bonding electrode 200. During the subsequent water washing process, these residues may detach and fall between two adjacent bonding electrodes 200. Figure 2 As shown, since the second touch layer 430 is conductive, these residues will connect the two bonding electrodes 200 that should be insulated, thus causing a short circuit.

[0047] In this embodiment, the portion of the second part 430b of the second touch layer 430 that extends beyond the bonding electrode 200 forms a buffer portion to relieve bonding stress.

[0048] Specifically, by forming a buffer section, the concentrated stress generated during the bonding process is actively dispersed and absorbed, thereby effectively preventing edge cracks and interlayer delamination of the bonding electrode 200 caused by stress concentration. Specifically, during the bonding process, pressure is applied to the second portion 430b of the second touch layer 430. If the edge of the bonding electrode 200 is a steep drop, stress will concentrate on the exposed corner, easily leading to cracks. This buffer section, by providing a ramp or cantilever structure formed by the second portion 430b of the second touch layer 430 extending outward from the sidewall of the bonding electrode 200, changes the force transmission path, dispersing the stress originally concentrated at one point to a wider area, thus acting as a buffer. Furthermore, this buffer section physically protects the edge of the bonding electrode 200 from direct exposure to the shear force of bonding. Simultaneously, because the material properties of the second portion 430b of the second touch layer 430 are different from those of the underlying bonding electrode 200, this structural change can also absorb and dissipate deformation energy to a certain extent, preventing cracks from initiating and spreading from the edge of the bonding electrode 200.

[0049] In some specific embodiments of the present invention, such as Figure 1As shown, the bonding electrode 200 includes multiple conductive layers sequentially disposed along a direction away from the substrate 100. In two adjacent conductive layers, the orthographic projection of the conductive layer away from the substrate 100 on the substrate 100 covers and extends the orthographic projection of the conductive layer closer to the substrate 100 on the substrate 100. The conductive layer furthest from the substrate 100 is electrically connected to the second portion 430b of the second touch layer 430. For example, there is no insulating layer between the conductive layer furthest from the substrate 100 and the second portion 430b, and each position on the upper surface of the conductive layer furthest from the substrate 100 is in contact with the second touch layer 430.

[0050] In this embodiment, in two adjacent conductive layers, the orthographic projection of the conductive layer furthest from the substrate 100 onto the substrate 100 covers and extends beyond the orthographic projection of the conductive layer closest to the substrate 100. This means that by extending the upper conductive layer outwards layer by layer to cover the edge of the lower conductive layer, the sidewalls of the lower conductive layer are protected, stress distribution is optimized, and the structural reliability and electrical stability of the entire bonding electrode 200 during the bonding process are improved, preventing cracks, peeling, and short circuits. This is because, firstly, during the manufacturing process of the display panel, the bonding electrode 200 undergoes multiple wet or dry processes such as etching and cleaning. If the edges of each conductive layer are directly exposed, their sidewalls are easily eroded by etching solutions, leading to over-etching, the formation of grooves, or the generation of metal particles that could cause short circuits. This embodiment provides protection for the lower layer by having the upper conductive layer cover and extend beyond it, preventing etching solutions from directly contacting the edges of the lower conductive layer. Secondly, during bonding, the bonding electrode 200 needs to withstand significant pressure and heat, generating complex mechanical stresses. If the edges of the conductive layers of the bonding electrode 200 are steep and the layers are aligned, stress will be highly concentrated at the edges of the conductive layers and at the interfaces between the layers, which can easily lead to interlayer delamination or cracks. This embodiment, by forming a stepped structure between the conductive layers, can effectively disperse and buffer the concentrated edge stress, allowing for smoother stress transmission and significantly reducing the risk of crack formation and propagation due to stress concentration. Thirdly, the stacking method of multiple conductive layers expanding outwards layer by layer helps to enhance the adhesion between layers, making the entire bonding electrode 200 more likely to deform as a whole when subjected to external force, rather than individual layers sliding or separating independently, thereby improving the mechanical robustness of the bonding electrode 200.

[0051] It should be noted that the structural shape formed between the conductive layers is not limited to... Figure 1 The stepped shape shown can be other shapes, such as arcs, ramps, etc., and is not specifically limited in this invention.

[0052] In some specific embodiments of the present invention, such as Figure 1As shown, the display panel also includes a thin-film transistor 600 located in the display area. The thin-film transistor 600 is located on the side of the planarization layer 700 close to the substrate 100. The one of the multilayer conductive layers of the bonding electrode 200 closest to the substrate 100 is disposed in the same layer as the gate 630 of the thin-film transistor 600.

[0053] Specifically, such as Figure 1 As shown, a gate insulating layer 500 is disposed on the side of the gate 630 of the thin-film transistor 600 away from the substrate 100. The gate insulating layer 500 extends from the display area to the bonding area. The multilayer conductive layers include a first conductive layer 210, a second conductive layer 220, a third conductive layer 230, and a fourth conductive layer 240 disposed sequentially along the direction away from the substrate 100. No insulating layer is disposed between the first conductive layer 210, the second conductive layer 220, the third conductive layer 230, and the fourth conductive layer 240 to facilitate conduction between the layers. The first conductive layer 210 is disposed on the same layer as the gate 630 of the thin-film transistor 600. The second conductive layer 220 is located on the side of the gate insulating layer 500 away from the substrate 100 and is electrically connected to the first conductive layer 210 through a via on the gate insulating layer 500. The second conductive layer 220, the third conductive layer 230, and the fourth conductive layer 240 can be disposed on the same layer as various conductive structures in the display area, for example, the second conductive layer 220 can be disposed on the same layer as a data line.

[0054] In some specific embodiments of the present invention, such as Figure 1 As shown, the display panel also includes, sequentially disposed on the side of the thin-film transistor 600 away from the substrate 100 and along the direction away from the substrate 100, a first insulating layer 650, a first transition electrode 660, a second insulating layer 670, and a second transition electrode 680. The first insulating layer 650 and the second insulating layer 670 can be made of organic materials. The first transition electrode 660 is electrically connected to the drain 640 of the thin-film transistor 600 through a via on the first insulating layer 650, and the second transition electrode 680 is electrically connected to the first transition electrode 660 through a via on the second insulating layer 670. The planarization layer 700 is located on the side of the layer containing the second transition electrode 680 away from the substrate 100. The light-emitting device 800 is disposed on the side of the planarization layer 700 away from the substrate 100 and includes a first electrode 810, a light-emitting layer 820, and a second electrode 830. The first electrode 810 is electrically connected to the second electrode 830 through a via on the planarization layer 700. A pixel defining layer 900 is also provided on the side of the planarization layer 700 away from the substrate 100. The pixel defining layer 900 has multiple pixel openings, and the light-emitting device 800 can be arranged one-to-one with each pixel opening. An encapsulation layer 840 is provided on the side of the light-emitting device 800 away from the substrate 100 for encapsulating the light-emitting device 800. The touch structure layer 400 is located on the side of the encapsulation layer 840 away from the substrate 100.

[0055] Specifically, the second conductive layer 220 is disposed in the same layer as the source 610 and drain 640 of the thin-film transistor 600, and the active layer 620 of the thin-film transistor 600 is disposed on the side of the source 610 and drain 640 facing the substrate; the third conductive layer 230 is disposed in the same layer as the first transition electrode 660; and the fourth conductive layer 240 is disposed in the same layer as the second transition electrode 680. The first insulating layer 650 and the second insulating layer 670 are both located outside the bonding region.

[0056] In some specific embodiments of the present invention, such as Figure 3 As shown, multiple electrode groups are arranged in the bonding area, each electrode group including at least two bonding electrodes 200 that are electrically connected to each other to reduce impedance or meet the requirements of the driver chip. Bonding electrodes 200 in the same electrode group can be electrically connected to the same parallel trace 250. The second portion 430b corresponding to the bonding electrodes 200 in the same electrode group is connected as a continuous protective layer. That is, as... Figure 4 and Figure 5 As shown, the second portion 430b above the two bonding electrodes 200 is integrated. The multiple bonding electrodes 200 may include multiple first bonding electrodes 201 and multiple second bonding electrodes 202. The first bonding electrodes 201 can be electrically connected to the input terminal of the driver chip, and the second bonding electrodes 202 can be electrically connected to the output terminal of the driver chip. This embodiment of the invention is illustrated by taking an electrode group comprising at least two first bonding electrodes 201 as an example, while each second bonding electrode 202 can be independent of the others.

[0057] Furthermore, the bonding electrode 200 includes multiple conductive layers sequentially disposed along a direction away from the substrate 100. Among the first bonding electrodes 201 of the same electrode group, the conductive layer furthest from the substrate 100 (i.e., the fourth conductive layer 240) is connected into a single structure, and the orthographic projection of the single structure onto the substrate 100 lies within the orthographic projection range of the protective layer onto the substrate 100. That is, as... Figure 3 , Figure 4 and Figure 5 As shown, in each of the first bonding electrodes 201 of the same electrode group, the fourth conductive layer 240 is connected as a whole, and the orthogonal projection of the connected fourth conductive layer 240 on the substrate 100 is located within the orthogonal projection range of the protective layer on the substrate 100.

[0058] In the same electrode group, the third conductive layer 230 of each first binding electrode 201 can also be connected into a single structure.

[0059] It should be noted that during the manufacturing process of the display panel, if the second portion 430b covering multiple first bonding electrodes 201 connected together is isolated, the fourth conductive layer 240 is prone to over-etching during the patterning process of the second touch layer 430. In this embodiment of the invention, the second portions 430b of the second touch layer 430 corresponding to the first bonding electrodes 201 in the same electrode group are connected as a continuous protective layer to avoid over-etching of the underlying fourth conductive layer 240 during the patterning process. During bonding and subsequent product bending, if the second portion 430b of the second touch layer 430 covering each first bonding electrode 201 is isolated, a single first bonding electrode 201 is prone to slight independent deformation or edge lifting due to uneven stress, becoming a new stress concentration point and crack initiation point. Connecting the second part 430b of the second touch layer 430 corresponding to the first bonding electrode 201 in the same electrode group into a continuous protective layer can enhance the collective rigidity and deformation resistance of the first bonding electrode 201, more evenly disperse and resist external stress, prevent abnormal displacement of the first bonding electrode 201, and thus improve the structural stability of the entire bonding area.

[0060] In some specific embodiments of the present invention, such as Figure 3 As shown, multiple independent bonding electrodes 200 are also provided in the bonding area. Among these multiple independent bonding electrodes 200, adjacent bonding electrodes 200 are not electrically connected. That is, as... Figure 6 As shown, the third conductive layer 230, the fourth conductive layer 240 of the adjacent bonding electrode 200, and the second part 430b of the topmost second touch layer 430 are not connected.

[0061] Secondly, embodiments of the present invention provide a method for manufacturing a display panel, the display panel having a display area and a bonding area located on one side of the display area, such as... Figure 7 As shown, the preparation method includes the following steps:

[0062] S110. Multiple bonding electrodes are formed on the substrate at positions corresponding to the bonding regions;

[0063] S120. A planarization layer is formed, at least a portion of which is located in the display area, and the orthographic projection of the planarization layer on the substrate does not overlap with the orthographic projection of the bonding electrode on the substrate.

[0064] S130. A touch structure layer is formed. The touch structure layer is located on the side of the planarization layer away from the substrate and includes a first touch layer, an insulating spacer layer, and a second touch layer disposed sequentially in a direction away from the substrate. At least a portion of the first touch layer and at least a portion of the second touch layer are located in the display area, and the insulating spacer layer is located outside the bonding area.

[0065] In some specific embodiments of the present invention, the preparation process of the second touch layer in step S130 includes:

[0066] Forming a touch material layer;

[0067] A patterning process is performed on the touch material layer to form a first part located in the display area and a second part located in the bonding area. The first part and the second part are spaced apart. The second part is located on the side of the bonding electrode away from the substrate, and the orthogonal projection of the second part on the substrate covers and exceeds the orthogonal projection of the bonding electrode on the substrate.

[0068] Specifically, in step S120, the orthographic projection of the planarization layer on the substrate does not overlap with the orthographic projection of the bonding electrode on the substrate, indicating that the planarization layer edging is removed from the sides of the bonding electrode. In step S130, the insulating spacer is located outside the bonding area, indicating that no insulating spacer is provided within the bonding area. These two steps combined reduce the height and width of the bonding electrode, completely eliminating the stress conflict caused by the opposing stress of the insulating spacer's own stress and the warping trend of the conductive layer of the bonding electrode. This fundamentally avoids the risk of insulating spacer peeling and cracks propagating downwards to the bonding electrode.

[0069] Physical samples of the bonding area of ​​the display panel manufactured using the above-described preparation method are shown below. Figure 8 As shown, from Figure 8 As can be seen, the orthographic projection of the second portion 430b of the topmost second touch layer 430 onto the substrate covers and extends beyond the orthographic projection of the bonding electrode 200 onto the substrate 100. Furthermore, no planarization layer or insulating spacer layer is formed on the sides of the bonding electrode 200, and there are no cracks at the bottom (the area within the dashed box in the figure). A physical sample showing a continuous protective layer formed by the second portion 430b above multiple first bonding electrodes 200 is shown below. Figure 9 As shown.

[0070] from Figure 8 and Figure 9 This demonstrates the feasibility of the display panel and its fabrication method provided by this invention. Using the display panel and its fabrication method provided by this invention, the cracking problem of the bonding electrodes is greatly improved, and the defect rate of the display panel is significantly reduced.

[0071] Thirdly, embodiments of the present invention also provide a display device, including the display panel described in the first aspect embodiment above. By employing the display panel in the above embodiments, the yield rate of the display device can be improved.

[0072] In some embodiments, the display device can be any product or component with display functionality, such as an OLED panel, OLED TV, OLED billboard, monitor, mobile phone, or navigator.

[0073] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display panel having a display area and a binding area located on one side of the display area, characterized by, The display panel includes: Substrate; A plurality of bonding electrodes are disposed on the substrate, the plurality of bonding electrodes being located in the bonding region; A planarization layer is disposed on the substrate, at least a portion of the planarization layer is located in the display area, and the orthographic projection of the planarization layer on the substrate does not overlap with the orthographic projection of the bonding electrode on the substrate; A touch structure layer is located on the side of the planarization layer away from the substrate, and includes a first touch layer, an insulating spacer layer, and a second touch layer sequentially disposed in a direction away from the substrate. At least a portion of the first touch layer and at least a portion of the second touch layer are located in the display area, and the insulating spacer layer is located outside the bonding area.

2. The display panel of claim 1, wherein, The second touch layer includes a first portion located in the display area and a second portion located in the bonding area, the first portion and the second portion being spaced apart, the second portion being located on the side of the bonding electrode away from the substrate, and the orthogonal projection of the second portion on the substrate covering and extending beyond the orthogonal projection of the bonding electrode on the substrate.

3. The display panel of claim 2, wherein, The bonding electrode includes multiple conductive layers arranged sequentially along a direction away from the substrate. In two adjacent conductive layers, the orthogonal projection of the conductive layer away from the substrate on the substrate covers and exceeds the orthogonal projection of the conductive layer close to the substrate on the substrate. The conductive layer furthest from the substrate is electrically connected to the second portion.

4. The display panel according to claim 3, characterized in that, The display panel also includes a thin-film transistor located in the display area. The thin-film transistor is located on the side of the planarization layer closest to the substrate, and the one of the multilayer conductive layers closest to the substrate is disposed in the same layer as the gate of the thin-film transistor.

5. The display panel according to claim 4, characterized in that, The thin-film transistor has a gate insulating layer on the side of the gate away from the substrate. The gate insulating layer extends from the display area to the bonding area. The multilayer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged sequentially in a direction away from the substrate. The first conductive layer is disposed in the same layer as the gate. The second conductive layer is located on the side of the gate insulating layer away from the substrate and is electrically connected to the first conductive layer through a via on the gate insulating layer.

6. The display panel according to claim 5, characterized in that, The display panel further includes, in sequence along the direction away from the substrate, a first insulating layer, a first transition electrode, a second insulating layer, and a second transition electrode located on the side of the thin-film transistor away from the substrate. The second transition electrode is electrically connected to the first transition electrode through a via in the second insulating layer, and the first transition electrode is electrically connected to the drain of the thin-film transistor through a via in the first insulating layer. The planarization layer is located on the side of the layer containing the second transition electrode away from the substrate. The second conductive layer is disposed on the same layer as the source and drain of the thin-film transistor; The third conductive layer is disposed in the same layer as the first transition electrode; The fourth conductive layer is disposed in the same layer as the second transfer electrode.

7. The display panel according to claim 6, characterized in that, Both the first insulating layer and the second insulating layer are located outside the bonding area.

8. The display panel according to claim 2, characterized in that, The bonding area is provided with multiple electrode groups, each electrode group including at least two bonding electrodes; the second part corresponding to the bonding electrodes in the same electrode group is connected as a continuous protective layer.

9. The display panel according to claim 8, characterized in that, The bonding electrode comprises multiple conductive layers sequentially disposed along a direction away from the substrate. In each bonded electrode of the same electrode group, the conductive layer furthest from the substrate is connected as a single structure, and the orthographic projection of the single structure on the substrate is within the orthographic projection range of the protective layer on the substrate.

10. A display device, characterized in that, The display panel includes any one of claims 1 to 9.

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