A low-cost re-wiring package fabrication method

Abstract

The application discloses a low-cost re-wiring packaging preparation method and belongs to the re-wiring packaging preparation field. The method mainly comprises the following steps: confirming the type of a driving wafer and LED incoming material, detecting the defects of the incoming material by using a full-automatic optical inspection method, removing unqualified incoming material, sequentially completing 1st PI coating, exposure development and curing process on the wafer surface, forming an insulating layer with a through hole, plating nickel gold on the surface of the through hole and the wafer pad, and forming a first nickel gold barrier layer. The application designs a re-wiring layer taking sintered silver paste as the core, a barrier layer of plated nickel gold and an insulating protective substrate of a three-step polyimide layer in a synergistic process system, significantly reduces the equipment and process cost of the re-wiring packaging, simplifies the production process, combines a segmented low-temperature process with a screen printing forming mode, realizes accurate regulation and control of the preparation process, and effectively balances the production efficiency and the product structure stability.

Description

Technical Field

[0001] This invention relates to the field of redistribution packaging technology, and in particular to a low-cost redistribution packaging method. Background Technology

[0002] Redistribution layer (RDL) is a core interconnect technology in advanced packaging. By depositing an insulating layer and redistributing metal lines on the chip surface, it rearranges the chip edges or dense native input / output (I / O) points to areas that are more conducive to package integration, thereby significantly improving I / O density, reducing package size, and supporting heterogeneous integration of multiple chips.

[0003] The prior art patent document with authorization announcement number CN116190311A discloses "a method for preparing a redistribution layer and a packaging structure". The preparation method is as follows: first, an insulating layer is applied to make a patterned first opening. Then, a conductive layer is filled into the first opening. After that, a planarization process is used to make a flat embedded structure. A sputtering layer is formed on the flat embedded structure surface. A photoresist layer is applied on the sputtering layer. The patterned photoresist layer forms a second opening. The position of the second opening corresponds to the position of the planarized conductive layer. Metal is electroplated in the second opening to form a metal interconnect layer. Finally, the photoresist layer and the sputtering layer covered by the photoresist layer are removed to form a redistribution layer.

[0004] The patent document with authorization announcement number CN116564830A discloses a "method for preparing a redistribution layer and a wafer-level packaging structure". The method for preparing a redistribution layer includes setting a dielectric layer on the side of the functional chip with pads; setting a metal wiring layer on the dielectric layer; placing the functional chip with the metal wiring layer in an inert gas atmosphere and letting it stand for a preset time; and after removing the functional chip from the inert atmosphere, setting a dielectric layer on the metal wiring layer.

[0005] While existing technologies can improve the electroplating process abnormalities and packaging structure delamination issues in redistribution fabrication, enhance the surface smoothness of the electroplated metal interconnect layer, and avoid electroplating process abnormalities caused by photoresist residue in deep holes, and simultaneously improve the surface roughening of the metal interconnect layer by placing it in an inert gas atmosphere to enhance the adhesion between the metal interconnect layer and the dielectric layer and improve the delamination phenomenon, existing technologies all rely on electroplated copper as the core for fabricating the redistribution layer, supplemented by a sputtering process to form the metal underlayer. This not only results in extremely high investment costs for core equipment such as sputtering machines and electroplating machines, but also in cumbersome process steps, requiring photolithography, electroplating, and etching. The production cycle is long due to multiple planarization processes. At the same time, the process design of existing technologies is based on the precision requirements of high-end chips, without process adaptation for low-cost, small-batch packaging products. The excessive pursuit of fine lines and high stack-up process characteristics has led to a surge in the unit manufacturing cost of low-end products. In addition, existing technologies lack interface protection designs to adapt to low-cost conductive materials such as non-electroplated copper. If low-cost conductive materials are directly replaced, problems such as ion diffusion and insufficient line bonding are likely to occur. It is difficult to meet the production requirements of low-cost advanced packaging in consumer electronics, power electronics and other fields, and it is also difficult to adapt to small-batch, multi-variety production scenarios. Summary of the Invention

[0006] Purpose of the invention: The purpose of this invention is to provide a low-cost redistribution packaging fabrication method to solve the problems mentioned in the background art.

[0007] Technical solution: A low-cost redistribution package fabrication method, comprising the following steps:

[0008] S1. Confirm the model of the driver wafers and LEDs, and use a fully automated optical inspection method to detect defects in the incoming materials and reject unqualified materials;

[0009] S2. The first PI coating, exposure, development and curing processes are completed sequentially on the wafer surface to form an insulating layer with through holes. Then, nickel-gold is electroplated in the through holes and on the wafer pad surface to form a first nickel-gold barrier layer.

[0010] S3. The second PI coating, exposure development and curing processes are sequentially completed on the surface of the first nickel-gold barrier layer and the first PI layer to form a pattern layer with redistribution line trenches.

[0011] S4. Nano silver paste is filled into the circuit trench using screen printing process, and a silver paste redistribution layer is formed by low-temperature hot pressing sintering. Then, the silver paste redistribution layer and the 2nd PI insulation layer are sequentially subjected to plasma etching cleaning and planarization treatment.

[0012] S5. After planarization, the 3rd PI coating, exposure development and curing process is completed on the surface of the silver paste redistribution layer and the 2nd PI layer to form a protective layer with solder joint through holes. Then, nickel gold is plated in the solder joint through holes and on the surface of the solder joints of the silver paste redistribution layer to form a second nickel gold barrier layer.

[0013] S6. Using a special ball-planting fixture that matches the solder joint pattern, the solder balls are precisely planted on the second nickel-gold barrier layer pads coated with flux.

[0014] S7. The wafer after ball placement is sent to a reflow oven for low-temperature reflow treatment, so that the solder balls and the second nickel-gold barrier layer form a metallurgical bond, and the redistribution packaging is completed.

[0015] Preferably, in S1, the incoming material defects detected by fully automated optical inspection include wafer surface scratches, LED pin deformation, substrate surface stains, pad defects / misalignment, and passivation layer cracks. After inspection, unqualified incoming materials with any of the above defects are directly rejected.

[0016] Preferably, in step S2, the first PI coating is applied using a spin coating process with a coating thickness of 3-8µm; the first PI curing is performed by gradient high-temperature baking at a temperature of 200-250℃ for 30-40 minutes; the nickel layer of the first nickel-gold barrier layer has a deposition thickness of 2-5µm, and the gold layer has a deposition thickness of 0.05-0.2µm.

[0017] Preferably, in step S3, the 2nd PI coating is applied using a spin coating process with a coating thickness of 8-20µm; the 2nd PI curing is performed by gradient high-temperature baking at a temperature of 200-250℃ for 30-40 minutes; the width and spacing of the rewiring trenches are both 10µm, and the trench sidewalls are vertical with a flat bottom.

[0018] Preferably, in step S4, the silver particles in the nano-silver paste have a particle size of 20-50 nm; the screen printing process uses a screen mesh of 300-500 mesh, a squeegee pressure of 5-10 N, a squeegee moving speed of 50-100 mm / s, and a silver paste filling thickness of 5-20 µm; the low-temperature hot pressing sintering sequentially includes a heating section, a sintering section, a heat preservation section, and a cooling section; the plasma etching uses an O2 / Ar mixed gas as the etching source, and the planarization treatment grinds the thickness of the 2nd PI layer to be consistent with the height of the silver paste redistribution layer, and the surface roughness Ra of the silver paste redistribution layer after the planarization treatment is <0.1 µm.

[0019] Preferably, in step S5, the 3rd PI coating is applied using a spin coating process with a coating thickness of 3-8µm; the 3rd PI curing is performed by gradient high-temperature baking at a temperature of 200-250℃ for 30-40 minutes; the nickel layer of the second nickel-gold barrier layer has a deposition thickness of 2-5µm, the gold layer has a deposition thickness of 0.05-0.2µm, and the solder joint via positions precisely correspond to the solder joint positions of the silver paste redistribution layer.

[0020] Preferably, in step S6, the flux is applied only to the surface of the pads of the second nickel-gold barrier layer; the hole pattern of the ball-planting fixture is perfectly matched with the through-hole pattern of the solder joint, and the hole size is precisely adapted to the solder ball size.

[0021] Preferably, in step S7, the peak temperature of the reflow oven for low-temperature reflow treatment is 230-250°C. During the reflow process, the solder balls react with the flux and the pads of the second nickel-gold barrier layer. After reflow, the solder balls and the second nickel-gold barrier layer form a metallurgical bond without any cold solder joints or bridging.

[0022] Preferably, the heating section raises the temperature from room temperature to 160°C at a rate of 5-8°C / min and a pressure of 0 MPa; the sintering section raises the temperature from 160°C to 220-250°C at a rate of 3-5°C / min and a pressure of 10-40 MPa; the holding section maintains the temperature at 220-250°C and a pressure of 10-40 MPa for 10-30 minutes; and the cooling section lowers the temperature from 250°C to room temperature at a rate of 2-3°C / min and a pressure gradually decreases to 0 MPa.

[0023] Beneficial Effects: This invention significantly reduces equipment and process costs for redistribution packaging by designing a synergistic process system consisting of a sintered silver paste-based redistribution layer, a nickel-gold plating barrier layer, and a three-step polyimide insulating protective substrate. This simplifies the production process. Furthermore, the combination of segmented low-temperature processing and screen printing allows for precise control of the manufacturing process, effectively balancing production efficiency and product structural stability. The use of a nano-silver paste and polyimide composite structure enhances the bonding strength and interface insulation of the circuitry. Simultaneously, the double-layer nickel-gold plating and triple-layer PI protection significantly improve the oxidation resistance of the redistribution layer. The invention improves the chemical and anti-ion diffusion properties of the core equipment. Furthermore, the simplified design of the core equipment and the introduction of no high-temperature sputtering / electroplating process further optimize material utilization, reduce energy consumption and fixed asset investment. The overall process reduces manufacturing costs while improving adaptability for small-batch, multi-variety production, aligning with the development trend of low-cost advanced packaging. This invention not only solves the common problems of high equipment investment, cumbersome processes, and poor adaptability for small batches in traditional copper electroplating redistribution processes, but also provides an economical and practical technical path for the large-scale preparation of low-cost redistribution packaging through multi-technology integration and innovation. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the method flow of the present invention;

[0025] Figure 2 This is a schematic diagram of the planarization process structure of the present invention;

[0026] Figure 3 This is a schematic diagram of the fabrication structure of the three-layer PI layer and the double-layer nickel-gold barrier layer of the present invention;

[0027] Figure 4 This is a schematic diagram of the adapter structure between the solder joint through hole and the nickel-gold barrier layer before ball placement in this invention;

[0028] Figure 5 This is a schematic diagram of the cross-sectional structure of the finished product of the present invention. Detailed Implementation

[0029] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Example 1

[0031] A low-cost redistribution package fabrication method includes:

[0032] 1. Confirm the model of the driver wafers and LEDs upon arrival, and use a fully automated optical inspection method to detect defects in the incoming materials. The defects detected include scratches on the wafer surface, deformation of LED pins, stains on the substrate surface, missing / offset pads, and cracks in the passivation layer. Unqualified incoming materials with any of the above defects are directly rejected.

[0033] 2. A spin-coating process is used to complete the first PI coating on the wafer surface, with a coating thickness of 3µm. After exposure and development to form an insulating layer with through holes, a gradient high-temperature baking curing process is performed at a baking temperature of 200-250℃ for 30 minutes. Subsequently, nickel-gold plating is performed in the through holes and on the wafer pad surface to form the first nickel-gold barrier layer, wherein the nickel layer deposition thickness is 2µm and the gold layer deposition thickness is 0.05µm.

[0034] 3. The second layer of PI is coated on the surface of the first nickel-gold barrier layer and the first layer of PI using a spin coating process. The coating thickness is 8µm. After exposure and development, a pattern layer with redistribution line trenches is formed (the trench width and spacing are both 10µm, the trench sidewalls are vertical and the bottom is flat). Then, gradient high temperature baking and curing is performed at a baking temperature of 200-250℃ for 30min.

[0035] 4. Nano-silver paste (silver particle size 20nm) is filled into the circuit trenches using screen printing. The screen printing mesh is 300 mesh, the squeegee pressure is 5N, the squeegee movement speed is 50mm / s, and the silver paste filling thickness is 5µm. After filling, a silver paste redistribution layer is formed by low-temperature hot pressing sintering. The sintering process is as follows: Heating stage: from room temperature to 160℃ at a rate of 5℃ / min, pressure 0MPa; Sintering stage: from 160℃ to 220℃ at a rate of 3℃ / min, pressure 10MPa; Holding stage: holding at 220℃ for 10min, pressure 10MPa; Cooling stage: from 220℃ to room temperature at a rate of 2℃ / min, pressure gradually decreasing to 0MPa; After sintering, plasma etching is performed using an O2 / Ar mixed gas as the etching source, followed by planarization treatment. The planarization treatment will... The PI layer thickness is ground to match the height of the silver paste redistribution layer, so that the surface roughness Ra of the silver paste redistribution layer is less than 0.1µm.

[0036] 5. After planarization, the third-layer PI is coated on the surface of the silver paste redistribution layer and the second-layer PI layer using a spin coating process. The coating thickness is 3µm. After exposure and development to form a protective layer with solder joint vias (the positions of the solder joint vias precisely correspond to the positions of the solder joints in the silver paste redistribution layer), the layer is cured by gradient high-temperature baking at a temperature of 200-250℃ for 30 minutes. Subsequently, nickel-gold is plated inside the solder joint vias and on the surface of the solder joints in the silver paste redistribution layer to form a second nickel-gold barrier layer. The nickel layer has a deposition thickness of 2µm, and the gold layer has a deposition thickness of 0.05µm.

[0037] 6. Apply only flux to the surface of the pads in the second nickel-gold barrier layer. Use a special ball-planting fixture that perfectly matches the hole pattern with the solder joint through-hole pattern and precisely matches the hole size with the solder ball size to accurately plant the solder balls on the pads.

[0038] 7. The wafer after ball placement is sent to a reflow oven for low-temperature reflow treatment. The peak temperature of the reflow oven is 230°C, which causes the solder balls to react with the flux and the second nickel-gold barrier layer pads to form a metallurgical bond without cold solder joints or bridging, thus completing the rewiring package.

[0039] Example 2

[0040] A low-cost redistribution package fabrication method includes:

[0041] 1. Same as Example 1 above.

[0042] 2. A spin-coating process is used to complete the first PI coating on the wafer surface, with a coating thickness of 5µm. After exposure and development to form an insulating layer with through-holes, a gradient high-temperature baking curing process is performed at a baking temperature of 200-250℃ for 35 minutes. Subsequently, nickel-gold plating is performed in the through-holes and on the wafer pad surface to form the first nickel-gold barrier layer, wherein the nickel layer deposition thickness is 3.5µm and the gold layer deposition thickness is 0.125µm.

[0043] 3. The second layer of PI is coated on the surface of the first nickel-gold barrier layer and the first layer of PI using a spin coating process. The coating thickness is 14µm. After exposure and development, a pattern layer with redistribution line trenches is formed (the trench width and spacing are both 10µm, the trench sidewalls are vertical and the bottom is flat). Then, gradient high temperature baking and curing is performed at a baking temperature of 200-250℃ for 35 minutes.

[0044] 4. Nano-silver paste (silver particle size 35nm) is filled into the circuit trenches using screen printing. The screen printing mesh is 400 mesh, the squeegee pressure is 7.5N, the squeegee movement speed is 75mm / s, and the silver paste filling thickness is 12.5µm. After filling, the silver paste redistribution layer is formed by low-temperature hot pressing sintering. The sintering process is as follows: heating stage: from room temperature to 160℃ at a heating rate of 6.5℃ / min, pressure 0MPa; sintering stage: from 160℃ to 235℃ at a heating rate of 4℃ / min, pressure 25MPa; holding stage: holding at 235℃ for 20min, pressure 25MPa; cooling stage: cooling from 235℃ to room temperature at a cooling rate of 2.5℃ / min, pressure gradually decreasing to 0MPa. After sintering, plasma etching is performed using O2 / Ar mixed gas as the etching source, followed by planarization treatment. The planarization treatment will... The PI layer thickness is ground to match the height of the silver paste redistribution layer, so that the surface roughness Ra of the silver paste redistribution layer is less than 0.1µm.

[0045] 5. After planarization, the third-layer PI is coated on the surface of the silver paste redistribution layer and the second-layer PI layer using a spin coating process. The coating thickness is 5µm. After exposure and development to form a protective layer with solder joint vias (the positions of the solder joint vias precisely correspond to the positions of the solder joints in the silver paste redistribution layer), the layer is cured by gradient high-temperature baking at a temperature of 200-250℃ for 35 minutes. Subsequently, nickel-gold is plated in the solder joint vias and on the surface of the solder joints in the silver paste redistribution layer to form a second nickel-gold barrier layer. The nickel layer has a deposition thickness of 3.5µm and the gold layer has a deposition thickness of 0.125µm.

[0046] 6. Same as Example 1 above.

[0047] 7. The wafer after ball placement is sent to a reflow oven for low-temperature reflow treatment. The peak temperature of the reflow oven is 240℃, which causes the solder balls to react with the flux and the second nickel-gold barrier layer pads to form a metallurgical bond without cold solder joints or bridging, thus completing the rewiring package.

[0048] Example 3

[0049] A low-cost redistribution package fabrication method includes:

[0050] 1. Same as Example 1 above.

[0051] 2. A spin-coating process is used to complete the first PI coating on the wafer surface, with a coating thickness of 8µm. After exposure and development to form an insulating layer with through-holes, a gradient high-temperature baking curing process is performed at a baking temperature of 200-250℃ for 40 minutes. Subsequently, nickel-gold plating is performed in the through-holes and on the wafer pads to form the first nickel-gold barrier layer, with a nickel layer deposition thickness of 5µm and a gold layer deposition thickness of 0.2µm.

[0052] 3. The second layer of PI is coated on the surface of the first nickel-gold barrier layer and the first layer of PI using a spin coating process. The coating thickness is 20µm. After exposure and development, a pattern layer with redistribution line trenches is formed (the trench width and spacing are both 10µm, the trench sidewalls are vertical and the bottom is flat). Then, gradient high temperature baking and curing is performed at a baking temperature of 200-250℃ for 40min.

[0053] 4. Nano-silver paste (silver particle size 50nm) is filled into the circuit trenches using screen printing. The screen printing mesh is 500 mesh, the squeegee pressure is 10N, the squeegee movement speed is 100mm / s, and the silver paste filling thickness is 20µm. After filling, a silver paste redistribution layer is formed by low-temperature hot pressing sintering. The sintering process is as follows: Heating stage: from room temperature to 160℃ at a rate of 8℃ / min, pressure 0MPa; Sintering stage: from 160℃ to 250℃ at a rate of 5℃ / min, pressure 40MPa; Holding stage: 250℃ for 30min, pressure 40MPa; Cooling stage: from 250℃ to room temperature at a rate of 3℃ / min, pressure gradually decreasing to 0MPa; After sintering, plasma etching is performed using an O2 / Ar mixed gas as the etching source, followed by planarization treatment. The planarization treatment will... The PI layer thickness is ground to match the height of the silver paste redistribution layer, so that the surface roughness Ra of the silver paste redistribution layer is less than 0.1µm.

[0054] 5. After planarization, the third-layer PI is coated on the surface of the silver paste redistribution layer and the second-layer PI layer using a spin coating process. The coating thickness is 8µm. After exposure and development to form a protective layer with solder joint vias (the positions of the solder joint vias precisely correspond to the positions of the solder joints in the silver paste redistribution layer), the layer is cured by gradient high-temperature baking at a temperature of 200-250℃ for 40 minutes. Subsequently, nickel-gold is plated inside the solder joint vias and on the surface of the solder joints in the silver paste redistribution layer to form a second nickel-gold barrier layer. The nickel layer has a deposition thickness of 5µm, and the gold layer has a deposition thickness of 0.2µm.

[0055] 6. Same as Example 1 above.

[0056] 7. The wafer after ball placement is sent to a reflow oven for low-temperature reflow treatment. The peak temperature of the reflow oven is 250°C, which causes the solder balls to react with the flux and the second nickel-gold barrier layer pads to form a metallurgical bond without cold solder joints or bridging, thus completing the rewiring package.

[0057] Comparative Example 1

[0058] The difference between Comparative Example 1 and Examples 1-3 is that Comparative Example 1 (refer to patent document CN116190311A in the background section above) includes the following steps:

[0059] 1. Provide a carrier made of glass / silicon wafer, and form a decomposition layer containing tape / polymer layer / photothermal conversion layer on the surface of the carrier.

[0060] 2. A patterned insulating layer with a thickness of 20~30μm is made on the decomposition layer using a photosensitive dry film. After exposure, development and curing, a first opening is formed. The first opening exposes the decomposition layer, and the opening depth is consistent with the thickness of the insulating layer.

[0061] 3. The conductive material of silver paste / copper paste is filled into the first opening by printing / chemical plating to form a conductive layer with its top extending above the insulating layer.

[0062] 4. A planarization process is performed on the conductive layer using a grinding / chemical mechanical polishing method to form a flat, inlaid structure with the insulating layer flush with it.

[0063] 5. A Ti-Cu stacked sputtering layer with a Ti layer as the bottom layer and a Cu layer as the top layer is formed on the upper surface of the embedded structure by sputtering process. Then, a photoresist layer is made on the surface of the sputtering layer by spin coating. After exposure and development, the photoresist layer is patterned to form a second opening. The second opening exposes the sputtering layer and its position corresponds precisely to the position of the planarized conductive layer.

[0064] 6. Using a patterned photoresist layer as a mask, copper metal is electroplated in the second opening based on the sputtered layer to form a metal interconnect layer.

[0065] 7. The patterned photoresist layer is removed by immersion in a tank or by single-wafer rotation spraying. Then, copper etchant and titanium etchant are used to remove the Cu and Ti layers covered by the photoresist layer to form a redistribution layer, thus completing the redistribution packaging fabrication.

[0066] Comparative Example 2

[0067] The difference between Comparative Example 2 and Examples 1-3 is that Comparative Example 2 (refer to patent document CN116564830A in the background section above) includes the following steps:

[0068] 1. A functional chip with pads is provided. A dielectric layer is prepared on the side of the functional chip where the pads are provided. An opening is made in the dielectric layer by a step-coating process. The opening exposes the pads and the width of the second opening is smaller than the width of the first opening.

[0069] 2. First, a copper metal layer is sputtered onto the surface of the dielectric layer. The functional chip with the first metal layer is placed in a nitrogen / helium / argon inert gas atmosphere at 23~28℃ and left to stand for 12~16 hours to complete the surface roughening of the first metal layer.

[0070] 3. A dielectric layer is formed on the surface of the first metal layer and a groove is etched to expose the first metal layer. A second metal layer of copper is electroplated in the groove. After removing the excess dielectric layer on the surface of the first metal layer, the functional chip is placed in an inert gas atmosphere at 23~28℃ for 12~16 hours to complete the surface roughening of the second metal layer. The first metal layer and the second metal layer together constitute a metal wiring layer, and the metal wiring layer fills and covers the opening of the dielectric layer and is electrically connected to the pad.

[0071] 4. After etching the metal wiring layer, perform photolithography to further improve the surface roughness of the metal wiring layer. Finally, coat a dielectric layer on the side of the metal wiring layer away from the functional chip to form a redistribution layer and complete the redistribution packaging preparation.

[0072] Comparative Example 3

[0073] The difference between Comparative Example 3 and Examples 1-3 is that Comparative Example 3 (refer to patent document CN120600718A) includes the following steps:

[0074] 1. Provide a carrier made of silicon dioxide / silicon / sapphire material, apply a UV adhesive layer to the surface of the carrier, and mount the chip with an Al metal layer on the front side onto the adhesive layer in a spaced array.

[0075] 2. A molding compound is formed on a carrier using a molding process, wherein the molding compound covers the chip and the metal layer on the front side of the chip is exposed.

[0076] 3. A through-hole clearance is formed on the metal layer by exposure development + etching process. SiN material is used to fill the clearance with a passivation layer so that the passivation layer is flush with the surface of the metal layer.

[0077] 4. A first PI layer is coated on the surface of the metal layer and the molding compound. After exposure and development to open the hole, a first conductive layer is formed by electroplating. The first conductive layer is misaligned with the clearance notch.

[0078] 5. A second PI layer is coated on the surface of the first PI layer. After exposure, development, patterning, and opening, a reconstructed circuit layer is formed by electroplating. The reconstructed circuit layer is electrically connected to the first conductive layer, and the projection of the reconstructed circuit layer on the front side of the chip at least partially overlaps with the avoidance notch, and the projection area does not exceed half of the projection area of ​​the subsequent solder ball.

[0079] 6. A third PI layer is coated on the surface of the second PI layer. After exposure, development and opening, a second conductive layer is formed by electroplating. The second conductive layer is electrically connected to the reconstructed circuit layer. Then, a third conductive layer (UBM metal layer) is formed by electroplating on the surface of the third PI layer and connected to the second conductive layer.

[0080] 7. Place solder balls on the third conductive layer. After placing the balls, peel off the carrier and cut it into individual products along the dicing path to complete the low-coupling rewiring package preparation.

[0081] To illustrate the rewiring described in this invention, project tests were conducted on the rewiring prepared in Examples 1-3 and Comparative Examples 1-3. The test methods are as follows:

[0082] Volume resistivity test of redistribution layers: Using the four-probe method, five test points were randomly selected on the surface of the redistribution layers prepared by each method. The volume resistivity was measured and calculated, and the average value was taken. The unit is ×10. -6 Ω·cm.

[0083] Surface roughness test of redistribution layer: Five test areas were randomly selected on the surface of each redistribution layer using a laser confocal microscope to test the surface roughness Ra value and take the average value in µm.

[0084] Circuit integrity rate after high and low temperature cycling: Each finished product was placed in a high and low temperature test chamber and subjected to multiple cycles of -40℃ (holding for 30 min) → room temperature (switching for 5 min) → 125℃ (holding for 30 min) → room temperature (switching for 5 min) as one cycle (taking 1000 cycles as an example). After the test, a fully automatic optical inspection instrument (AOI) was used to check whether there were defects such as breakage, delamination, and oxidation in the rewiring layer circuit. The number of products with intact circuits / the total number of tested products × 100% was calculated, with the unit being 0.

[0085] Unit wafer manufacturing cost: Using 8-inch wafers as the test benchmark, the total manufacturing cost of materials, equipment depreciation, labor, energy consumption, etc., for each scheme to produce a single 8-inch redistribution packaged wafer is calculated, with the unit being RMB / wafer.

[0086] Small-batch production changeover time: The total time from completing the redistribution preparation of one type of wafer to completing equipment debugging, process parameter adjustment, and achieving normal production of another type of wafer for each scheme, in hours.

[0087] Solder joint metallurgical bonding yield test: The solder joints of each finished product are fully inspected using a fully automated optical inspection (AOI) combined with a solder joint tensile test. The tensile test load is 5N. The number of solder joints without cold solder joints, bridging, or detachment is counted as the total number of solder joints × 100%. The unit is _____.

[0088] The test results are shown in the table below:

[0089] Test metrics Example 1 Example 2 Example 3 Comparative Example 1 Comparative Example 2 Comparative Example 3 <![CDATA[Volume Resistivity Test of the Redistribution Layer (×10 -6 Ω·cm)]]> 4.2 4.5 4.8 1.7 1.6 1.8 Surface roughness test of redistribution layer (µm) 0.08 0.09 0.09 0.15 0.13 0.16 Circuit integrity rate (%) after high and low temperature cycling No cracks, no open circuits, no failures No cracks, no open circuits, no failures No cracks, no open circuits, no failures 23% of the samples had cracked circuits, and 15% had open circuits. 18% of samples had stripped circuitry, and 12% had open circuits. 28% of the samples had cracked circuits, and 20% had open circuits. Unit wafer manufacturing cost (RMB / wafer) 850 845 855 2600 2550 2650 Changeover time for small-batch production (h) 2.0 1.8 2.2 12.5 11.0 13.0 Weld joint metallurgical bonding yield test (%) 99.8 99.9 99.8 82.5 85.0 80.0

[0090] As can be seen from the comparison between the embodiments and the comparative examples, although the volume resistivity of the redistribution layer prepared by the present invention is slightly higher than that of the electroplated copper comparative scheme, the value fully meets the conductivity requirements of low-cost packaging products; the surface roughness Ra value is lower, the circuit surface is smoother, and the structural forming effect is better. After high and low temperature cycle testing, the product of the present invention has no failure problems such as circuit cracking and open circuit. The resistance to ion diffusion, oxidation resistance and interlayer bonding performance are significantly better than the comparative scheme, the product reliability is significantly improved, and the unit wafer manufacturing cost is only about 1 / 3 of the comparative scheme, with a prominent cost advantage; the changeover time for small-batch production is greatly shortened, making it more suitable for multi-variety, small-batch production scenarios. At the same time, the metallurgical bonding yield of the solder joints of the present invention is close to 100%, which is much higher than that of the comparative scheme, effectively improving the overall packaging yield. While simplifying the production process, it achieves a balance between low cost and high reliability, perfectly adapting to the low-cost advanced packaging production needs of consumer electronics and other fields.

[0091] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A low-cost redistribution package fabrication method, characterized in that, Includes the following steps: S1. Confirm the model of the driver wafers and LEDs, and use a fully automated optical inspection method to detect defects in the incoming materials and reject unqualified materials; S2. The first PI coating, exposure, development and curing processes are completed sequentially on the wafer surface to form an insulating layer with through holes. Then, nickel-gold is electroplated in the through holes and on the wafer pad surface to form a first nickel-gold barrier layer. S3. The second PI coating, exposure development and curing processes are sequentially completed on the surface of the first nickel-gold barrier layer and the first PI layer to form a pattern layer with redistribution line trenches. S4. Nano silver paste is filled into the circuit trench using screen printing process, and a silver paste redistribution layer is formed by low-temperature hot pressing sintering. Then, the silver paste redistribution layer and the 2nd PI insulation layer are sequentially subjected to plasma etching cleaning and planarization treatment. S5. After planarization, the 3rd PI coating, exposure development and curing process is completed on the surface of the silver paste redistribution layer and the 2nd PI layer to form a protective layer with solder joint through holes. Then, nickel gold is plated in the solder joint through holes and on the surface of the solder joints of the silver paste redistribution layer to form a second nickel gold barrier layer. S6. Using a special ball-planting fixture that matches the solder joint pattern, the solder balls are precisely planted on the second nickel-gold barrier layer pads coated with flux. S7. The wafer after ball placement is sent to a reflow oven for low-temperature reflow treatment, so that the solder balls and the second nickel-gold barrier layer form a metallurgical bond, and the redistribution packaging is completed.

2. The low-cost redistribution package fabrication method according to claim 1, characterized in that, In S1, the incoming material defects detected by fully automated optical inspection include wafer surface scratches, LED pin deformation, substrate surface stains, pad defects / offsets, and passivation layer cracks. After inspection, unqualified incoming materials with any of the above defects are directly rejected.

3. The low-cost redistribution package fabrication method according to claim 1, characterized in that, In S2, the 1st PI coating is carried out by spin coating process with a coating thickness of 3-8µm; the 1st PI curing is carried out by gradient high temperature baking with a baking temperature of 200-250℃ and a baking time of 30-40min; the nickel layer deposition thickness of the first nickel-gold barrier layer is 2-5µm and the gold layer deposition thickness is 0.05-0.2µm.

4. The low-cost redistribution package fabrication method according to claim 1, characterized in that, In S3, the 2st PI coating adopts a spin coating process, and the coating thickness is relatively high, which is higher than that of the silver paste redistribution layer, generally 8-20µm; the 2st PI is cured by gradient high temperature baking, with a baking temperature of 200-250℃ and a baking time of 30-40min; the width and spacing of the redistribution line trench are both 10µm, and the trench sidewalls are vertical and the bottom is flat.

5. The low-cost redistribution package fabrication method according to claim 1, characterized in that, In step S4, the silver particles in the nano-silver paste have a particle size of 20-50 nm; the screen printing process uses a screen mesh of 300-500 mesh, a squeegee pressure of 5-10 N, a squeegee moving speed of 50-100 mm / s, and a silver paste filling thickness of 5-20 µm; the low-temperature hot pressing sintering process includes a heating section, a sintering section, a heat preservation section, and a cooling section; the plasma etching process uses an O2 / Ar mixed gas as the etching source, and the planarization process grinds the 2stPI layer thickness to be consistent with the height of the silver paste redistribution layer, resulting in a surface roughness Ra < 0.1 µm for the silver paste redistribution layer after planarization.

6. The low-cost redistribution package fabrication method according to claim 1, characterized in that, In step S5, the 3st PI coating is applied using a spin coating process with a coating thickness of 3-8µm; the 3st PI curing is performed by gradient high-temperature baking at a temperature of 200-250℃ for 30-40 minutes; the nickel layer of the second nickel-gold barrier layer has a deposition thickness of 2-5µm and a gold layer thickness of 0.05-0.2µm, and the solder joint via positions precisely correspond to the solder joint positions of the silver paste redistribution layer.

7. The low-cost redistribution package fabrication method according to claim 1, characterized in that, In step S6, the flux is applied only to the surface of the pads of the second nickel-gold barrier layer; the hole pattern of the ball-planting fixture is perfectly matched with the through-hole pattern of the solder joint, and the hole size is precisely matched with the solder ball size.

8. The low-cost redistribution package fabrication method according to claim 1, characterized in that, In S7, the peak temperature of the reflow oven for low-temperature reflow treatment is 230-250℃. During the reflow process, the solder balls react with the flux and the pads of the second nickel-gold barrier layer. After reflow, the solder balls and the second nickel-gold barrier layer form a metallurgical bond without cold solder joints or bridging.

9. A low-cost redistribution package fabrication method according to claim 5, characterized in that, The heating section raises the temperature from room temperature to 160°C at a rate of 5-8°C / min and a pressure of 0 MPa; the sintering section raises the temperature from 160°C to 220-250°C at a rate of 3-5°C / min and a pressure of 10-40 MPa; the holding section maintains the temperature at 220-250°C and a pressure of 10-40 MPa for 10-30 minutes; the cooling section lowers the temperature from 250°C to room temperature at a rate of 2-3°C / min and a pressure gradually decreases to 0 MPa.

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