Application of insulating multilayer clip to internal interconnection of power semiconductor device and single-phase inverter

Abstract

The application discloses an insulating multilayer Clip applied to internal interconnection of a power semiconductor device and a single-phase inverter, and relates to the technical field of chip packaging. The insulating multilayer Clip comprises a bottom shaped sheet metal thin layer, an intermediate insulating layer, a top shaped sheet metal thin layer and upper and lower copper-plated through holes; the bottom shaped sheet metal thin layer, the intermediate insulating layer and the top shaped sheet metal thin layer are sequentially stacked and are formed into a downward bottom tensile connecting groove and a bottom tensile fixing groove through die stamping; the upper and lower copper-plated through holes penetrate through the bottom shaped sheet metal thin layer, the intermediate insulating layer and the top shaped sheet metal thin layer; the upper surface of the bottom shaped sheet metal thin layer and the lower surface of the top shaped sheet metal thin layer are both provided with circuit connection patterns, stress balance patterns and positioning rings; and the upper surface of the bottom shaped sheet metal thin layer is further provided with a fixing pattern. The application improves the connection strength of the power semiconductor device in a process and a life test, and can be applied to the technical field of chip packaging.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more particularly to a multilayer interconnecting insulating clip for power semiconductor devices and a single-phase inverter. Background Technology

[0002] Currently, the top interconnection structure of the electric drive host power module in new energy vehicles mainly adopts the following form: 1) The structure of ultrasonic bonding of metal wires has a small connection cross-sectional area, low process efficiency, and poor current sharing performance when the chip is distributed. 2) Sheet metal structure: This structure increases the connection cross-sectional area and improves process efficiency, but it requires a large height space. Thicker sheet metal parts are subject to greater stress during product reliability testing, which can easily cause cracks in the brittle insulating filler material, leading to internal insulation failure. 3) Based on the sheet metal structure, two sheet metal parts are stacked in the height direction, so that the two close sheet metal parts generate a large mutual inductance, which cancels and reduces the system inductance of the entire circuit, but the stress and height space occupation problems are still not solved.

[0003] In summary, the existing top interconnect structure of the electric drive host power module has the following defects: 1) The greater stress generated during the product reliability test of thicker sheet metal parts causes cracks in the brittle insulating filler material, ultimately leading to internal insulation failure. 2) The single-layer copper sheet structure deforms severely at high temperatures, and thermal expansion and contraction in alternating hot and cold environments can easily lead to loosening and failure of electrical connections; 3) The flatness of the welding position of a single-layer copper sheet structure is difficult to control. Poor flatness can easily lead to large welding voids in the welding surface area where electrical connections are formed, increasing the difficulty of process implementation and reducing the life of the structural connection. 4) The long single-layer copper metal sheet itself has a high parasitic inductance, which greatly increases the overall parasitic inductance of the device. This leads to high current and voltage spikes during the device switching phase. In order to suppress the voltage spikes, the application needs to increase the gate drive resistance, which ultimately causes the device switching speed to decrease and the losses to increase. 5) The packaging of sheet metal parts requires a certain amount of height space, resulting in a thicker module size.

[0004] The above problems urgently need to be addressed. Summary of the Invention

[0005] To address the aforementioned technical problems, the present invention aims to: propose a multilayer insulating clip (Clip) for internal interconnection of power semiconductor devices and a single-phase inverter based on this multilayer insulating clip. By etching two thin sheet metal layers at the bottom and top into multiple circuit connection patterns of different shapes, these patterns are connected and coordinated with multiple components and circuit boards. Copper-plated through-hole structures and bottom-stretched connection grooves are introduced in local locations to supplement and improve the circuit connections, thereby enabling flexible arrangement of high-loss, high-heat-generating chips. The design of the bottom-stretched fixing groove and stress-balanced patterns improves the connection strength of the power semiconductor device during the manufacturing process and lifespan testing. The design of the positioning ring improves manufacturability. Overall, the invention meets the electrical connection requirements, thermal management requirements, and stress-life requirements of the target power semiconductor device product, enabling efficient, highly integrated, and highly flexible product development.

[0006] The first technical solution adopted in this invention is: A multilayer insulating clip for internal interconnection in power semiconductor devices is disclosed. The multilayer insulating clip includes a bottom formed sheet metal layer, an intermediate insulating layer, a top formed sheet metal layer, and upper and lower copper-plated through holes. The bottom formed sheet metal layer, the intermediate insulating layer, and the top formed sheet metal layer are stacked sequentially and formed by die stamping with downward bottom stretching connection grooves and bottom stretching fixing grooves. The upper and lower copper-plated through holes penetrate the bottom formed sheet metal layer, the intermediate insulating layer, and the top formed sheet metal layer. The upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer are provided with circuit connection patterns, stress balance patterns, and positioning rings. The upper surface of the bottom formed sheet metal layer is also provided with fixing patterns.

[0007] Furthermore, in one embodiment of the present invention, the bottom formed sheet metal layer is a sheet metal layer formed by stamping a die at the bottom, used to achieve electrical connection with components on the circuit board; the intermediate insulating layer is a thermosetting polyimide formed by material modification treatment of polyimide, used to insulatingly bond the bottom formed sheet metal layer and the top formed sheet metal layer; the top formed sheet metal layer is a sheet metal layer formed by stamping a die at the top, used to interconnect multiple circuit connection patterns through circuit design; the upper and lower copper-plated through holes include hole walls and copper-plated layers disposed on the hole walls, used to achieve electrical connection between the bottom formed sheet metal layer and the top formed sheet metal layer.

[0008] Furthermore, in one embodiment of the present invention, the circuit connection pattern is a copper foil pattern separated by adhesive coating, photolithography, and etching on the upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer, used to realize circuit topology connection; the stress balance pattern is a copper foil sheet separated on the upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer, used to realize the symmetry of the metal structure of the bottom formed sheet metal layer and the top formed sheet metal layer to suppress the warping and expansion and contraction stress of the copper foil plate; the positioning ring is a circular hole / ring etched on the upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer, used to realize the accurate bonding of the bottom formed sheet metal layer and the top formed sheet metal layer; the fixing pattern is a copper foil welding surface separated on the upper surface of the bottom formed sheet metal layer, used to form a bonding and fixing structure with the top formed sheet metal layer to offset the expansion and contraction stress of the copper foil plate.

[0009] Furthermore, in one embodiment of the present invention, the bottom stretching connection groove is a downwardly protruding connection plane formed by stamping the bottom formed sheet metal layer, the intermediate insulating layer, and the top formed sheet metal layer with a die, used to achieve planar welding with the connection area of ​​the circuit board; the bottom stretching fixing groove is a downwardly protruding fixing plane formed by stamping the bottom formed sheet metal layer, the intermediate insulating layer, and the top formed sheet metal layer with a die, used to connect and fix with the circuit board to form a connection barrier near the connection area, thereby reducing the expansion and contraction stress of the connection area.

[0010] The second technical solution adopted in this invention is: A single-phase inverter, comprising: Circuit board; The insulating multilayer Clip as described above; The bottom formed sheet metal layer of the insulating multilayer Clip is disposed on the circuit board and is used to electrically connect with the components on the circuit board to realize a single-phase inverter topology circuit.

[0011] Furthermore, in one embodiment of the present invention, the surface copper layer of the circuit substrate is etched to divide it into an upper bridge copper layer, an upper bridge gate copper layer, an upper bridge source copper layer, a lower bridge copper layer, a lower bridge gate copper layer, a lower bridge source copper layer, a first temperature sensing signal copper layer, and a second temperature sensing signal copper layer. The upper bridge copper layer is fitted with a plurality of upper bridge arm chips, and the lower bridge copper layer is fitted with a plurality of lower bridge arm chips. A thermistor is disposed on the first temperature sensing signal copper layer.

[0012] Furthermore, in one embodiment of the present invention, the upper surface of the upper bridge arm chip and the upper surface of the upper bridge arm chip are provided with a gate electrode metal layer and a source electrode metal layer, and the bottom of the upper bridge arm chip and the upper surface of the upper bridge arm chip are both drain electrode metal layers.

[0013] Furthermore, in one embodiment of the present invention, the bottom forming sheet metal thin layer of the insulating multilayer Clip is etched and divided into a first circuit connection pattern copper foil, a fixing pattern copper foil, a first stress balance pattern copper foil, and a first positioning ring pattern copper foil. The first circuit connection pattern copper foil includes a negative terminal welding pattern copper foil, an upper bridge chip gate parallel pattern copper foil, a lower bridge chip gate parallel pattern copper foil, an upper bridge chip gate welding pattern copper foil, a lower bridge chip gate welding pattern copper foil, an AC connection pattern copper foil, a lower bridge source parallel pattern copper foil, a thermistor left side welding pattern copper foil, a thermistor right side welding pattern copper foil, and a lower bridge source bottom lead-out pattern copper foil.

[0014] Furthermore, in one embodiment of the present invention, the top formed sheet metal layer of the insulating multilayer Clip is etched and divided into a second circuit connection pattern copper foil, a second stress balance pattern copper foil, and a second positioning ring pattern copper foil. The second circuit connection pattern copper foil includes a negative terminal connection pattern copper foil, an upper bridge chip gate bridging pattern copper foil, a lower bridge chip gate bridging pattern copper foil, and a thermistor connection pattern copper foil.

[0015] Further, in one embodiment of the present invention, the upper bridge copper layer, the drain electrode metal layer of the upper bridge arm chip, the source electrode metal layer of the upper bridge arm chip, the AC connection patterned copper foil, the lower bridge copper layer, the drain electrode metal layer of the lower bridge arm chip, the source electrode metal layer of the lower bridge arm chip, the lower bridge source parallel patterned copper foil, the upper and lower copper-plated vias, the negative terminal connection patterned copper foil, and the negative terminal welding patterned copper foil constitute the main circuit connection path of the single-phase inverter. The gate electrode metal layer of the upper bridge arm chip, the gate welding patterned copper foil of the upper bridge chip, the upper and lower copper-plated vias, the gate bridging patterned copper foil of the upper bridge chip, the gate parallel patterned copper foil of the upper bridge chip, the upper bridge gate copper layer, the source electrode metal layer of the upper bridge arm chip, the AC connection patterned copper foil, and the upper bridge source copper layer are all part of the main circuit connection path of the single-phase inverter. The upper bridge control circuit path of the single-phase inverter comprises the gate electrode metal layer of the lower bridge arm chip, the gate welding patterned copper foil of the lower bridge chip, the upper and lower copper plated vias, the gate bridging patterned copper foil of the lower bridge chip, the gate parallel patterned copper foil of the lower bridge chip, the lower bridge gate copper layer, the source electrode metal layer of the lower bridge arm chip, the lower bridge source parallel patterned copper foil, the negative terminal connection patterned copper foil, the lower bridge source bottom lead-out patterned copper foil, and the lower bridge source copper layer. The first temperature sensing signal copper layer, the thermistor, the thermistor left side welding patterned copper foil, the upper and lower copper plated vias, the thermistor connection patterned copper foil, the thermistor right side welding patterned copper foil, and the second temperature sensing signal copper layer constitute the thermistor signal path of the single-phase inverter.

[0016] The beneficial effects of this invention are as follows: This invention provides an internal interconnection multilayer clip for power semiconductor devices and a single-phase inverter based on this multilayer clip. By etching two thin sheet metal layers at the bottom and top into multiple circuit connection patterns of different shapes, these patterns are connected and cooperated with multiple components and circuit boards. Copper-plated through-hole structures and bottom stretching connection grooves are introduced in local locations to supplement and improve the circuit connections, thereby enabling flexible arrangement of high-loss, high-heat-generating chips. The design of the bottom stretching fixing groove and stress-balanced patterns improves the connection strength of the power semiconductor device during the process and life testing. The design of the positioning ring improves the manufacturability. Overall, this invention meets the electrical connection requirements, thermal management requirements, and stress life requirements of the target power semiconductor device product, enabling efficient, highly integrated, and highly flexible product development. Attached Figure Description

[0017] Figure 1 A cross-sectional view of a multilayer clip for internal interconnection insulation of a power semiconductor device provided in an embodiment of the present invention; Figure 2 A schematic diagram showing the layout of the upper surface of the bottom-formed sheet metal thin layer provided in an embodiment of the present invention; Figure 3 A schematic diagram showing the layout of the lower surface of the top-formed sheet metal thin layer provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a single-phase inverter provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the circuit board structure provided in an embodiment of the present invention; Figure 6 A front view of the power chip provided in an embodiment of the present invention; Figure 7 A schematic diagram of the back of a power chip provided in an embodiment of the present invention; Figure 8 A schematic diagram of the layout of the bottom copper foil of an insulating multilayer Clip provided in an embodiment of the present invention; Figure 9 for Figure 8 A schematic diagram of the layout of the copper foil in the first circuit connection pattern; Figure 10 for Figure 8 A schematic diagram of the layout of the fixed-pattern copper foil; Figure 11 A schematic diagram of the layout of the top copper foil of an insulating multilayer Clip provided in an embodiment of the present invention; Figure 12 This is a single-phase inverter topology diagram provided for an embodiment of the present invention. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0019] In the description of this invention, "multiple" means two or more. The use of "first" and "second" is for distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or the order in which the indicated technical features are presented. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention.

[0020] Reference Figure 1 , 2According to embodiment 3 of the present invention, an insulating multilayer clip for internal interconnection of power semiconductor devices is provided. The insulating multilayer clip includes a bottom formed sheet metal layer, an intermediate insulating layer, a top formed sheet metal layer, and upper and lower copper-plated through holes. The bottom formed sheet metal layer, the intermediate insulating layer, and the top formed sheet metal layer are stacked sequentially and formed by die stamping to form a downward bottom stretching connection groove and a bottom stretching fixing groove. The upper and lower copper-plated through holes penetrate the bottom formed sheet metal layer, the intermediate insulating layer, and the top formed sheet metal layer. The upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer are provided with circuit connection patterns, stress balance patterns, and positioning rings. The upper surface of the bottom formed sheet metal layer is also provided with fixing patterns.

[0021] Specifically, the insulating multilayer Clip of the present invention is a multilayer flexible circuit structure that can be applied to power semiconductor devices. The overall structure includes a bottom formed sheet metal layer 1, an intermediate insulating layer 2, a top formed sheet metal layer 3, and upper and lower copper-plated through holes 4 penetrating the bottom formed sheet metal layer 1, the intermediate insulating layer 2, and the top formed sheet metal layer 3. The bottom formed sheet metal layer 1, the intermediate insulating layer 2, and the top formed sheet metal layer 3 are stacked sequentially and formed by die stamping with downward bottom stretching connection groove 5 and bottom stretching fixing groove 6. The upper surface of the bottom formed sheet metal layer 1 and the lower surface of the top formed sheet metal layer 3 are provided with circuit connection pattern 8, stress balance pattern 10, and positioning ring 7. The upper surface of the bottom formed sheet metal layer 1 is also provided with fixing pattern 9.

[0022] As a further optional implementation, the bottom formed sheet metal layer is a sheet metal layer formed by stamping a die at the bottom, used to achieve electrical connection with components on the circuit board. The middle insulating layer is a thermosetting polyimide formed by material modification treatment of polyimide, used to insulate and bond the bottom formed sheet metal layer and the top formed sheet metal layer. The top formed sheet metal layer is a sheet metal layer formed by stamping a die at the top, used to interconnect multiple circuit connection patterns through circuit design. The upper and lower copper-plated through holes include hole walls and copper-plated layers disposed on the hole walls, used to achieve electrical connection between the bottom formed sheet metal layer and the top formed sheet metal layer.

[0023] Specifically, the bottom formed sheet metal layer 1 is a sheet metal layer (thickness 0.13-0.2mm) formed by die stamping at the bottom, which is electrically connected to the circuit board and various types of devices at the bottom; the middle insulating layer 2 is a thermosetting polyimide TPI formed by material modification of thin film insulating material polyimide PI, which facilitates the bonding of the upper and lower sheet metal layers, and at the same time serves as insulation and connection; the top formed sheet metal layer 3 is a sheet metal layer formed by die stamping at the top, which realizes the interconnection of multiple separated circuit connection patterns inside the bottom sheet metal layer through circuit design; the upper and lower copper plated through holes 4 have a thin copper plating layer, realize the interconnection of the upper and lower circuit connection patterns of the upper and lower sheet metal layers, and facilitate the layout and lead-out of small signal control circuits of devices.

[0024] As a further optional implementation, the circuit connection pattern is a copper foil pattern separated by adhesive coating, photolithography, and etching on the upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer, used to realize the circuit topology connection. The stress balance pattern is a copper foil sheet separated on the upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer, used to realize the symmetry of the metal structure of the bottom formed sheet metal layer and the top formed sheet metal layer to suppress the warping and expansion and contraction stress of the copper foil plate. The positioning ring is a circular hole / ring etched on the upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer, used to realize the accurate joining of the bottom formed sheet metal layer and the top formed sheet metal layer. The fixing pattern is a copper foil welding surface separated on the upper surface of the bottom formed sheet metal layer, used to form a bonding and fixing structure with the top formed sheet metal layer to offset the expansion and contraction stress of the copper foil plate.

[0025] Specifically, the circuit connection pattern 8 is a copper foil pattern separated by coating, photolithography, and etching, realizing the connection of various circuit topologies and integrating them into a single sheet metal layer; the stress balance pattern 10 is a single copper foil sheet that is separated and does not participate in electrical connection, ensuring the symmetry of the metal structure on both sides of the PI and suppressing the warping and thermal stress of the copper foil board; the positioning ring 7 is a circular hole or ring formed by etching, which serves as an identification and positioning reference in the process to ensure the accurate bonding of the copper foil board with other structures; the fixing pattern 9 is a single copper foil welding surface that is separated and does not participate in electrical circuit connection, forming a bonding and fixing structure of a certain area to offset the expansion and contraction stress of the copper foil board during the thermal process.

[0026] As a further optional implementation, the bottom stretching connection groove is a downwardly protruding connection plane formed by stamping the bottom formed sheet metal thin layer, the middle insulating layer and the top formed sheet metal thin layer with a mold, which is used to achieve planar welding with the connection area of ​​the circuit board. The bottom stretching fixing groove is a downwardly protruding fixing plane formed by stamping the bottom formed sheet metal thin layer, the middle insulating layer and the top formed sheet metal thin layer with a mold, which is used to connect and fix with the circuit board to form a connection barrier near the connection area, thereby reducing the expansion and contraction stress of the connection area.

[0027] Specifically, the bottom stretching connection groove 5 is a downwardly protruding connection plane formed by local die stamping, which facilitates planar welding with the devices and circuit boards of the bottom circuit board, while creating gaps in the non-connection area to facilitate filling with insulating material and ensure insulation; the bottom stretching fixing groove 6 is a downwardly protruding fixing plane formed by local die stamping, which does not participate in electrical connection, but is fixed to the bottom circuit board, forming a connection barrier near the small connection area, reducing the thermal expansion and contraction stress in the protected area, and ensuring circuit connection.

[0028] It can be recognized that the insulating multilayer Clip of the present invention can be etched and divided into multiple circuit connection patterns of different shapes on the upper and lower sheet metal layers according to the needs of different semiconductor chips (Si IGBT / SiC MOSFET / GaN HEMT), different types of additional components (thermometer / discrete bus capacitor / gate resistor / loop balancing inductor), and different power conversion topologies. It can connect and cooperate with multiple devices (including chips and other common types of devices) and the bottom circuit board (PCB / shaped double-layer Clip / ceramic substrate). Through-hole copper plating structure and bottom stretching connection groove are introduced in local positions to supplement and improve the circuit connection, thereby enabling flexible arrangement of high-loss and high-heat-generating chips. The design of bottom stretching fixing groove and stress balancing pattern improves the connection strength of power semiconductor devices in process and life test. The design of positioning ring improves process manufacturability. Overall, it meets the electrical connection requirements, thermal management requirements and stress life requirements of target power semiconductor device products, and can realize efficient, highly integrated and highly flexible product development.

[0029] Furthermore, the embodiments of the present invention significantly reduce the sheet metal thickness, reduce the difficulty of shaping, and greatly reduce the stress on the top structure during the process and subsequent reliability testing. The thinner thickness and easier shaping characteristics result in a smaller overall structural height. In addition, the integration of the drive circuit and thermistor circuit eliminates the need to reserve height space for layout lead bonding, resulting in a smaller overall thickness. Due to the reduced overall circuit height, the circuit length is significantly reduced. In addition, the mutual inductance formed by the double layer cancels out the parasitic inductance of the circuit, resulting in a reduction of nearly 60%.

[0030] Reference Figure 4 This invention provides a single-phase inverter, comprising: Circuit board 100; The aforementioned multilayer insulating Clip200; The bottom forming sheet metal layer of the insulating multilayer Clip200 is disposed on the circuit board 100 for electrical connection with the components on the circuit board 100 to realize a single-phase inverter topology circuit.

[0031] Specifically, the unidirectional inverter of this embodiment of the invention comprises a circuit board and the aforementioned insulating multilayer clip, and possesses the beneficial effects of the aforementioned insulating multilayer clip.

[0032] As a further optional implementation, the surface copper layer of the circuit board is etched to divide it into an upper bridge copper layer, an upper bridge gate copper layer, an upper bridge source copper layer, a lower bridge copper layer, a lower bridge gate copper layer, a lower bridge source copper layer, a first temperature sensing signal copper layer, and a second temperature sensing signal copper layer. Multiple upper bridge arm chips are mounted on the upper bridge copper layer, and multiple lower bridge arm chips are mounted on the lower bridge copper layer. A thermistor is disposed on the first temperature sensing signal copper layer.

[0033] Specifically, such as Figure 5 The diagram shows a schematic of the circuit board provided in an embodiment of the present invention. The copper layer on the surface of the circuit board is etched into an upper bridge copper layer 11, an upper bridge gate copper layer 131, an upper bridge source copper layer 132, a lower bridge copper layer 12, a lower bridge gate copper layer 141, a lower bridge source copper layer 142, a first temperature sensing signal copper layer 151, and a second temperature sensing signal copper layer 152. The circuit board is mounted with power chips 16, including four upper bridge arm chips 16a mounted on the upper bridge copper layer 11 and four lower bridge arm chips 16b mounted on the lower bridge copper layer 12. In addition, a thermistor 17 is provided on the first temperature sensing signal copper layer 151.

[0034] As a further optional implementation, both the upper bridge arm chip and the upper surface of the upper bridge arm chip are provided with a gate electrode metal layer and a source electrode metal layer, and the bottom of both the upper bridge arm chip and the upper bridge arm chip are provided with a drain electrode metal layer.

[0035] Specifically, such as Figure 6 and Figure 7 The figures shown are a front view and a back view of the power chip provided in the embodiment of the present invention. The upper surface of the upper bridge arm chip 16a and the lower bridge arm chip 16b includes a gate electrode metal layer 161 and a source electrode metal layer 162, and the bottom is a drain electrode metal layer 163.

[0036] As a further optional implementation, the bottom forming sheet metal layer of the insulating multilayer Clip is etched and divided into a first circuit connection pattern copper foil, a fixing pattern copper foil, a first stress balance pattern copper foil, and a first positioning ring pattern copper foil. The first circuit connection pattern copper foil includes a negative terminal welding pattern copper foil, an upper bridge chip gate parallel pattern copper foil, a lower bridge chip gate parallel pattern copper foil, an upper bridge chip gate welding pattern copper foil, a lower bridge chip gate welding pattern copper foil, an AC connection pattern copper foil, a lower bridge source parallel pattern copper foil, a thermistor left side welding pattern copper foil, a thermistor right side welding pattern copper foil, and a lower bridge source bottom lead-out pattern copper foil.

[0037] Specifically, such as Figure 8 The diagram shown is a schematic representation of the layout of the bottom copper foil of the insulating multilayer Clip provided in an embodiment of the present invention. Figure 9 and Figure 10 The figures shown are respectively Figure 8 The schematic diagram of the layout of the first circuit connection pattern copper foil and the fixed pattern copper foil shows that the bottom copper foil of the insulating multilayer Clip is etched and divided into multiple copper foil patterns, including the first circuit connection pattern copper foil 21, the fixed pattern copper foil 22, the first stress balance pattern copper foil 23, and the first positioning ring pattern copper foil 24. The circuit connection pattern copper foil 21 includes the negative terminal welding pattern copper foil 211, the upper bridge chip gate parallel pattern copper foil 212, the lower bridge chip gate parallel pattern copper foil 213, the upper bridge chip gate welding pattern copper foil 214, the lower bridge chip gate welding pattern copper foil 215, the AC connection pattern copper foil 216, the lower bridge source parallel pattern copper foil 217, the thermistor left side welding pattern copper foil 218, the thermistor right side welding pattern copper foil 219, and the lower bridge source bottom lead pattern copper foil 220.

[0038] As a further optional implementation, the top formed sheet metal layer of the insulating multilayer Clip is etched and divided into a second circuit connection pattern copper foil, a second stress balance pattern copper foil, and a second positioning ring pattern copper foil. The second circuit connection pattern copper foil includes a negative terminal connection pattern copper foil, an upper bridge chip gate bridging pattern copper foil, a lower bridge chip gate bridging pattern copper foil, and a thermistor connection pattern copper foil.

[0039] Specifically, such as Figure 11 The diagram shows the layout of the top copper foil of the insulating multilayer Clip provided in an embodiment of the present invention. As can be seen, the top copper foil of the insulating multilayer Clip is etched and divided into multiple copper foil patterns, including a second circuit connection pattern copper foil and a second stress balance pattern copper foil 32. The second circuit connection pattern copper foil includes a negative terminal connection pattern copper foil 311, an upper bridge chip gate bridging pattern copper foil 312, a lower bridge chip gate bridging pattern copper foil 313, and a thermistor connection pattern copper foil 314.

[0040] As a further optional implementation, the main circuit connection path of the single-phase inverter is composed of the upper bridge copper layer, the drain electrode metal layer of the upper bridge arm chip, the source electrode metal layer of the upper bridge arm chip, the AC connection patterned copper foil, the lower bridge copper layer, the drain electrode metal layer of the lower bridge arm chip, the source electrode metal layer of the lower bridge arm chip, the lower bridge source parallel patterned copper foil, upper and lower copper-plated vias, the negative terminal connection patterned copper foil, and the negative terminal welding patterned copper foil. The upper bridge arm chip gate electrode metal layer, the upper bridge chip gate welding patterned copper foil, the upper and lower copper-plated vias, the upper bridge chip gate bridging patterned copper foil, the upper bridge chip gate parallel patterned copper foil, the upper bridge gate copper layer, the upper bridge arm chip source electrode metal layer, the AC connection patterned copper foil, and the upper bridge source copper layer. The upper bridge control circuit path of the single-phase inverter consists of the gate electrode metal layer of the lower bridge arm chip, the gate welding patterned copper foil of the lower bridge chip, the upper and lower copper plated vias, the gate bridging patterned copper foil of the lower bridge chip, the gate parallel patterned copper foil of the lower bridge chip, the lower bridge gate copper layer, the source electrode metal layer of the lower bridge arm chip, the lower bridge source parallel patterned copper foil, the negative terminal connection patterned copper foil, the lower bridge source bottom lead-out patterned copper foil, and the lower bridge source copper layer. The lower bridge control circuit path of the single-phase inverter consists of the first temperature sensing signal copper layer, the thermistor, the thermistor left side welding patterned copper foil, the upper and lower copper plated vias, the thermistor connection patterned copper foil, the thermistor right side welding patterned copper foil, and the second temperature sensing signal copper layer.

[0041] Specifically, such as Figure 12 The diagram shown is a single-phase inverter topology diagram of a single-phase inverter provided in an embodiment of the present invention. The single-phase inverter of the present invention can realize the single-phase inverter topology circuit connection and can be expanded and replicated to form a three-phase inverter circuit for the electric drive host power module of new energy vehicles.

[0042] Main circuit connection path: Upper bridge copper layer 11 → Drain electrode metal layer 163 of upper bridge arm chip 16a → Source electrode metal layer 162 of upper bridge arm chip 16a → AC connection pattern copper foil 216 → Lower bridge copper layer 12 → Drain electrode metal layer 163 of lower bridge arm chip 16b → Source electrode metal layer 162 of lower bridge arm chip 16b → Lower bridge source parallel pattern copper foil 217 → Upper and lower layer copper plated through-holes 5 → Negative terminal connection pattern copper foil 311 → Upper and lower layer copper plated through-holes 5 → Negative terminal soldering pattern copper foil 211.

[0043] Upper bridge control loop path: Gate electrode metal layer 161 of upper bridge arm chip 16a → Gate welding patterned copper foil 214 of upper bridge chip → Upper and lower copper plated vias 5 → Gate bridging patterned copper foil 312 of upper bridge chip → Upper and lower copper plated vias 5 → Gate parallel patterned copper foil 212 of upper bridge chip → Gate copper layer 131 of upper bridge & Source electrode metal layer 162 of upper bridge arm chip 16a → AC connection patterned copper foil 216 → Source copper layer 132 of upper bridge.

[0044] The path of the lower bridge control loop is as follows: Gate electrode metal layer 161 of lower bridge arm chip 16b → Gate welding patterned copper foil 215 of lower bridge chip → Upper and lower copper plated vias 5 → Gate bridging patterned copper foil 313 of lower bridge chip → Upper and lower copper plated vias 5 → Gate parallel patterned copper foil 213 of lower bridge chip → Gate copper layer 141 of lower bridge & Source electrode metal layer 162 of lower bridge arm chip 16b → Source parallel patterned copper foil 217 of lower bridge → Upper and lower copper plated vias 5 → Negative terminal connection patterned copper foil 311 → Upper and lower copper plated vias 5 → Bottom lead-out patterned copper foil 220 of lower bridge source → Source copper layer 142 of lower bridge.

[0045] Thermistor signal path: First temperature sensing signal copper layer 151 → Thermistor 17 → Thermistor left side welded pattern copper foil 218 → Upper and lower layer copper plated through holes 5 → Thermistor connection pattern copper foil 314 → Upper and lower layer copper plated through holes 5 → Thermistor right side welded pattern copper foil 219 → Second temperature sensing signal copper layer 152.

[0046] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0047] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0048] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0050] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, as long as they achieve the technical effects of the present invention by the same means, should be included within the scope of protection of the present invention. Within the scope of protection of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A multilayer insulating clip for internal interconnection in power semiconductor devices, characterized in that, The insulating multilayer Clip includes a bottom formed sheet metal thin layer, an intermediate insulating layer, a top formed sheet metal thin layer, and upper and lower copper-plated through holes. The bottom formed sheet metal thin layer, the intermediate insulating layer, and the top formed sheet metal thin layer are stacked sequentially and formed by die stamping to create a downward bottom stretching connection groove and a bottom stretching fixing groove. The upper and lower copper-plated through holes penetrate the bottom formed sheet metal thin layer, the intermediate insulating layer, and the top formed sheet metal thin layer. The upper surface of the bottom formed sheet metal thin layer and the lower surface of the top formed sheet metal thin layer are provided with circuit connection patterns, stress balance patterns, and positioning rings. The upper surface of the bottom formed sheet metal thin layer is also provided with fixing patterns.

2. The Clip for internal interconnection insulation of power semiconductor devices according to claim 1, characterized in that, The bottom formed sheet metal layer is a sheet metal layer formed by stamping a die at the bottom, used to achieve electrical connection with components on the circuit board. The intermediate insulating layer is a thermosetting polyimide formed by material modification treatment of polyimide, used to insulate and bond the bottom formed sheet metal layer and the top formed sheet metal layer. The top formed sheet metal layer is a sheet metal layer formed by stamping a die at the top, used to interconnect multiple circuit connection patterns through circuit design. The upper and lower copper-plated through holes include hole walls and copper-plated layers disposed on the hole walls, used to achieve electrical connection between the bottom formed sheet metal layer and the top formed sheet metal layer.

3. The Clip for internal interconnection insulation of power semiconductor devices according to claim 2, characterized in that, The circuit connection pattern is a copper foil pattern separated by adhesive coating, photolithography, and etching on the upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer, used to realize circuit topology connection. The stress balance pattern is a copper foil sheet separated on the upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer, used to achieve symmetry of the metal structure of the bottom formed sheet metal layer and the top formed sheet metal layer to suppress the warping and expansion and contraction stress of the copper foil plate. The positioning ring is a circular hole / ring etched on the upper surface of the bottom formed sheet metal layer and the lower surface of the top formed sheet metal layer, used to achieve accurate bonding between the bottom formed sheet metal layer and the top formed sheet metal layer. The fixing pattern is a copper foil welding surface separated on the upper surface of the bottom formed sheet metal layer, used to form a close and fixed structure with the top formed sheet metal layer to counteract the expansion and contraction stress of the copper foil plate.

4. The multilayer insulating clip for internal interconnection of power semiconductor devices according to claim 2, characterized in that, The bottom stretching connection groove is a downwardly protruding connection plane formed by the bottom forming sheet metal layer, the middle insulating layer, and the top forming sheet metal layer through die stamping, used to achieve planar welding with the connection area of ​​the circuit board. The bottom stretching fixing groove is a downwardly protruding fixing plane formed by the bottom forming sheet metal layer, the middle insulating layer, and the top forming sheet metal layer through die stamping, used to connect and fix with the circuit board to form a connection barrier near the connection area, thereby reducing the expansion and contraction stress of the connection area.

5. A single-phase inverter, characterized in that, include: Circuit board; Insulating multilayer Clip as described in any one of claims 1 to 4; The bottom formed sheet metal layer of the insulating multilayer Clip is disposed on the circuit board and is used to electrically connect with the components on the circuit board to realize a single-phase inverter topology circuit.

6. A single-phase inverter according to claim 5, characterized in that, The surface copper layer of the circuit board is etched into an upper bridge copper layer, an upper bridge gate copper layer, an upper bridge source copper layer, a lower bridge copper layer, a lower bridge gate copper layer, a lower bridge source copper layer, a first temperature sensing signal copper layer, and a second temperature sensing signal copper layer. Multiple upper bridge arm chips are mounted on the upper bridge copper layer, and multiple lower bridge arm chips are mounted on the lower bridge copper layer. A thermistor is disposed on the first temperature sensing signal copper layer.

7. A single-phase inverter according to claim 6, characterized in that, Both the upper bridge arm chip and the upper surface of the upper bridge arm chip are provided with a gate electrode metal layer and a source electrode metal layer, and the bottom of both the upper bridge arm chip and the upper bridge arm chip are provided with a drain electrode metal layer.

8. A single-phase inverter according to claim 7, characterized in that, The bottom formed sheet metal layer of the insulating multilayer Clip is etched and divided into a first circuit connection pattern copper foil, a fixing pattern copper foil, a first stress balance pattern copper foil, and a first positioning ring pattern copper foil. The first circuit connection pattern copper foil includes a negative terminal welding pattern copper foil, an upper bridge chip gate parallel pattern copper foil, a lower bridge chip gate parallel pattern copper foil, an upper bridge chip gate welding pattern copper foil, a lower bridge chip gate welding pattern copper foil, an AC connection pattern copper foil, a lower bridge source parallel pattern copper foil, a thermistor left side welding pattern copper foil, a thermistor right side welding pattern copper foil, and a lower bridge source bottom lead-out pattern copper foil.

9. A single-phase inverter according to claim 8, characterized in that, The top shaped sheet metal layer of the insulating multilayer Clip is etched and divided into a second circuit connection pattern copper foil, a second stress balance pattern copper foil, and a second positioning ring pattern copper foil. The second circuit connection pattern copper foil includes a negative terminal connection pattern copper foil, an upper bridge chip gate bridging pattern copper foil, a lower bridge chip gate bridging pattern copper foil, and a thermistor connection pattern copper foil.

10. A single-phase inverter according to claim 9, characterized in that, The upper bridge copper layer, the drain electrode metal layer of the upper bridge arm chip, the source electrode metal layer of the upper bridge arm chip, the AC connection patterned copper foil, the lower bridge copper layer, the drain electrode metal layer of the lower bridge arm chip, the source electrode metal layer of the lower bridge arm chip, the lower bridge source parallel patterned copper foil, the upper and lower copper-plated vias, the negative terminal connection patterned copper foil, and the negative terminal welding patterned copper foil constitute the main circuit connection path of the single-phase inverter. The gate electrode metal layer of the upper bridge arm chip, the gate welding patterned copper foil of the upper bridge chip, the upper and lower copper-plated vias, the gate bridging patterned copper foil of the upper bridge chip, the gate parallel patterned copper foil of the upper bridge chip, the upper bridge gate copper layer, the source electrode metal layer of the upper bridge arm chip, the AC connection patterned copper foil, and the upper bridge source copper layer constitute the single-phase inverter. The upper bridge control loop path of the single-phase inverter consists of the gate electrode metal layer of the lower bridge arm chip, the gate welding patterned copper foil of the lower bridge chip, the upper and lower copper plated vias, the gate bridging patterned copper foil of the lower bridge chip, the gate parallel patterned copper foil of the lower bridge chip, the lower bridge gate copper layer, the source electrode metal layer of the lower bridge arm chip, the lower bridge source parallel patterned copper foil, the negative terminal connection patterned copper foil, the lower bridge source bottom lead-out patterned copper foil, and the lower bridge source copper layer. The first temperature sensing signal copper layer, the thermistor, the thermistor left side welding patterned copper foil, the upper and lower copper plated vias, the thermistor connection patterned copper foil, the thermistor right side welding patterned copper foil, and the second temperature sensing signal copper layer.

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