A power module package structure based on an insulating multi-layer clip

Abstract

The application discloses a power module packaging structure based on an insulating multilayer Clip, which comprises the insulating multilayer Clip, a power chip and a gate sintering layer. The insulating multilayer Clip comprises a first copper foil layer, an intermediate insulating layer, a second copper foil layer and a first copper-plated through hole. The first copper foil layer, the intermediate insulating layer and the second copper foil layer are sequentially stacked from top to bottom and are formed into a downward protruding chip connecting area through die stamping. The first copper-plated through hole is located at the center position of the chip connecting area and penetrates the first copper foil layer, the intermediate insulating layer and the second copper foil layer. The gate sintering layer is arranged at the center position of the lower surface of the chip connecting area. The gate of the power chip is located at the center position of the upper surface of the power chip. The gate is sintered and connected with the lower surface of the chip connecting area through the gate sintering layer. The application avoids cracking of the gate sintering layer, improves the stability of the power module packaging structure and can be applied to the technical field of chip packaging.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a power module packaging structure based on an insulating multilayer clip. Background Technology

[0002] With the rapid development of the new energy vehicle industry, the bus voltage of batteries is constantly increasing, and it is now common for new energy vehicles to be equipped with an 800V high-voltage platform architecture. Power modules play a core role in the main drive system of new energy vehicles, acting as the core power conversion and controller. To improve the performance of power modules, reducing stray inductance has become crucial in module design. Currently, one of the main solutions for reducing stray inductance in the circuit is to increase the stack-up area of ​​the power circuit. Since multilayer insulated clips (multilayer flexible circuit structures) are a more specialized stack-up structure, they can significantly reduce the stray inductance of the module. However, after sintering, multilayer insulated clips introduce new problems: the stress generated by the shrinkage of the multilayer insulated clips after sintering and cooling can easily cause cracking of the gate sintering layer of the SiC chip. Therefore, it is necessary to improve the packaging structure of power modules based on multilayer insulated clips. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a power module packaging structure based on an insulating multilayer clip. By placing the gate at the center of the upper surface of the power chip and the gate sintering layer at the center of the lower surface of the chip connection area, the area of ​​the gate sintering region of the second copper foil layer is increased, reducing the thermal stress between the gate sintering layer and the second copper foil layer and preventing cracking caused by thermal stress pulling the gate sintering layer. Furthermore, the surrounding source / emitter electrodes can form a ring-shaped source / emitter sintering region with a larger area, thereby generating greater bonding force to prevent cracking of the gate sintering layer. In addition, the U-shaped cutouts in the first copper foil sheet of the first copper foil layer allow the second copper foil sheet of the first copper foil layer to have a sufficiently long extension distance to generate plastic deformation to offset thermal stress, further preventing cracking of the gate sintering layer and improving the stability of the power module packaging structure.

[0004] The first technical solution adopted in this invention is: A power module packaging structure based on an insulating multilayer clip is disclosed. The power module packaging structure includes an insulating multilayer clip, a power chip, and a gate sintering layer. The insulating multilayer clip includes a first copper foil layer, an intermediate insulating layer, a second copper foil layer, and a first copper-plated via. The first copper foil layer, the intermediate insulating layer, and the second copper foil layer are stacked sequentially from top to bottom and formed into a downwardly protruding chip connection area by die stamping. The first copper-plated via is located at the center of the chip connection area and penetrates the first copper foil layer, the intermediate insulating layer, and the second copper foil layer. The gate sintering layer is located at the center of the lower surface of the chip connection area. The gate of the power chip is located at the center of the upper surface of the power chip. The gate is sintered and connected to the lower surface of the chip connection area through the gate sintering layer.

[0005] Furthermore, in one embodiment of the present invention, the first copper foil layer of the chip connection area includes a first copper foil sheet and a second copper foil sheet. The first copper foil sheet has a U-shaped hollow groove in the middle, and the second copper foil sheet is disposed in the U-shaped hollow groove and is arranged parallel to the two side edges of the U-shaped hollow groove.

[0006] Furthermore, in one embodiment of the present invention, the second copper foil layer of the chip connection area includes a third copper foil and a fourth copper foil. The third copper foil has a rounded corner hollow groove in the middle, and the fourth copper foil is disposed at the center of the rounded corner hollow groove. The fourth copper foil is located below the first end of the second copper foil near the inside of the U-shaped hollow groove.

[0007] Furthermore, in one embodiment of the present invention, the first copper-plated through hole penetrates the second copper foil sheet near the first end of the U-shaped hollow groove, the intermediate insulating layer, and the fourth copper foil sheet.

[0008] Furthermore, in one embodiment of the present invention, the gate sintering layer is disposed at the center of the lower surface of the fourth copper foil.

[0009] Furthermore, in one embodiment of the present invention, the power module packaging structure further includes a source / emitter sintering layer, the source / emitter sintering layer being disposed on the lower surface of the third copper foil, the source / emitter of the power chip being distributed around the gate, and the source / emitter being sintered and connected to the lower surface of the third copper foil through the source / emitter sintering layer.

[0010] Furthermore, in one embodiment of the present invention, the power module packaging structure further includes a second copper-plated through-hole, the insulating multilayer Clip further includes a second copper-plated through-hole, the second copper foil extends from the second end away from the interior of the U-shaped slot out of the chip connection area, the second copper foil layer further includes a fifth copper foil, the fifth copper foil is located on one side of the third copper foil and below the second end of the second copper foil away from the interior of the U-shaped slot, the second copper-plated through-hole penetrates the second end of the second copper foil away from the interior of the U-shaped slot, the intermediate insulating layer and the fifth copper foil.

[0011] Furthermore, in one embodiment of the present invention, the power module packaging structure further includes a plurality of power terminals, which are disposed at the edge of the insulating multilayer Clip.

[0012] Furthermore, in one embodiment of the present invention, the power module packaging structure further includes a circuit board, the insulating multilayer clip and the power chip are both disposed on the circuit board, the drain / collector of the power chip is located on the lower surface of the power chip, and the drain / collector is sintered and connected to the upper surface of the circuit board.

[0013] The beneficial effects of this invention are as follows: This invention provides a power module packaging structure based on an insulating multilayer clip. By placing the gate at the center of the upper surface of the power chip and placing the gate sintering layer at the center of the lower surface of the chip connection area, on the one hand, the area of ​​the gate sintering region of the second copper foil layer is increased, reducing the thermal stress between the gate sintering layer and the second copper foil layer, and preventing cracking caused by thermal stress pulling the gate sintering layer. On the other hand, the surrounding source / emitter can form a ring-shaped source / emitter sintering region with a larger area, thereby generating greater bonding force to avoid cracking of the gate sintering layer. In addition, the U-shaped cutout of the first copper foil sheet in the first copper foil layer allows the second copper foil sheet of the first copper foil layer to have a sufficiently long extension distance to generate plastic deformation to offset thermal stress, further avoiding cracking of the gate sintering layer and improving the stability of the power module packaging structure. Attached Figure Description

[0014] Figure 1 This is a top view of the power module packaging structure based on an insulating multilayer clip provided in an embodiment of the present invention; Figure 2 The left view of the power module packaging structure based on the insulating multilayer Clip provided in the embodiment of the present invention; Figure 3 A partial cross-sectional view of a power module packaging structure based on an insulating multilayer clip provided in an embodiment of the present invention; Figure 4This is a partial perspective view of a power module packaging structure based on an insulating multilayer clip, provided for an embodiment of the present invention.

[0015] Figure label: 11. First copper foil layer; 111. First copper foil sheet; 112. Second copper foil sheet; 12. Intermediate insulating layer; 13. Second copper foil layer; 131. Third copper foil sheet; 132. Fourth copper foil sheet; 133. Fifth copper foil sheet; 14. First copper-plated through-hole; 15. Second copper-plated through-hole; 20. Power chip; 21. Gate; 22. Source / emitter; 30. Gate sintered layer; 40. Source / emitter sintered layer; 50. Power terminal. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0017] In the description of this invention, "multiple" means two or more. The use of "first" and "second" is for distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or the order in which the indicated technical features are presented. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention.

[0018] In the prior art, sintering an insulating multilayer clip requires preheating, heat preservation, and cooling stages. Due to the mismatch between the thermal expansion coefficient of the insulating multilayer clip and the chip, the shrinkage rate of the insulating multilayer clip is faster than that of the chip during the cooling stage, resulting in thermal stress between the insulating multilayer clip and the chip. When the gate 21 is not centered, the area of ​​the gate 21 of the chip is small and not centered, the sintering area is small, and the generated thermal stress is high. Excessive stress will cause the sintering layer 30 of the chip gate to crack, ultimately leading to circuit connection failure.

[0019] Reference Figure 1 , 2According to embodiments 3 and 4, this invention provides a power module packaging structure based on an insulating multilayer clip. The power module packaging structure includes an insulating multilayer clip, a power chip 20, and a gate sintering layer 30. The insulating multilayer clip includes a first copper foil layer 11, an intermediate insulating layer 12, a second copper foil layer 13, and a first copper-plated through-hole 14. The first copper foil layer 11, the intermediate insulating layer 12, and the second copper foil layer 13 are stacked sequentially from top to bottom and formed by die stamping to form a downwardly protruding chip connection area. The first copper-plated through-hole 14 is located at the center of the chip connection area and penetrates the first copper foil layer 11, the intermediate insulating layer 12, and the second copper foil layer 13. The gate sintering layer 30 is located at the center of the lower surface of the chip connection area. The gate 21 of the power chip 20 is located at the center of the upper surface of the power chip 20. The gate 21 is sintered and connected to the lower surface of the chip connection area through the gate sintering layer 30.

[0020] Specifically, to address the issue of gate sintering layer 30 cracking during the sintering of the insulating multilayer clip, this embodiment of the invention improves the power module packaging structure. By stamping the first copper foil layer 11, the intermediate insulating layer 12, and the second copper foil layer 13 with a die to form a downwardly protruding chip connection area, and by placing the gate 21 at the center of the upper surface of the power chip 20 and the gate sintering layer 30 at the center of the lower surface of the chip connection area, the area of ​​the gate sintering region of the second copper foil layer 13 is increased, reducing the thermal stress between the gate sintering layer 30 and the second copper foil layer 13, thus preventing the gate sintering layer 30 from cracking and improving the stability of the power module packaging structure.

[0021] It should be noted that the power module packaging structure of this embodiment has multiple downwardly protruding chip connection areas, the specific number of which can be designed according to actual needs. Figure 1 The CCP has shown eight chip connection areas, each corresponding to one of the eight power chips. The structure of the chip connection area in the lower right corner is shown as an example. The structures of the other chip connection areas are similar and will not be described again.

[0022] Reference Figure 1 , 3 4. Further, as an optional implementation, the first copper foil layer 11 of the chip connection area includes a first copper foil sheet 111 and a second copper foil sheet 112. The first copper foil sheet 111 has a U-shaped hollow groove in the middle, and the second copper foil sheet 112 is disposed in the U-shaped hollow groove and is arranged parallel to the two sides of the U-shaped hollow groove.

[0023] In this embodiment of the invention, the U-shaped hollow groove of the first copper foil sheet 111 in the first copper foil layer 11 allows the second copper foil sheet 112 of the first copper foil layer 11 to have a sufficiently long extension distance to generate plastic deformation in order to offset thermal stress, thereby further improving the stability of the power module packaging structure.

[0024] Reference Figure 3 and 4 As an optional implementation, the second copper foil layer 13 of the chip connection area includes a third copper foil 131 and a fourth copper foil 132. The third copper foil 131 has a rounded corner hollow groove in the middle, and the fourth copper foil 132 is located at the center of the rounded corner hollow groove. The fourth copper foil 132 is located below the first end of the second copper foil 112 near the inside of the U-shaped hollow groove.

[0025] Specifically, the fourth copper foil 132 is used to sinter and connect with the gate 21 of the power chip 20 through the gate sintering layer 30, and the third copper foil 131 is used to sinter and connect with the source / emitter 22 of the power chip 20 through the source / emitter sintering layer 40.

[0026] Reference Figure 3 and 4 As an optional implementation, the first copper-plated through hole 14 penetrates the first end of the second copper foil 112 near the inside of the U-shaped hollow groove, the middle insulating layer 12, and the fourth copper foil 132.

[0027] Specifically, the first copper-plated through-hole 14 is used to realize the electrical connection between the second copper foil 112 and the fourth copper foil 132, thereby realizing the transmission of current from the second copper foil 112 to the fourth copper foil 132 and then to the gate sintering layer 30 and the gate 21 of the power chip 20.

[0028] Reference Figure 3 and 4 As an optional implementation, the gate sintering layer 30 is disposed at the center of the lower surface of the fourth copper foil 132.

[0029] Reference Figure 3 As an optional implementation, the power module packaging structure further includes a source / emitter sintering layer 40, which is disposed on the lower surface of the third copper foil 131. The source / emitter 22 of the power chip 20 is distributed around the gate 21, and the source / emitter 22 is sintered and connected to the lower surface of the third copper foil 131 through the source / emitter sintering layer 40.

[0030] Specifically, the source / emitter 22 of the power chip 20 is sintered and connected to the lower surface of the third copper foil 131 through the source / emitter sintering layer 40. Since the fourth copper foil 132 is located inside the rounded corner hollow groove of the third copper foil 131, the gate 21 and the source / emitter 22 of the power chip 20 are insulated.

[0031] Reference Figure 1 and 4As an optional implementation, the insulating multilayer Clip further includes a second copper-plated through-hole 15, the second copper foil 112 extends from the second end away from the interior of the U-shaped cutout into the chip connection area, the second copper foil layer 13 also includes a fifth copper foil 133, the fifth copper foil 133 is located on one side of the third copper foil 131 and is located below the second end of the second copper foil 112 away from the interior of the U-shaped cutout, the second copper-plated through-hole 15 penetrates the second end of the second copper foil 112 away from the interior of the U-shaped cutout, the intermediate insulating layer 12 and the fifth copper foil 133.

[0032] Specifically, the second copper-plated through-hole 15 is used to realize the electrical connection between the second copper foil 112 and the fifth copper foil 133, thereby realizing the transmission of current from the fifth copper foil 133 to the second copper foil 112, and finally realizing the current path from the fifth copper foil 133 to the gate 21 of the power chip 20. Since the fifth copper foil 133 is insulated from the third copper foil 131, the insulation between the gate 21 and the source / emitter 22 of the power chip 20 is also guaranteed.

[0033] Reference Figure 1 and 2 As an optional implementation, the power module package structure further includes a plurality of power terminals 50, which are disposed at the edge of the insulating multilayer Clip.

[0034] Specifically, the power terminal 50 is located at the edge of the insulating multilayer Clip for connection to external devices.

[0035] As a further optional implementation, the power module packaging structure also includes a circuit board, with the insulating multilayer clip and the power chip 20 both disposed on the circuit board. The drain / collector of the power chip 20 is located on the lower surface of the power chip 20, and the drain / collector is sintered and connected to the upper surface of the circuit board.

[0036] The current path for driving gate 21 in this embodiment of the invention differs from that in the previous version. Specifically, as follows: Figure 4 The arrow indicating the current I flows from the circuit board to the fifth copper foil 133 of the second copper foil layer 13, from the fifth copper foil 133 through the second copper-plated through-hole 15 to the second copper foil 112 of the first copper foil layer 11, from the second copper foil 112 to above the gate 21, and then through the first copper-plated through-hole 14 to the fourth copper foil 132 of the second copper foil layer 13, and finally through the gate sintering layer 30 and the gate 21.

[0037] As can be seen, the current in this embodiment of the invention will switch between the first copper foil layer 11 and the second copper foil layer 13. This can achieve the insulation between the gate 21 and the source / emitter 22 after the position of the gate 21 of the power chip 20 and the position of the gate sintering layer 30 are centered.

[0038] Since the gate 21 and the fourth copper foil 132 of the second copper foil layer 13 are connected through the gate sintering layer 30, the sintering area can be increased by increasing the size of the fourth copper foil 132. Placing the gate sintering layer 30 at the center of the chip connection area extends the length of the second copper foil 112 in the first copper foil layer 11. Due to the good plasticity of the copper foil, the thermal stress generated during cooling can be buffered by the plastic deformation of the copper foil. Furthermore, increasing the sintering area helps improve the sintering layer's ability to resist thermal stress generated during cooling. The upper and lower layer current conversion structure can prevent short circuits. The shear stress of the gate sintering layer 30 in the power module packaging structure of this embodiment is between 40-60 MPa, which is significantly improved compared to the previous version (150 MPa).

[0039] It can be understood that by placing the gate at the center of the upper surface of the power chip and placing the gate sintering layer at the center of the lower surface of the chip connection area, the embodiments of the present invention increase the area of ​​the gate sintering region of the second copper foil layer, reducing the thermal stress between the gate sintering layer and the second copper foil layer, and preventing cracking caused by thermal stress pulling the gate sintering layer. On the other hand, the surrounding source / emitter can form a ring-shaped source / emitter sintering region with a larger area, thereby generating greater bonding force to avoid cracking of the gate sintering layer. In addition, by setting the U-shaped hollow groove of the first copper foil sheet in the first copper foil layer, the second copper foil sheet of the first copper foil layer has a sufficiently long extension distance to generate plastic deformation to offset the thermal stress, further avoiding cracking of the gate sintering layer and improving the stability of the power module packaging structure.

[0040] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0041] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0042] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0043] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0044] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, as long as they achieve the technical effects of the present invention by the same means, should be included within the scope of protection of the present invention. Within the scope of protection of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A power module packaging structure based on an insulating multilayer clip, characterized in that, The power module packaging structure includes an insulating multilayer clip, a power chip, and a gate sintering layer. The insulating multilayer clip includes a first copper foil layer, an intermediate insulating layer, a second copper foil layer, and a first copper-plated via. The first copper foil layer, the intermediate insulating layer, and the second copper foil layer are stacked sequentially from top to bottom and formed into a downwardly protruding chip connection area by die stamping. The first copper-plated via is located at the center of the chip connection area and penetrates the first copper foil layer, the intermediate insulating layer, and the second copper foil layer. The gate sintering layer is located at the center of the lower surface of the chip connection area. The gate of the power chip is located at the center of the upper surface of the power chip. The gate is sintered to the lower surface of the chip connection area through the gate sintering layer, wherein: The first copper foil layer of the chip connection area includes a first copper foil sheet and a second copper foil sheet. The first copper foil sheet has a U-shaped hollow groove in the middle, and the second copper foil sheet is disposed in the U-shaped hollow groove and is arranged parallel to the two sides of the U-shaped hollow groove. The second copper foil layer of the chip connection area includes a third copper foil and a fourth copper foil. The third copper foil has a rounded corner hollow groove in the middle. The fourth copper foil is located at the center of the rounded corner hollow groove and is located below the first end of the second copper foil near the inside of the U-shaped hollow groove.

2. The power module packaging structure based on a multilayer insulating clip according to claim 1, characterized in that, The first copper-plated through hole penetrates the second copper foil sheet near the first end of the U-shaped hollow groove, the intermediate insulating layer, and the fourth copper foil sheet.

3. The power module packaging structure based on a multilayer insulating clip according to claim 1, characterized in that, The gate sintering layer is disposed at the center of the lower surface of the fourth copper foil.

4. The power module packaging structure based on a multilayer insulating clip according to claim 1, characterized in that, The power module packaging structure further includes a source / emitter sintering layer, which is disposed on the lower surface of the third copper foil. The source / emitter of the power chip is distributed around the gate, and the source / emitter is sintered and connected to the lower surface of the third copper foil through the source / emitter sintering layer.

5. A power module packaging structure based on an insulating multilayer clip according to claim 1, characterized in that, The insulating multilayer Clip also includes a second copper-plated through-hole, the second copper foil extending from the second end away from the interior of the U-shaped groove out of the chip connection area, the second copper foil layer also includes a fifth copper foil, the fifth copper foil is located on one side of the third copper foil and below the second end of the second copper foil away from the interior of the U-shaped groove, the second copper-plated through-hole penetrates the second end of the second copper foil away from the interior of the U-shaped groove, the intermediate insulating layer and the fifth copper foil.

6. The power module packaging structure based on a multilayer insulating clip according to claim 1, characterized in that, The power module packaging structure also includes several power terminals, which are disposed at the edge of the insulating multilayer Clip.

7. A power module packaging structure based on an insulating multilayer clip according to any one of claims 1 to 6, characterized in that, The power module packaging structure also includes a circuit board, on which the insulating multilayer clip and the power chip are both disposed. The drain / collector of the power chip is located on the lower surface of the power chip, and the drain / collector is sintered and connected to the upper surface of the circuit board.

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