Test device, test method and test system
By using machine learning models to predict wafer process parameters and automatically adjust die trimming values, the problem of lengthy and costly wafer testing processes is solved, achieving efficient and low-cost wafer testing.
CN122193867APending Publication Date: 2026-06-12NUVOTON
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NUVOTON
- Filing Date
- 2025-06-19
- Publication Date
- 2026-06-12
Smart Images
Figure CN122193867A_ABST
Abstract
The present application provides a test device, a test method and a test system. The test device includes a storage circuit and a processing circuit. The storage circuit stores a machine learning model. The processing circuit accesses the storage circuit. In a training mode, the processing circuit loads the machine learning model and inputs wafer acceptance test sample data of each sample die of a sample wafer to the machine learning model to train the machine learning model to predict a process parameter of each sample die of the sample wafer. In a test mode, the processing circuit inputs wafer acceptance test data of each test die of a test wafer to the machine learning model to predict a process parameter of each test die of the test wafer. The processing circuit converts the process parameter of each test die to generate a trimming value and provides the trimming value to a first functional circuit of the corresponding test die.
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