Chip testing method, device, electronic equipment, medium and product

Abstract

The disclosure provides a chip test method, relates to the field of artificial intelligence technology, and particularly relates to the field of integrated circuit silicon pre-verification. The method comprises the following steps: obtaining an initial control sequence and an initial waveform sequence required for target chip testing; control instructions in the initial control sequence and waveform statements in the initial waveform sequence are transmitted along different physical paths inside the target chip and have different transmission delays; logical handover points between the control instructions and the waveform statements in the initial control sequence and the initial waveform sequence are determined respectively, and a handover delay corresponding to the logical handover points is determined through simulation; based on the logical handover points, the handover delay is written into the initial control sequence and the initial waveform sequence respectively to obtain a time-delay control sequence and a time-delay waveform sequence; and the target chip is tested by using the time-delay control sequence and the time-delay waveform sequence. The disclosure realizes the timing alignment of the control instructions and the waveform statements inside the target chip, compensates for the transmission delay difference, and shortens the single-chip test time.

Description

Technical Field

[0001] This relates to the field of artificial intelligence technology, particularly to the field of pre-silicon verification for integrated circuits. Specifically, it involves a chip testing method, apparatus, electronic device, medium, and product. Background Technology

[0002] In the field of pre-silicon verification of integrated circuits, test vector simulation has evolved into a complex mode of coordinated execution of control instructions and waveform statements. Control instructions and waveform statements are transmitted along different physical paths within the chip, resulting in different transmission delays. Timing alignment must be achieved at the logic junction point; otherwise, initialization failures, link errors, or misjudgments of test results will occur, directly impacting the chip's first-pass yield on ATE (Automatic Test Equipment) machines.

[0003] The relevant technology involves engineers manually inserting redundant waiting time at logical handover points based on their understanding of the protocol, and determining the handover delay through repeated full-scale simulations and trial and error. However, this method not only reduces testing efficiency and lengthens the verification iteration cycle due to excessive conservative margins, but also cannot effectively compensate for the delay dispersion introduced by the multi-level transmission paths within the chip at different process corners, thus making it difficult to guarantee high-precision timing alignment between control instructions and waveform statements. Summary of the Invention

[0004] This disclosure provides a chip testing method, apparatus, electronic device, medium, and product.

[0005] According to one aspect of this disclosure, a chip testing method is provided, the method comprising: Obtain the initial control sequence and initial waveform sequence required for target chip testing; wherein, the control commands in the initial control sequence and the waveform statements in the initial waveform sequence are transmitted along different physical paths inside the target chip, and the transmission delays are different; The logical handover points between the control command and the waveform statement are determined in the initial control sequence and the initial waveform sequence, respectively, and the handover delay corresponding to the logical handover points is determined by simulation. Based on the logical handover point, the handover delay is written into the initial control sequence and the initial waveform sequence respectively to obtain the delay control sequence and the delay waveform sequence; The target chip is tested using the time delay control sequence and the time delay waveform sequence.

[0006] According to another aspect of this disclosure, a chip testing apparatus is provided, the apparatus comprising: The sequence acquisition module is used to acquire the initial control sequence and initial waveform sequence required for target chip testing; wherein, the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence are transmitted along different physical paths inside the target chip, and the transmission delays are different; The delay determination module is used to determine the logical handover point between the control command and the waveform statement in the initial control sequence and the initial waveform sequence, respectively, and to determine the handover delay corresponding to the logical handover point through simulation; The delay writing module is used to write the handover delay into the initial control sequence and the initial waveform sequence respectively based on the logical handover point, so as to obtain the delay control sequence and the delay waveform sequence; The chip testing module is used to test the target chip using the time delay control sequence and the time delay waveform sequence.

[0007] According to another aspect of this disclosure, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed, enables the at least one processor to perform the chip testing method described in any embodiment of this disclosure.

[0008] According to another aspect of this disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to perform the chip testing method described in any embodiment of this disclosure.

[0009] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the chip testing method described in any embodiment of this disclosure.

[0010] This disclosure achieves timing alignment of control commands and waveform statements within the target chip, compensates for transmission delay differences, and shortens single-chip testing time.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1This is a flowchart of a chip testing method provided according to an embodiment of the present disclosure; Figure 2 This is a flowchart of another chip testing method provided according to an embodiment of the present disclosure; Figure 3 This is a schematic diagram of a chip testing device provided according to an embodiment of the present disclosure; Figure 4 A block diagram of an electronic device used to implement a chip testing method according to an embodiment of the present disclosure. Detailed Implementation

[0013] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0014] Figure 1 This is a flowchart illustrating a chip testing method according to an embodiment of this disclosure. This embodiment is applicable to chip testing scenarios in the pre-silicon verification stage and ATE mass production testing stage of integrated circuits, where a test environment needs to be established through control instructions and functional stimuli executed through waveform statements. Examples include initialization and wake-up of SoC (System on Chip) chips, high-speed interface link training, firmware download, and multi-power domain reset and release, where precise timing alignment of control instructions and waveform statements is required at logical intersection points. This method can be executed by a chip testing device, which can be implemented in hardware and / or software and can be configured in an electronic device. (Reference) Figure 1 The method specifically includes the following: S101. Obtain the initial control sequence and initial waveform sequence required for testing the target chip; wherein, the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence are transmitted along different physical paths inside the target chip, and the transmission delays are different; S102. Determine the logical handover point between the control command and the waveform statement in the initial control sequence and the initial waveform sequence respectively, and determine the handover delay corresponding to the logical handover point through simulation; S103. Based on the logical handover point, the handover delay is written into the initial control sequence and the initial waveform sequence respectively to obtain the delay control sequence and the delay waveform sequence; S104. The target chip is tested using the time delay control sequence and the time delay waveform sequence.

[0015] The initial control sequence is a set of control instructions arranged in a preset execution logical order. These control instructions drive the JTAG (Joint Test Action Group) interface state machine and operate the chip's internal test data registers. The initial waveform sequence is a set of waveform statements arranged in a logical execution order. These waveform statements describe the voltage level or voltage change of a function pin at a specific moment. The initial control sequence and the initial waveform sequence are independent of each other. Optionally, the control instructions are TDR (Test Data Register Control Vector) control vectors, and the waveform statements are SVF (Serial Vector Format) function vectors.

[0016] In the initial control sequence, control instructions and waveform statements in the initial waveform sequence are transmitted along different physical paths within the target chip. The target chip is the integrated circuit chip to be tested by ATE (Automatic Test Equipment), which contains a JTAG interface path and a functional pin path. The physical routing and logic units traversed by these two paths differ within the chip. In the initial control sequence, control instructions are serially shifted into the target chip via the JTAG interface to perform control operations such as register configuration, reset domain release, and test mode switching. In the initial waveform sequence, waveform statements are parallelly fed into the target chip via functional pins to perform functional stimulus operations such as clock locking, firmware download, and link training.

[0017] Control commands are transmitted step-by-step through the TAP (Test Access Port Controller) and internal register links, while waveform statements are directly driven via function pins and the analog front end. The transmission delays experienced by control commands and waveform statements within the chip differ. This difference in transmission delay causes the control commands and waveform statements to not be naturally synchronized in time, leading to timing mismatches.

[0018] To address this, logical handover points between control instructions and waveform statements are determined in both the initial control sequence and the initial waveform sequence. These logical handover points are the points of interaction where execution phase switching occurs between the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence during the target chip testing process. In the global execution logic, one side of the logical handover point contains the control instructions, and the other side contains the waveform statements.

[0019] After the logical handover points are determined, the execution process of the initial control sequence and initial waveform sequence is simulated using a timing simulation environment. The start and end times of each control instruction segment and each waveform statement segment are recorded, thereby determining the handover delay corresponding to each logical handover point. The handover delay refers to the actual waiting time at the logical handover point, obtained through timing simulation, caused by the difference in physical paths between the control instruction and the waveform statement. To more clearly describe the handover delay, let's take the switch from executing control instructions to executing waveform statements as an example. The handover delay can be obtained by calculating the time difference between the start time of the continuous control instructions and the start time of the first waveform statement. The handover delay includes both the actual execution time of the continuous control instructions and the waiting time after the continuous control instructions are completed. Optionally, the handover delay can be directly obtained from the simulated waveform.

[0020] Based on each logical junction point, the corresponding junction delay is written into the initial control sequence and the initial waveform sequence, respectively. The writing operation involves determining the delay writing position in the initial control sequence and the initial waveform sequence based on the logical junction point, and writing the junction delay corresponding to the logical junction point into the corresponding delay writing position. This yields the delay control sequence and the delay waveform sequence. Both the delay control sequence and the delay waveform sequence already contain timing compensation information for physical path differences. This allows the timing intervals originally implicit in the initial control sequence and the initial waveform sequence to be explicitly expressed as precise waiting periods, ensuring that control commands and waveform statements carry timing calibration information matching the actual physical delay of the target chip within their respective sequences.

[0021] Finally, the target chip is tested using a delay control sequence and a delay waveform sequence. Since the delay control sequence and the delay waveform sequence contain simulated and verified handover delays, the execution timing of the two types of instructions within the chip can be precisely aligned at the logic handover point, compensating for the transmission delay differences caused by different physical paths. Optionally, the delay control sequence and the delay waveform sequence are loaded onto the ATE (Automatic Test Equipment). The delay control sequence is serially shifted into the target chip via the JTAG interface to establish the test environment, while the delay waveform sequence is parallelly fed into the target chip via functional pins to perform functional stimuli in the test environment.

[0022] This disclosed technical solution determines the handover delay at the logical junction point between the initial control sequence and the initial waveform sequence during the simulation phase, and writes this handover delay into the sequence to generate a time-delayed control sequence and a time-delayed waveform sequence. This allows the control instructions in the time-delayed control sequence and the waveform statements in the time-delayed waveform sequence to automatically wait for the corresponding duration when they reach the logical junction point. This compensates for the transmission delay difference caused by the two types of instructions being transmitted along different physical paths within the target chip, achieving timing alignment between the control instructions and the waveform statements. Therefore, when testing the target chip using the time-delayed control sequence and the time-delayed waveform sequence, manual timing debugging on the ATE machine is unnecessary, avoiding initialization failures or test misjudgments caused by timing deviations. This shortens the single-chip testing time and improves the first-pass yield and mass production testing efficiency of the target chip on the ATE machine.

[0023] In an optional embodiment, determining the logical handover point between the control instruction and the waveform statement in the initial control sequence and the initial waveform sequence respectively includes: traversing the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence as sequence elements according to global execution logic; if the current sequence element and the previous sequence element come from different sequences, determining the sequences to which the current sequence element and the previous sequence element belong and their positions in the sequences respectively; in the sequence to which the current sequence element belongs, determining the position between the current sequence element and its subsequent adjacent sequence element as the logical handover point in that sequence; in the sequence to which the previous sequence element belongs, determining the position between the previous sequence element and its subsequent adjacent sequence element as the logical handover point in that sequence.

[0024] During the traversal of the initial control sequence and initial waveform sequence according to the global execution logic, control instructions and waveform statements are collectively referred to as sequence elements, both of which participate in the determination of logical junction points as sequence elements. The global execution logic refers to the execution order of control instructions and waveform statements within the target chip testing process, determined by the chip's internal hardware state dependencies, and which must be followed between control operations and functional stimulus operations.

[0025] According to the global execution logic, the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence are traversed as sequence elements, and the source sequence of the current sequence element is compared with that of the previous sequence element. If it is detected that the current sequence element and the previous sequence element come from different sequences, such as the current sequence element coming from the initial control sequence and the previous sequence element coming from the initial waveform sequence, or the current sequence element coming from the initial waveform sequence and the previous sequence element coming from the initial control sequence, it indicates that a type switch of control instructions and waveform statements has occurred at this point. In the sequence to which the current sequence element belongs, the position between the current sequence element and its next adjacent sequence element is determined as a logical intersection point in that sequence; at the same time, in the sequence to which the previous sequence element belongs, the position between the previous sequence element and its next adjacent sequence element is determined as another logical intersection point in that sequence. Thus, each type switch will determine a logical intersection point in both the initial control sequence and the initial waveform sequence, completely marking all the connection positions of control instructions and waveform statements in the collaborative execution flow.

[0026] The above technical solution iterates through the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence according to the global execution logic. It identifies the type switching position based on whether the source sequences of adjacent sequence elements are the same, and determines the logical handover point in each sequence. This approach relies solely on the source type and execution order of the sequence elements themselves, automatically and accurately identifying all connection positions of control instructions and waveform statements in the collaborative execution process without simulation. This avoids omissions or misalignments that may occur when manually identifying each point according to the protocol. It provides a reliable and complete location basis for subsequent simulation to extract the handover delay for each logical handover point, thereby ensuring that the delay control sequence and delay waveform sequence after the handover delay is written can fully cover all timing alignment requirements.

[0027] In an optional embodiment, testing the target chip using the delay control sequence and the delay waveform sequence includes: inputting the delay control sequence into the target chip through a joint test action group interface to establish a test environment for the target chip; and after the test environment is established, inputting the delay waveform sequence into the target chip through a functional pin channel to perform performance testing on the target chip.

[0028] The delay control sequence and delay waveform sequence, which have been written to the corresponding handover delay at each logical handover point, are released as a formal test vector file. Optionally, the handover delay exists in the form of a wait instruction in the delay control sequence and delay waveform sequence. This test vector file is loaded into the ATE (Automatic Test Equipment) machine, which parses the control instructions and wait instructions in the delay control sequence, as well as the waveform statements and wait instructions in the delay waveform sequence, and configures the digital channel and timer parameters.

[0029] During the field testing or mass production testing phase, the ATE (Automatic Test Equipment) tool first serially feeds the delay control sequence into the target chip via the Joint Test Action Group (JTAG) interface. The JTAG interface conforms to the IEEE 1149.1 standard and includes signal pins for test clock, test mode selection, test data input, and test data output. Each control instruction in the delay control sequence sequentially executes register configuration, reset domain release, and clock enable operations. Since the sequence already includes wait instructions inserted at each logic junction, a hardware timer is triggered at the junction between control instructions to wait for the corresponding junction delay. This ensures that the timing intervals of each state establishment step within the target chip are consistent with the simulation verification results, thereby stably establishing the test environment. The test environment refers to the measurable state achieved by the target chip after completing register configuration, reset domain release, and clock enable operations.

[0030] After the test environment is established, the ATE (Automatic Test Equipment) switch to the function pin channel, through which the delay waveform sequence is fed into the target chip in parallel. The function pin channel refers to the physical signal path between the ATE and the high-speed function pins of the target chip. The waveform statements in the delay waveform sequence drive the function pins to generate high-speed excitations. Because the handover delay is pre-written at the logical junctions between waveform statements within the sequence, timing alignment is automatically achieved from the completion of control instruction execution to the start of waveform statement execution, ensuring precise matching between the start edge of the function excitation and the test environment readiness time. Thus, the target chip performs functional operations and generates responses according to the delay waveform sequence under the preset test environment. The ATE collects the responses and compares them with the expected values ​​to complete the performance test.

[0031] The above technical solution inputs the pre-written handover delay control sequence into the target chip via the joint test action group interface. This allows each control command to automatically wait for the preset handover delay during execution, thus establishing a stable and orderly test environment. After the test environment is established, the pre-written handover delay waveform sequence is input into the target chip via the function pin channel. This ensures that the start time of the waveform statement is precisely aligned with the test environment readiness time, driving the target chip to perform performance testing under correct timing conditions. By pre-embedding timing compensation information within the sequence, the ATE equipment can complete the entire process of test environment establishment and functional stimulation in one go without manual intervention after loading the delay control sequence and delay waveform sequence. This avoids timing deviations caused by differences in transmission delays between control commands and waveform statements, ensuring the test stability and first-pass yield of the target chip in mass production testing.

[0032] Figure 2 This is a flowchart of another chip testing method provided according to an embodiment of the present disclosure; this embodiment is an optional solution proposed based on the above embodiments.

[0033] See Figure 2 The chip testing method provided in this embodiment includes: S201. Obtain the initial control sequence and initial waveform sequence required for testing the target chip; wherein, the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence are transmitted along different physical paths inside the target chip, and the transmission delays are different.

[0034] S202. Determine the logical handover point between the control command and the waveform statement in the initial control sequence and the initial waveform sequence, respectively.

[0035] S203. Based on the logical junction point, the initial control sequence and the initial waveform sequence are split to obtain control instruction fragments and waveform statement fragments.

[0036] The control instruction fragment refers to the subset of instructions obtained by splitting the initial control sequence based on logical intersection points. It consists of consecutive control instructions located between adjacent logical intersection points in the initial control sequence, and each control instruction fragment contains several consecutive control instructions. The waveform statement fragment refers to the subset of statements obtained by splitting the initial waveform sequence based on logical intersection points. It consists of consecutive waveform statements located between adjacent logical intersection points in the initial waveform sequence, and each waveform statement fragment contains several consecutive waveform statements.

[0037] S204. Arrange the control instruction fragments and waveform statement fragments according to the global execution logic, and input them sequentially into the timing simulation environment.

[0038] The global execution logic specifies the order in which control instructions and waveform statements should be executed during the target chip testing process. This order is determined by the objective dependencies between chip initialization and functional testing.

[0039] Optionally, control instruction segments and waveform statement segments are alternately arranged according to global execution logic to form a simulation input sequence, which is then input into a timing simulation environment. The timing simulation environment refers to an electronic design automation (EDA) simulation platform used to run the initial control sequence and initial waveform sequence and record signal waveform timing information. Optionally, the timing simulation environment is provided by an EDA platform.

[0040] S205. Obtain the start and end times of the control instruction segment and the start and end times of the waveform statement segment through the timing simulation environment.

[0041] During the execution of the simulation input sequence in the timing simulation environment, the start and end times of each control instruction segment, as well as the start and end times of each waveform statement segment, can be obtained by monitoring and recording the simulation waveforms.

[0042] For control instruction segments, the start time is the simulation time point when the first control instruction in the segment begins execution, and the end time is the simulation time point when the last control instruction in the segment completes execution. For waveform statement segments, the start time is the simulation time point when the first waveform statement in the segment begins execution, and the end time is the simulation time point when the last waveform statement in the segment completes execution.

[0043] S206. For each logical handover point in the initial control sequence and the initial waveform sequence, the handover delay is determined based on the global execution logic, the start and end times of the control instruction segment, and the start and end times of the waveform statement segment.

[0044] The initial control sequence and the initial waveform sequence are two independent sequences, each marked with a logical handover point. For each logical handover point in the initial control sequence and each logical handover point in the initial waveform sequence, the corresponding handover delay is determined.

[0045] The logic handover points in the initial control sequence are traversed. According to the global execution logic, there is a control instruction segment before and after the current logic handover point. In the initial waveform sequence, there exists a waveform statement segment corresponding to the current logic handover point. The start and end times of the control instruction segments have been obtained through the timing simulation environment, and the start time of the waveform statement segments has also been obtained.

[0046] Based on this, the actual execution time of the control instruction segment itself can be determined, as well as the waiting time before the waveform statement segment begins execution after the control instruction segment has finished executing. Furthermore, the handover delay corresponding to any logical handover point in the initial control sequence can be determined. Following this logic, the handover delay corresponding to any logical handover point in the initial waveform sequence can also be determined.

[0047] S207. Based on the logical handover point, the handover delay is written into the initial control sequence and the initial waveform sequence respectively to obtain the delay control sequence and the delay waveform sequence.

[0048] S208. The target chip is tested using the time delay control sequence and the time delay waveform sequence.

[0049] This disclosed technical solution decomposes the initial control sequence and initial waveform sequence based on logical junction points, breaking down the complex sequence into control instruction fragments and waveform statement fragments. These fragments are then sequentially input into a timing simulation environment after being arranged according to global execution logic, allowing for precise recording of the execution timing of each fragment on the chip design model. By obtaining the start and end times of each control instruction fragment and waveform statement fragment using the timing simulation environment, the actual execution time and waiting time between fragments due to differences in physical paths within the target chip can be accurately reflected. Based on this, by associating each logical junction point with the corresponding fragment start and end times according to the global execution logic, the junction delay can be directly calculated. The automatically extracted delay values ​​obtained through simulation closely correspond to the chip's physical implementation, providing a precise basis for subsequent timing compensation and laying a reliable foundation for the timing alignment of control instructions and waveform statements at logical junction points.

[0050] In an optional embodiment, for each logical handover point in the initial control sequence, the handover delay is determined based on the global execution logic, the start and end times of the control instruction segment, and the start and end times of the waveform statement segment. This includes: for each logical handover point in the initial control sequence, determining the first instruction segment and the second instruction segment associated with it in the control instruction segment sequentially based on the global execution logic, and determining the handover statement segment associated with it in the waveform statement segment; determining the handover delay corresponding to the handover statement segment based on the start and end times of the first instruction segment and the start time of the handover statement segment; and determining the handover delay corresponding to the second instruction segment based on the start and end times of the handover statement segment and the start time of the second instruction segment.

[0051] The logical handover points in the initial control sequence are traversed. First, the control instruction segment that precedes and is adjacent to the current logical handover point in the execution order is identified within the control instruction segments; this segment is denoted as the first instruction segment. The control instruction segment that follows and is adjacent to the current logical handover point in the execution order is identified; this segment is denoted as the second instruction segment. Simultaneously, based on the global execution logic, the waveform statement segment corresponding to the current logical handover point is identified within the waveform statement segments; this segment is denoted as the handover statement segment. The relationship between the first instruction segment, the second instruction segment, and the handover statement segment is uniquely determined by the global execution logic. Their execution order is as follows: the first instruction segment is executed first, followed by the handover statement segment, and then the second instruction segment.

[0052] Given that the start and end times of the first instruction segment, the second instruction segment, and the handover statement segment have been obtained through a timing simulation environment, the handover delay corresponding to the handover statement segment includes the actual execution time of the first instruction segment itself, as well as the waiting time from the completion of the first instruction segment's execution to the start of the handover statement segment's execution. Optionally, the actual execution time of the first instruction segment itself is determined based on its start and end times. The waiting time from the completion of the first instruction segment's execution to the start of the handover statement segment's execution is determined based on the end time of the first instruction segment and the start time of the handover statement segment. The sum of the actual execution time of the first instruction segment itself and the waiting time from the completion of the first instruction segment's execution to the start of the handover statement segment's execution is determined as the handover delay corresponding to the handover statement segment.

[0053] Similarly, the handover delay corresponding to the second instruction fragment includes both the actual execution time of the handover statement fragment itself and the waiting time from the completion of the handover statement fragment to the start of the second instruction fragment. Optionally, the actual execution time of the handover statement fragment itself is determined based on its start and end times. The waiting time from the completion of the handover statement fragment to the start of the second instruction fragment is determined based on the end time of the handover statement fragment and the start time of the second instruction fragment. The sum of the actual execution time of the handover statement fragment itself and the waiting time from the completion of the handover statement fragment to the start of the second instruction fragment is determined as the handover delay corresponding to the second instruction fragment.

[0054] The above technical solution determines the handover delay corresponding to the handover statement segment and the second instruction segment by determining the start and end times of the first instruction segment, the start and end times of the handover statement segment, and the start time of the second instruction segment. This ensures that the determined handover delay fully reflects the execution time of the control instruction segment, the execution time of the waveform statement segment, and the waiting time between segments. This accurately compensates for the transmission delay difference between the initial control sequence and the initial waveform sequence within the target chip due to different physical paths, providing an accurate basis for timing alignment at the logic handover point.

[0055] In an optional embodiment, based on the logical handover point, the handover delay is written into the initial control sequence to obtain a delay control sequence, including: generating a waiting instruction based on the handover delay corresponding to the second instruction segment; and concatenating the waiting instruction between the first instruction segment and the second instruction segment to obtain the delay control sequence.

[0056] This process iterates through the logical handover points in the initial control sequence. The second instruction fragment refers to the control instruction fragment located after and adjacent to the current logical handover point. The first instruction fragment refers to the control instruction fragment located before and adjacent to the current logical handover point. The handover delay includes the actual execution time of the handover statement fragment associated with the current logical handover point and the waiting time from the completion of the handover statement fragment to the start of the second instruction fragment.

[0057] A wait instruction is a control instruction that indicates the target chip should pause and wait for a specified duration during test execution; the wait duration is equal to the handover delay. A delay control sequence refers to the complete set of control instructions formed after the wait instruction has been written between the first and second instruction segments.

[0058] Based on the determined handover delay corresponding to the second instruction fragment, a wait instruction is generated, with its wait duration set to the value of the handover delay. Since the global execution logic specifies the execution order of the first instruction fragment, the handover statement fragment, and the second instruction fragment as follows: first, the first instruction fragment is executed; then, the handover statement fragment is executed; and finally, the second instruction fragment is executed. Therefore, when concatenating the control instruction fragments in the initial control sequence, the wait instruction is inserted between the first and second instruction fragments. This ensures that during test execution, the wait instruction is precisely in the stable process following the completion of the handover statement fragment and before the start of the second instruction fragment's execution. Concatenating the control instruction fragments after inserting the wait instruction sequentially yields the delay control sequence.

[0059] The delay control sequence contains a waiting instruction of equal length to the handover delay. When the delay control sequence is used to test the target chip, after the target chip completes the first instruction segment, it will automatically execute the waiting instruction and pause the corresponding handover delay. This pause period covers the execution and stabilization process of the handover statement segment, thus ensuring that the start time of the second instruction segment is precisely aligned with the completion time of the waveform statement segment and the chip's ready state.

[0060] The above technical solution generates a waiting instruction based on the handover delay corresponding to the second instruction segment, and splices the waiting instruction between the first instruction segment and the second instruction segment to obtain a delay control sequence. This makes the handover delay embedded within the initial control sequence, thereby automatically compensating for the transmission delay difference between the control instruction and the waveform statement due to different physical paths during test execution, ensuring that the start time of the second instruction segment is precisely aligned with the completion time of the waveform statement segment.

[0061] In an optional embodiment, for each logical handover point in the initial waveform sequence, the handover delay is determined based on the start and end times of the global execution logic, the control instruction segment, and the waveform statement segment. This includes: for each logical handover point in the initial waveform sequence, determining the first and second statement segments associated with it in the waveform statement segments according to the global execution order, and determining the handover instruction segment associated with it in the control instruction segment; determining the handover delay corresponding to the handover instruction segment based on the start and end times of the first statement segment; and determining the handover delay corresponding to the second statement segment based on the start and end times of the handover instruction segment.

[0062] The logical handover points in the initial waveform sequence are traversed. The first statement fragment is the waveform statement fragment that precedes and is adjacent to the current logical handover point in execution order. The second statement fragment is the waveform statement fragment that follows and is adjacent to the current logical handover point in execution order. The handover instruction fragment is the control instruction fragment corresponding to the current logical handover point, determined from the control instruction fragments based on the global execution logic. The relationship between the first statement fragment, the second statement fragment, and the handover instruction fragment is uniquely determined by the global execution logic, and their execution order is: first, the first statement fragment is executed; then, the handover instruction fragment is executed; and finally, the second statement fragment is executed.

[0063] The method for determining the corresponding handover delay for each logic handover point in the initial waveform sequence is the same as that for each logic handover point in the initial control sequence, and will not be repeated here.

[0064] In an optional embodiment, based on the logical handover point, the handover delay is written into the initial waveform sequence to obtain a delay waveform sequence, including: generating a waiting instruction based on the handover delay corresponding to the second statement segment; and splicing the waiting instruction between the first statement segment and the second statement segment to obtain a delay waveform sequence.

[0065] The implementation of "writing the handover delay into the initial waveform sequence based on the logical handover point to obtain the time delay waveform sequence" is the same as "writing the handover delay into the initial control sequence based on the logical handover point to obtain the time delay control sequence", and will not be repeated here.

[0066] In an optional embodiment, the method further includes: inputting the time-delay control sequence and the time-delay waveform sequence in parallel into a timing simulation environment to obtain simulation results output by the timing simulation environment; if the simulation results fail to match the expected response, then the logical junction point that causes the matching failure is taken as an abnormal junction point; adjusting the junction delay of the abnormal junction points in the time-delay control sequence and the time-delay waveform sequence to obtain a new control sequence and a new waveform sequence; inputting the new control sequence and the new waveform sequence in parallel into the timing simulation environment to obtain a new simulation result, until the new simulation result matches the expected response.

[0067] The delay control sequence and delay waveform sequence, already written into the handover delay, are input in parallel into the timing simulation environment. The timing simulation environment simulates the actual execution timing of the ATE (Automatic Test Equipment) machine, simultaneously driving the joint test action group interface and functional pin channels, outputting simulation results, and comparing these results with the preset expected response. The simulation result refers to the actual response data collected from the target chip's output pins after the timing simulation environment executes the delay control sequence and delay waveform sequence. The expected response refers to the standard response data that should be generated under correct timing conditions, as predetermined according to the target chip's design specifications.

[0068] If the simulation results match the expected response, it indicates that the handover delays in the time delay control sequence and the time delay waveform sequence have accurately compensated for the transmission delay differences between the control command and the waveform statement, and the timing alignment is correct. If the simulation result fails to match the expected response, it indicates that at least one logical junction point exists whose junction delay fails to accurately reflect the actual timing offset at that point. This logical junction point is marked as an abnormal junction point. An abnormal junction point is the logical junction point located that caused the matching failure when the simulation result fails to match the expected response. Optionally, the abnormal junction point can be determined by analyzing the timing and pin location of the response deviation in the simulation result.

[0069] For abnormal handover points, the handover delay corresponding to that point in the time-delay control sequence and time-delay waveform sequence is adjusted. The adjustment method can be to increase the waiting time for instructions, generating a new control sequence and a new waveform sequence. The new control sequence refers to the set of control instructions regenerated after adjusting the handover delay corresponding to the abnormal handover point in the time-delay control sequence. The new waveform sequence refers to the set of waveform statements regenerated after adjusting the handover delay corresponding to the abnormal handover point in the time-delay waveform sequence.

[0070] The new control sequence and the new waveform sequence are input into the timing simulation environment in parallel again to obtain new simulation results, which are then compared with the expected response. This adjustment and verification process is repeated until the new simulation results pass the comparison with the expected response.

[0071] The above technical solution performs closed-loop verification by inputting the delay control sequence and delay waveform sequence into a timing simulation environment in parallel. When the simulation result fails to match the expected response, the abnormal handover point is located and the handover delay is iteratively adjusted until the match passes. This ensures that the handover delay at each logic handover point is fully calibrated during the simulation stage, guaranteeing the timing accuracy of the final generated delay control sequence and delay waveform sequence. Consequently, the first-pass yield of the target chip can be guaranteed without manual debugging during ATE (Automatic Test Equipment) testing, effectively avoiding test misjudgments and repeated debugging costs caused by handover delay deviations.

[0072] Figure 3 This is a schematic diagram of a chip testing apparatus according to an embodiment of this disclosure. This embodiment is applicable to chip testing scenarios in the pre-silicon verification stage and ATE mass production testing stage of integrated circuits, where a test environment needs to be established through control instructions and functional stimuli executed through waveform statements. Examples include initialization and wake-up of SoC (System on Chip) chips, high-speed interface link training, firmware download, and multi-power domain reset and release, where precise timing alignment of control instructions and waveform statements is required at logical intersection points. This apparatus can be implemented using software and / or hardware, and can implement the chip testing methods described in any embodiment of this disclosure.

[0073] like Figure 3 As shown, the chip testing device 300 includes: The sequence acquisition module 301 is used to acquire the initial control sequence and initial waveform sequence required for the target chip test; wherein, the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence are transmitted along different physical paths inside the target chip, and the transmission delays are different. The delay determination module 302 is used to determine the logical handover point between the control command and the waveform statement in the initial control sequence and the initial waveform sequence, respectively, and to determine the handover delay corresponding to the logical handover point through simulation; The delay writing module 303 is used to write the handover delay into the initial control sequence and the initial waveform sequence respectively based on the logical handover point to obtain the delay control sequence and the delay waveform sequence; The chip testing module 304 is used to test the target chip using the time delay control sequence and the time delay waveform sequence.

[0074] This disclosed technical solution determines the handover delay at the logical junction point between the initial control sequence and the initial waveform sequence during the simulation phase, and writes this handover delay into the sequence to generate a time-delayed control sequence and a time-delayed waveform sequence. This allows the control instructions in the time-delayed control sequence and the waveform statements in the time-delayed waveform sequence to automatically wait for the corresponding duration when they reach the logical junction point. This compensates for the transmission delay difference caused by the two types of instructions being transmitted along different physical paths within the target chip, achieving timing alignment between the control instructions and the waveform statements. Therefore, when testing the target chip using the time-delayed control sequence and the time-delayed waveform sequence, manual timing debugging on the ATE machine is unnecessary, avoiding initialization failures or test misjudgments caused by timing deviations. This shortens the single-chip testing time and improves the first-pass yield and mass production testing efficiency of the target chip on the ATE machine.

[0075] Optionally, the delay determination module 302 includes: a sequence splitting submodule, used to split the initial control sequence and the initial waveform sequence respectively based on the logical junction point to obtain control instruction fragments and waveform statement fragments; and a fragment arrangement submodule, used to arrange the control instruction fragments and the waveform statement fragments according to the global execution logic and input them sequentially into the timing simulation environment. The start time acquisition submodule is used to acquire the start and end times of the control instruction segment and the start and end times of the waveform statement segment through the timing simulation environment; the delay determination submodule is used to determine the handover delay for each logical handover point in the initial control sequence and the initial waveform sequence, based on the global execution logic, the start and end times of the control instruction segment, and the start and end times of the waveform statement segment.

[0076] Optionally, the delay determination submodule includes: an associated segment determination unit, configured to, for each logical handover point in the initial control sequence, sequentially determine the first instruction segment and the second instruction segment associated with it in the control instruction segment based on global execution logic, and determine the handover statement segment associated with it in the waveform statement segment; a first delay determination unit, configured to determine the handover delay corresponding to the handover statement segment based on the start time and end time of the first instruction segment and the start time of the handover statement segment; and a second delay determination unit, configured to determine the handover delay corresponding to the second instruction segment based on the start time and end time of the handover statement segment and the start time of the second instruction segment.

[0077] Optionally, the delay writing module 303 includes: a wait instruction generation submodule, used to generate a wait instruction based on the handover delay corresponding to the second instruction fragment; and a wait instruction splicing submodule, used to splice the wait instruction between the first instruction fragment and the second instruction fragment to obtain the delay control sequence.

[0078] Optionally, the device further includes: a simulation result acquisition module, used to input the time delay control sequence and the time delay waveform sequence in parallel into a timing simulation environment to obtain the simulation result output by the timing simulation environment; an anomaly identification module, used to identify the logical junction point that caused the comparison failure as an abnormal junction point if the simulation result fails to match the expected response; a time delay adjustment module, used to adjust the junction delay of the abnormal junction points in the time delay control sequence and the time delay waveform sequence to obtain a new control sequence and a new waveform sequence; and a sequence input module, used to input the new control sequence and the new waveform sequence in parallel into the timing simulation environment to obtain a new simulation result until the new simulation result matches the expected response.

[0079] Optionally, the delay determination module 302 includes: a sequence element traversal submodule, used to traverse the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence as sequence elements according to the global execution logic; a position determination submodule, used to determine the sequence to which the current sequence element and the previous sequence element belong and their positions in the sequence if the current sequence element and the previous sequence element come from different sequences; a first intersection point determination submodule, used to determine the position between the current sequence element and its subsequent adjacent sequence element in the sequence to which the current sequence element belongs as the logical intersection point in the sequence; and a second intersection point determination submodule, used to determine the position between the previous sequence element and its subsequent adjacent sequence element in the sequence to which the previous sequence element belongs as the logical intersection point in the sequence.

[0080] Optionally, the chip testing module 304 includes: an environment setup submodule, used to input the delay control sequence into the target chip through the joint test action group interface to establish a test environment for the target chip; and a performance testing submodule, used to input the delay waveform sequence into the target chip through a functional pin channel after the test environment is established to perform performance testing on the target chip.

[0081] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision, and disclosure of any type of information, such as user personal information, comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0082] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0083] Figure 4 A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0084] like Figure 4 As shown, device 400 includes a computing unit 401, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 402 or a computer program loaded from storage unit 408 into random access memory (RAM) 403. RAM 403 may also store various programs and data required for the operation of device 400. The computing unit 401, ROM 402, and RAM 403 are interconnected via bus 404. Input / output (I / O) interface 405 is also connected to bus 404.

[0085] Multiple components in device 400 are connected to I / O interface 405, including: input unit 406, such as keyboard, mouse, etc.; output unit 407, such as various types of monitors, speakers, etc.; storage unit 408, such as disk, optical disk, etc.; and communication unit 409, such as network card, modem, wireless transceiver, etc. Communication unit 409 allows device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0086] The computing unit 401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above, such as chip testing methods. For example, in some embodiments, the chip testing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 408. In some embodiments, part or all of the computer program may be loaded and / or installed on device 400 via ROM 402 and / or communication unit 409. When the computer program is loaded into RAM 403 and executed by the computing unit 401, one or more steps of the chip testing method described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to perform chip testing methods by any other suitable means (e.g., by means of firmware).

[0087] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0088] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0089] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0090] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0091] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0092] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is established by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service ecosystem that addresses the management difficulties and weak business scalability inherent in traditional physical hosting and VPS services. Servers can also be servers for distributed systems or servers integrated with blockchain technology.

[0093] Artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies mainly include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0094] Cloud computing refers to a technology system that enables access to a shared pool of physical or virtual resources via a network. These resources can include servers, operating systems, networks, software, applications, and storage devices, and can be deployed and managed on demand and in a self-service manner. Cloud computing technology can provide efficient and powerful data processing capabilities for applications such as artificial intelligence and blockchain, as well as for model training.

[0095] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution provided in this disclosure can be achieved, and this is not limited herein.

[0096] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A chip testing method, the method comprising: Obtain the initial control sequence and initial waveform sequence required for testing the target chip; wherein, the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence are transmitted along different physical paths inside the target chip, and the transmission delays are different; The logical handover points between the control command and the waveform statement are determined in the initial control sequence and the initial waveform sequence, respectively, and the handover delay corresponding to the logical handover points is determined by simulation. Based on the logical handover point, the handover delay is written into the initial control sequence and the initial waveform sequence respectively to obtain the delay control sequence and the delay waveform sequence; The target chip is tested using the time delay control sequence and the time delay waveform sequence.

2. The method according to claim 1, wherein, The step of determining the handover delay corresponding to the logical handover point through simulation includes: Based on the logical junction point, the initial control sequence and the initial waveform sequence are split into control instruction fragments and waveform statement fragments respectively. The control instruction fragments and waveform statement fragments are arranged according to the global execution logic and then sequentially input into the timing simulation environment. The start and end times of the control instruction segment, as well as the start and end times of the waveform statement segment, are obtained through the timing simulation environment. For each logical handover point in the initial control sequence and the initial waveform sequence, the handover delay is determined based on the global execution logic, the start and end times of the control instruction segment, and the start and end times of the waveform statement segment.

3. The method according to claim 2, wherein, For each logical handover point in the initial control sequence, the handover delay is determined based on the global execution logic, the start and end times of the control instruction segment, and the start and end times of the waveform statement segment, including: For each logical handover point in the initial control sequence, based on the global execution logic, the first instruction segment and the second instruction segment associated with it are determined sequentially in the control instruction segment, and the handover statement segment associated with it is determined in the waveform statement segment. Based on the start and end times of the first instruction fragment and the start time of the handover statement fragment, the handover delay corresponding to the handover statement fragment is determined; Based on the start and end times of the handover statement fragment and the start time of the second instruction fragment, the handover delay corresponding to the second instruction fragment is determined.

4. The method according to claim 3, wherein, Based on the logical handover point, the handover delay is written into the initial control sequence to obtain a delay control sequence, including: Based on the handover delay corresponding to the second instruction fragment, a waiting instruction is generated; The waiting instruction is concatenated between the first instruction fragment and the second instruction fragment to obtain the delay control sequence.

5. The method according to claim 1 or 2, further comprising: The time delay control sequence and the time delay waveform sequence are input in parallel into the timing simulation environment to obtain the simulation results output by the timing simulation environment; If the simulation results fail to match the expected response, the logical junction that caused the failure will be designated as an abnormal junction. Adjust the handover delay of abnormal handover points in the time delay control sequence and the time delay waveform sequence to obtain a new control sequence and a new waveform sequence. The new control sequence and the new waveform sequence are input in parallel into the timing simulation environment to obtain new simulation results until the new simulation results are compared with the expected response.

6. The method according to claim 1, wherein, Determining the logical handover point between the control command and the waveform statement in the initial control sequence and the initial waveform sequence respectively includes: According to the global execution logic, the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence are traversed as sequence elements. If the current sequence element and the previous sequence element come from different sequences, determine the sequences to which the current sequence element and the previous sequence element belong and their positions in the sequences, respectively. In the sequence to which the current sequence element belongs, the position between the current sequence element and its adjacent sequence element is determined as the logical intersection point in the sequence; In the sequence to which the previous sequence element belongs, the position between the previous sequence element and its adjacent sequence element is determined as the logical intersection point in the sequence.

7. The method according to claim 1, wherein, The step of testing the target chip using the time delay control sequence and the time delay waveform sequence includes: The delay control sequence is input into the target chip through the joint test action group interface to establish a test environment for the target chip; After the test environment is established, the delay waveform sequence is input to the target chip through the functional pin channel to perform performance testing on the target chip.

8. A chip testing apparatus, the apparatus comprising: The sequence acquisition module is used to acquire the initial control sequence and initial waveform sequence required for target chip testing; wherein, the control instructions in the initial control sequence and the waveform statements in the initial waveform sequence are transmitted along different physical paths inside the target chip, and the transmission delays are different; The delay determination module is used to determine the logical handover point between the control command and the waveform statement in the initial control sequence and the initial waveform sequence, respectively, and to determine the handover delay corresponding to the logical handover point through simulation; The delay writing module is used to write the handover delay into the initial control sequence and the initial waveform sequence respectively based on the logical handover point, so as to obtain the delay control sequence and the delay waveform sequence; The chip testing module is used to test the target chip using the time delay control sequence and the time delay waveform sequence.

9. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the chip testing method according to any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to execute the chip testing method according to any one of claims 1-7.

11. A computer program product comprising a computer program that, when executed by a processor, implements the chip testing method according to any one of claims 1-7.

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