A small current grounding device real-time simulation test system based on FPGA

Abstract

This invention discloses a real-time simulation and testing system for low-current grounding devices based on FPGA. It simulates the primary side of a distribution network using a discretized form of the Bergeron model and runs the model in real time on the FPGA. The FPGA interacts with the device under test (DUT) through physical interfaces of analog output modules, power amplifiers, and digital I / O modules, enabling full closed-loop testing of the DUT's line selection algorithm and tripping logic. This system allows for arbitrary changes to test parameters and fault conditions, can be modified online without recompilation, and facilitates the exploration of boundary conditions. It is a hardware-in-the-loop testing solution for R&D desktops, combining real-time performance with flexibility.

Description

Technical Field

[0001] This invention relates to a real-time simulation test system for a low-current grounding device based on FPGA, belonging to the field of low-voltage device testing technology. Background Technology

[0002] In recent years, low-current grounding systems (including ungrounded neutral, arc-suppression coil grounded, or high-resistance grounded systems) have become dominant in medium- and low-voltage distribution networks. In these systems, single-phase grounding faults are the most common type of fault. Due to the weak fault current and the symmetrical three-phase line voltages, the system can operate with the fault for 1-2 hours. However, prolonged operation can lead to an increase in the voltage of the non-faulty phases, potentially causing insulation breakdown, phase-to-phase short circuits, or even equipment burnout. Therefore, how to quickly and accurately select the faulty line has always been a technical challenge in the field of power system relay protection.

[0003] Currently, low-current grounding fault location technology has evolved from passive detection to active analysis of steady-state and transient criteria and active detection of signal injection, moving towards higher precision, higher reliability, intelligence, and self-adaptability. However, the testing of low-current grounding fault location devices still relies on real grounding fault data captured by transient fault recorders in actual power grids. This open-loop test based on playback technology can more realistically verify the robustness of the device under real-world operating conditions, but the limited data volume and the inability to reflect the mutual influence of system transient processes after the device trips in real time make it unable to meet the testing requirements during the development process. While large-scale real-time simulators such as RTDS / ADPSS offer high precision and powerful functionality, they often require appointments and dedicated personnel, making them unsuitable for R&D personnel to debug anytime, anywhere. Furthermore, model modification, environment setup, and testing procedures are relatively cumbersome, hindering rapid iteration. There is an urgent need for a testing method for low-current grounding fault location devices that is desktop-oriented and combines real-time performance with flexibility. Summary of the Invention

[0004] This invention provides a real-time simulation test system for a low-current grounding device based on FPGA, which solves the problems disclosed in the background art.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A real-time simulation test system for a low-current grounding device based on FPGA includes: a host computer, an FPGA, an analog output module, a power amplifier, a digital I / O module, and the device under test;

[0007] The host computer is equipped with an electromagnetic transient model for simulating the primary side of the power distribution network. The electromagnetic transient model includes: busbars, lines, arc suppression coils, fault modules, and circuit breakers.

[0008] The fault module is used to set the fault line, fault phase, grounding resistance, fault initial phase angle, fault duration, and grounding resistance to a fixed value or time-varying value.

[0009] The FPGA is connected to the host computer via Ethernet. The electromagnetic transient model is converted into HDL code running on the FPGA for real-time simulation. Test parameters are input through the host computer, and the FPGA calculates the corresponding voltage / current digital quantities based on the test parameters. The voltage / current digital quantities are then input to the analog output module.

[0010] The analog output module converts digital voltage / current quantities into analog signals, which are then amplified by a power amplifier to the rated secondary value of the device under test and input to the device under test.

[0011] The circuit breaker is used to interact with the device under test;

[0012] The digital I / O module is used to receive the trip contact signal from the device under test. The trip contact signal is transmitted to the host computer via the FPGA to control the circuit breaker.

[0013] The electromagnetic transient model modifies the admittance matrix of the circuit breaker at the corresponding position to the open circuit state, and at the same time updates the circuit breaker position signal and outputs it to the input interface of the device under test via FPGA and digital I / O module.

[0014] Furthermore, the host computer is equipped with a top-level system state machine and a fault injection and tripping response state machine;

[0015] The top-level system state machine is used to manage the overall operation mode of the simulation system, including idle, fault testing, tripping, and FPGA and device under test reset.

[0016] The fault injection and trip response state machine is used to control the occurrence, persistence, and clearing of faults, receive trip node signals from the device under test, and implement multi-round trip logic.

[0017] Furthermore, the electromagnetic transient model uses nodal voltage equations to describe the bus; the Bergeron model is used to describe the line and frequency effects are compensated through segmented frequency compensation; and a dynamic model including inductance L, damping resistor R, and thyristor tuned branch is used to describe the arc suppression coil.

[0018] Furthermore, the Bergeron model equates a distributed parameter line to two Norton current sources in series with the surge impedance; for a single lossless line, we have:

[0019] ;

[0020] ;

[0021] in, Let be the current flowing into the line from terminal k at time t. For wave impedance, Let be the voltage at terminal k to ground at time t. For the propagation time of the traveling wave, Let be the current flowing into the line from end m at time t. Let m be the voltage at time t to ground, and let historical current be the term. and Calculated from historical values ​​of the voltage and current at the opposite end.

[0022] Furthermore, methods for using the Bergeron model to describe the line and compensating for frequency effects through segmented frequency compensation include:

[0023] Frequency is estimated by counting the number of times the current sign changes;

[0024] set up:

[0025] Low frequency: ≤8 times, corresponding to a frequency ≤ 800 Hz;

[0026] Mid-frequency: 9~30 times, corresponding to frequencies of 900 Hz ~ 3 kHz;

[0027] High frequency: >30 times, corresponding to a frequency >3 kHz.

[0028] Furthermore, methods for describing arc suppression coils using a dynamic model that includes inductance L, damping resistor R, and thyristor tuning branches include:

[0029] The Mayr and Cassie models are set up to simulate intermittent electric arcs. The Mayr model assumes that the arc diameter is constant and the temperature changes, which is suitable for describing the breaking process of low-current, high-impedance arcs. The Cassie model assumes that the arc temperature is constant and the diameter changes, which describes the inverse relationship between arc voltage and arc resistance when the current crosses zero, and is suitable for high-current, low-impedance arcs.

[0030] The Mayr model is described as follows: ;

[0031] The Cassie model is described as follows: ;

[0032] in, For the time derivative, The derivative of conductance, This represents the rate of change of electrical conductance with respect to time. For arc conductivity, and It is a time constant. U is the heat dissipation power constant, and u is the arc voltage. The arc voltage constant is...i This is the arc current.

[0033] Furthermore, the FPGA discretizes a complete cycle of arc resistance change over time, i.e., the process of arc ignition, extinguishing, and reigniting starting from the zero-crossing point, into a time-resistance value sequence and stores it in ROM; based on the offset of the current time relative to the most recent current zero-crossing point, the resistance value is obtained by looking up a table; each time a current zero-crossing point is detected, the FPGA internally resets the cycle counter and reads the resistance value starting from the starting address of the lookup table.

[0034] Furthermore, the FPGA employs fixed-step discrete-time simulation to convert the continuous model into discrete difference equations; the solver uses the back-Euler method, and the inductor components in the circuit satisfy the following:

[0035] ;

[0036] Using the backward Euler method, get:

[0037] ;

[0038] Because the inductor is connected in series with the resistor, there is , = Substituting, we get:

[0039] ;

[0040] Because the capacitor satisfies Then, using the backward Euler method, we have:

[0041] ;

[0042] = Right now: ;

[0043] in, For the nth time moment The variable value, Let be the variable value at time n+1. For the next moment, Step size, =h, For varying time periods, Let L be the voltage across the inductor and L be the inductance. For the time derivative, For the differential of the current, For the current at the next moment, The current at the current moment, The branch voltage at the next moment. To input the node voltage for the next time step. This represents the capacitor voltage at the next moment. For resistance voltage drop, For segmented inductors, For segmented resistors, For capacitor current, For capacitance, The derivative of the capacitor voltage, The capacitor voltage at the current moment. This represents the capacitor current at the next moment.

[0044] The beneficial effects achieved by this invention are as follows:

[0045] This invention miniaturizes and desktopizes the core concepts of large-scale real-time simulation (RTDS) simulators through an FPGA-based real-time simulation and testing system, providing researchers with a platform for conducting fully closed-loop, highly dynamic, and real-time testing at any time. Seamlessly connected to the device under test via digital I / O modules, it can recreate transient processes, calculate high-frequency components after a fault in real time, verify device transient criteria, verify multiple tripping logics, flexibly set grounding resistances of up to several thousand ohms to cover high-resistance grounding boundaries, and verify steady-state criteria such as the zero-sequence active power method. It simplifies test wiring and significantly improves the depth and efficiency of R&D testing for low-current grounding fault location devices. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the system structure of the real-time simulation test system for a small current grounding device based on FPGA in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the model building algorithm flow of the real-time simulation test system for a small current grounding device based on FPGA in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the preparation process for the real-time simulation test system of the FPGA-based low-current grounding device in this embodiment of the invention.

[0049] Figure 4 This is a schematic diagram of the different fault condition scanning test process of the real-time simulation test system for a small current grounding device based on FPGA in an embodiment of the present invention.

[0050] Figure 5 This is a schematic diagram of the multi-trip logic test process of the real-time simulation test system for a small current grounding device based on FPGA in an embodiment of the present invention. Detailed Implementation

[0051] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0052] Example 1

[0053] like Figure 1 As shown, this embodiment provides a system for real-time simulation testing of a small current grounding device based on FPGA, including: a host computer, an FPGA, an analog output module, a power amplifier, a digital I / O module, and the device under test;

[0054] An electromagnetic transient model for simulating the primary side of a power distribution network is built using MATLAB / Simulink on the host computer, including:

[0055] Busbar: Described using nodal voltage equations;

[0056] Circuit: To accurately simulate transient high-frequency components, a discretized form of the electromagnetic transient circuit model is adopted, with a step size of 50μs;

[0057] Arc suppression coil: A dynamic model including inductance L, damping resistor R, and thyristor tuning branch; to avoid assuming grounding faults as fixed resistance, Mayr and Cassie models are used to simulate intermittent arcs. The Mayr model assumes a constant arc diameter and temperature variation, suitable for describing the breaking process of low-current, high-impedance arcs. The Cassie model assumes a constant arc temperature and diameter variation, describing the inverse relationship between arc voltage and arc resistance when the current crosses zero, suitable for high-current, low-impedance arcs. The Mayr model is described as follows: ;

[0058] The Cassie model is described as follows: ;

[0059] in, For the time derivative, The derivative of conductance, This represents the rate of change of electrical conductance with respect to time. For arc conductivity, and It is a time constant. U is the heat dissipation power constant, and u is the arc voltage. Let V be the arc voltage constant (V). i For the arc current, the encapsulated arc model is connected in series to the fault branch of the main circuit.

[0060] Fault module: Programmable control of faulty line, faulty phase, grounding resistance, initial phase angle of the fault, and fault duration. Grounding resistance can be set to a fixed value or time-varying value;

[0061] Circuit breaker: Controlled by the device trip signal, the admittance matrix is ​​modified to the open circuit state at the corresponding position in the model, and the circuit breaker position signal output is updated at the same time;

[0062] The host computer connects to the FPGA via Ethernet. The FPGA connects to the analog output module. The FPGA initializes its internal state variables according to parameters and can perform real-time simulation calculations. The FPGA calculates the bus zero-sequence voltage 3U0 and three-phase voltages, the zero-sequence current 3I0 and three-phase currents of each line, and outputs the voltage / current digital quantities to the analog output module. The parameters refer to the bus rated voltage, frequency, line length, unit length parameters, neutral grounding method, arc suppression coil parameters, and load parameters set for this test. The host computer uses Simulink HDL Coder to convert the electromagnetic transient model into HDL code that can run on the FPGA. Furthermore, leveraging the parallelism of the FPGA, the calculations of each line and component are parallelized to ensure that the entire network solution is completed within a single step. D / A output drivers, digital input acquisition, and digital output drivers are written. The system communicates with the host computer via a communication interface, receiving parameters (such as fault resistance and fault time) and transmitting internal state variables back for monitoring. When converting the data into HDL code that can run on the FPGA, to avoid the resource-intensive problem of division and exponential operations required for directly solving differential equations in the FPGA, a complete cycle of arc resistance change over time—from the zero-crossing point, through arc ignition, extinction, and reignition—is discretized into a time-resistance value sequence and stored in ROM. The FPGA looks up the resistance value in a table based on the offset of the current time relative to the most recent current zero-crossing point. Each time a current zero-crossing point is detected, the FPGA internally resets the cycle counter and reads the resistance value from the starting address of the lookup table.

[0063] The analog output module is connected to the power amplifier. The signal is boosted by the power amplifier. The analog output module uses a high-speed D / A converter with more than 16 bits to convert the digital voltage / current calculated by the FPGA into an analog signal of ±10V.

[0064] The output of the power amplifier is connected to the voltage and current input interface of the device under test, and the output of the digital I / O module is connected to the input and output interfaces of the device under test.

[0065] The power amplifier uses a small linear power amplifier to amplify the weak signal output by the analog output module to the device's rated secondary value of 100V and 5A.

[0066] The digital I / O module includes optocoupler-isolated digital inputs and relay outputs. The digital I / O module is used to receive trip contact signals from the device under test. The trip contact signals are transmitted to the host computer via the FPGA to control the circuit breaker. The host computer modifies the admittance matrix to the open circuit state at the corresponding position in the electromagnetic transient model, and at the same time updates the circuit breaker position signal, which is output to the input interface of the device under test via the FPGA and the digital I / O module.

[0067] The host computer is connected to the device under test via Ethernet, which facilitates the monitoring of the real-time operating data of the device under test.

[0068] To ensure that events such as fault triggering, tripping commands, circuit breaker opening and closing, and fault clearing occur in a strict sequence, the host computer adopts a hierarchical finite state machine (FSM) design and uses the Stateflow module to graphically build the FSM model, constructing the top-level system state machine, fault injection state machine, and tripping response state machine, among which:

[0069] 1. Top-level system state machine: manages the overall operation mode of the simulation system, such as idle, fault testing, trip handling, and reset;

[0070] 2. The fault injection and trip response state machine controls the occurrence, persistence, and clearing of faults, receives trip signals from the device, and implements multi-round trip logic.

[0071] When building an FSM model graphically, the Counter Limited module is used to implement fixed-delay fault counting.

[0072] The host computer runs a graphical interface for setting system parameters such as line length, arc suppression coil compensation degree, and load; defining fault sequences such as trigger time, fault type, resistance, and duration; displaying key waveforms in real time; automatically running test scripts; recording device action time and line selection results; and generating test reports by comparing with expectations.

[0073] The host computer can call the FPGA communication library to automatically traverse different combinations of grounding resistance, initial phase angle, and faulty lines to form a test matrix.

[0074] The host computer has a test case library that defines various fault sequences. Each test case has different initialization parameters, fault trigger time, fault type, resistance, and duration. The FPGA initializes its internal state variables according to the initialization parameters and starts real-time simulation calculation.

[0075] In normal operation, the FPGA continuously outputs waveforms while monitoring whether the digital input port receives a trip signal from the device. At this time, there should be no trip signal, and the signal should remain low. At the moment of failure, the host computer 10 issues a fault trigger command according to a preset time. For example, if the command is set to "at t=1.0s, phase A of line L2 is grounded through a 100Ω resistor", then at t=1.0s, the FPGA modifies the internal node admittance matrix and grounds phase A of L2 through a 100Ω resistor. In the subsequent calculation steps, the bus zero-sequence voltage and the zero-sequence current of each line immediately show transient and steady-state changes. These real-time waveforms are output to the device under test through the analog output module and the power amplifier.

[0076] The device under test (DUT) detects that 3U0 exceeds the start-up setpoint and initiates the line selection algorithm. After internal algorithm selection, the faulty line is identified. Assuming L2 has the highest probability, the DUT sends an output signal to trip L2. The digital I / O module detects the contact closure and sends a rising edge to the FPGA to trigger an interrupt. The FPGA immediately modifies the admittance matrix in the next simulation step, disconnecting the line from the bus and disconnecting the L2 circuit breaker in the model. Simultaneously, it sends a closing signal to the corresponding circuit breaker position output contact to the digital I / O module, which then sends a signal to the DUT's input interface simulating that the circuit breaker has tripped.

[0077] If the device under test correctly identifies the low-current grounding line, that is, outputs multiple fault lines that may be grounded, sorts them according to the grounding probability, and outputs a trip signal, then line 3U0 drops below the threshold, the device under test no longer sends out subsequent trip signals, the FPGA records the waveform and action timing of the entire process, and the test ends.

[0078] If the device under test fails to correctly identify the low-current grounding line, i.e., L2 is not a faulty line, then 3U0 will continue to exist, the FPGA will continue to remain in the fault state, or if the line cannot be selected, it indicates that the line selection has failed. The host computer records the waveform of the entire process and the judgment result of the device under test, and the test result.

[0079] The FPGA has an internal buffer that can record key electrical quantities such as 3U0, each of 3I0, and circuit breaker status for a period of time before and after the fault. After the test, the data is sent to the host computer 10 for analysis of the correctness of the device's line selection algorithm, compared with the device report, and the test conclusion is drawn.

[0080] The real-time simulation test system for low-current grounding devices based on FPGA of the present invention downloads the primary side model of the distribution network into the FPGA for real-time operation and interacts directly with the device under test through a physical interface to realize full closed-loop testing of the line selection algorithm and tripping logic of the device under test, effectively improving the efficiency and reliability of R&D testing.

[0081] like Figure 2 As shown, the electromagnetic transient model used to simulate the primary side of the distribution network is built in Simulink. A fixed-step solver needs to be set, with the step size fixed at 50μs, consistent with the FPGA real-time simulation step size. A voltage source with internal resistance is used to represent the system power supply to build the bus module, ensuring that the three-phase voltage amplitude and frequency are settable. An improved Bergeron model with segmented frequency compensation is used to build the line module, dividing each line into several π-type circuits. Each segment includes a series resistor R, an inductor L, and a parallel capacitor C. The resistor R in each segment is designed as a variable resistor, which is controlled by the frequency detection module. The inductor L and capacitor C are fixed values ​​set based on the power frequency parameters.

[0082] A fault module is built to simulate a single-phase ground fault using an ideal switch and a grounding resistor; the switch is controlled by an external control signal from a host computer. The fault point can be located on the busbar or at any segment node of any line. A circuit breaker module is built to simulate a controlled circuit breaker using an ideal switch; the circuit breaker status (closed / open) is simultaneously output as a circuit breaker position signal to the digital I / O module. Depending on the testing requirements, an arc suppression coil model is added to build a neutral point module, which can be directly grounded or ungrounded.

[0083] To reduce the hardware requirements for real-time simulation, the electromagnetic transient circuit model uses the Bergeron model (constant parameter traveling wave model). The Bergeron model equates the distributed parameter circuit to two Norton current sources in series with the wave impedance. For a single lossless line, we have:

[0084] ;

[0085] ;

[0086] in, Let be the current flowing into the line from terminal k at time t. For wave impedance, Let be the voltage at terminal k to ground at time t. For the propagation time of the traveling wave, Let be the current flowing into the line from end m at time t. Let m be the voltage at time t to ground, and let historical current be the term. and Calculated from historical values ​​of the voltage and current at the opposite end. To account for losses, a lumped resistor is typically connected in series across the two ends. ;

[0087] To compensate for the shortcomings of the Bergeron model, which uses a constant resistor and has a small high-frequency resistance, resulting in insufficient attenuation of high-frequency components, a segmented frequency compensation method is used to compensate for the frequency effect. That is, the R value at 1kHz, 2kHz and 5kHz is obtained through offline simulation, the equivalent resistance at different frequencies is pre-calculated in the FPGA, and the series resistance in the model is dynamically adjusted according to the dominant frequency of the current transient.

[0088] To overcome the dependence of common frequency detection methods on amplitude, the sign rate of change method, also known as the zero-crossing count method, is used to estimate the frequency by counting the number of current sign changes, thus reducing dependence on amplitude and the impact of noise. The following explanation is provided for this method: Common frequency detection methods, such as the threshold comparison method based on the current rate of change, rely on... The absolute value of the amplitude is compared with two preset thresholds, such as 1kHz and 2kHz, to divide the transient frequency into three intervals: low frequency, mid frequency, and high frequency. The corresponding series resistance value is selected according to the interval to achieve frequency compensation of the line parameters. However, this method has two inherent drawbacks: The sign change rate is proportional to the current amplitude. When grounding with high resistance, the fault current is very small, and even if the actual frequency is high, it may be below the low-frequency threshold, causing the model to incorrectly use the low-frequency resistor. The principle of using the sign change rate method is that for a periodic current signal, the sign changes twice per cycle (positive → negative and negative → positive). Therefore, the number of sign changes per unit time is proportional to the frequency. A sign comparator is set up in the algorithm. In each step, the current is compared with 0, and the sign bit is output. The sign bit of the current step is XORed with the sign bit of the previous step, indicating that the sign has changed (crossed zero). A fixed-length time window counter is set. Each sign change within the window increments the counter by 1. When the window count reaches the preset length, the counter value is read. The frequency range is determined based on two predefined thresholds. In the algorithm, we set:

[0089] Low frequency: ≤8 times (corresponding frequency ≤ 800 Hz);

[0090] Intermediate frequency: 9~30 times (corresponding to frequencies of 900 Hz ~ 3 kHz);

[0091] High frequency: >30 times (corresponding frequency >3 kHz);

[0092] Preferably, a hysteresis comparator is added after the comparator to prevent frequent switching.

[0093] Based on the frequency band index, use Simulink's Multiport Switch module to select one of three preset resistance values ​​(R_low, R_mid, R_high). The low-frequency resistor R_low uses power frequency parameters; the mid-frequency and high-frequency resistors can be obtained by performing frequency sweep fitting on a similar circuit using Simulink's ATP-EMTP module, or by using empirical formulas. Estimate.

[0094] Preferably, to reduce numerical oscillations caused by sudden changes in resistance, a first-order low-pass filter can be connected in series after the switch to make the resistance transition smoothly.

[0095] FPGA simulation using fixed-step discrete-time methods requires converting continuous systems into difference equations. To avoid iteration and ensure real-time performance, the solver employs the back-Euler method, and the inductors in the circuit satisfy the following conditions:

[0096] ;

[0097] Using the backward Euler method, i.e. We can then conclude that:

[0098] ;

[0099] Because the inductor is connected in series with the resistor, there is , = Substituting, we get:

[0100] ;

[0101] Because the capacitor satisfies Then, using the backward Euler method, we have:

[0102] ;

[0103] There are also = Right now:

[0104] ;

[0105] This facilitates FPGA implementation. The dynamic range of each physical quantity is determined and normalized to the [-1, 1] interval. The data type is set using the Fixdt tool in Simulink, and simulations are performed to verify accuracy and overflow risk.

[0106] Offline simulation of the discretized fixed-point model was performed in Simulink, and the results were compared with those of the continuous model to ensure that the error was acceptable.

[0107] like Figure 3 As shown, the preparation process needs to be completed when the test system is first built, or repeated whenever the system topology or circuit parameters need to be modified. The goal is to generate a real-time simulation model that can run on the FPGA.

[0108] Press Figure 2 After the model is built, the Simulink model needs to be configured to HDL code generation mode, and hdlcoder needs to be run to generate VHDL code and test files and complete the FPGA project integration.

[0109] The FPGA engineering integration includes writing SPI or parallel interface logic based on the D / A chip datasheet and adding a D / A driver module. A digital input processing module is added for debouncing and level conversion. A digital output driver module is added to control relays. An Ethernet communication interface module is added to exchange data with the host computer. The top-level file is written, all modules are connected, and synthesis, placement and routing are performed to generate a bitstream file.

[0110] The development of the host computer communication protocol needs to be completed, including defining simple command and data frame formats and setting the data to be uploaded. The defined simple command and data frame formats are used to set fault parameters, start / stop simulation, and read internal variables. The uploaded data refers to the FPGA transmitting selected electrical quantities back to the host computer in real time for monitoring and recording.

[0111] A circular buffer is designed in the internal data cache of the FPGA to cyclically store waveform data for a specified duration before and after the fault, which is convenient for sending the data to the host computer for analysis after testing.

[0112] like Figure 3 As shown, before each new test sequence, hardware connections and test environment preparation are required to ensure the system status is correct, the FPGA is correctly connected to the analog output module, the analog output module is correctly connected to the power amplifier, the FPGA is correctly connected to the digital I / O module, the power amplifier output is correctly connected to the analog input interface of the device under test, and the digital I / O module is correctly connected to the input and output interfaces of the device under test.

[0113] Specifically, the trip output contact of the device under test must be optically isolated from the digital I / O module. An oscilloscope should be used to measure at the device end to confirm there are no open circuits or short circuits, and that the signal amplitude range meets the device requirements.

[0114] Load the newly generated FPGA configuration file onto the FPGA via JTAG, start the host computer test software, establish a connection with the FPGA via Ethernet or serial port, and confirm that the communication is normal.

[0115] Before the test begins, system parameters and fault lines, resistances, and initial phase angles need to be set according to the power grid structure of the test to facilitate a quick start to the test.

[0116] Example 2

[0117] like Figure 4 As shown, according to one embodiment of the present invention, a low-current grounding fault location device can be subjected to scanning tests under different fault conditions. The method includes the following steps:

[0118] Step S102: Connect the various modules in the test system in sequence to prepare for the execution of the test task;

[0119] Step S104: Start FPGA simulation, output steady-state power frequency voltage, and check that the device has no startup alarms and the 3U0 display is close to 0. Confirm that the device communicates normally with the FPGA, and the host computer can monitor the current waveform of each line in real time.

[0120] Step S106, verify the basic line selection criteria: Set the fault parameters via the host computer: Fault line: L2, Fault type: A-phase grounding, Grounding resistance: 20Ω (metallic), Fault initial phase angle: 90°, Fault duration: 1s; The host computer sends a "Start Fault" command, and the FPGA closes the fault switch at the zero-crossing point of the next power frequency cycle (or at a specified time). The FPGA calculates and outputs the fault waveform in real time. The device under test should start line selection. The host computer records the internal electrical quantities of the FPGA (3U0, each of 3I0, fault flag), and records the action message of the device under test: it should display the fault line L2 and output a trip signal. If the device under test correctly selects L2 and the trip output is activated, the FPGA detects the trip signal and immediately disconnects the circuit breaker of L2 in the model, updating the circuit breaker position status. If the fault is cleared, 3U0 should drop below the threshold, and the device under test should no longer operate. The host computer performs result judgment: Line selection correctness 100%, and the action time conforms to the device technical specifications.

[0121] Step S108: Perform different fault condition scanning tests: The host computer runs an automatic test script, traverses the following parameter combinations, and automatically resets the device under test and FPGA model after each test.

[0122] Faulty lines: L1, L2, L3, L4 (including busbar faults);

[0123] Grounding resistance: 0Ω, 100Ω, 500Ω, 1000Ω, 5000Ω (high resistance);

[0124] Initial phase angles: 0°, 30°, 60°, 90°;

[0125] Neutral point configuration: ungrounded, via arc suppression coil;

[0126] In step S110, the host computer automatically reads the device report through the communication interface of the device under test and compares it with the fault lines preset by the FPGA to generate a statistical table.

[0127] According to this embodiment of the invention, it can be verified whether the device correctly selects the line based on the zero-sequence active power method when the transient component is small under high-resistance grounding. Under the action of the arc suppression coil, it can be verified whether the transient zero-sequence current amplitude-phase comparison method remains effective. During a bus fault, the device should not trip or incorrectly select the line.

[0128] Example 3

[0129] like Figure 5 As shown, according to one embodiment of the present invention, multiple tripping logic tests can be performed, including the following steps:

[0130] Step S112: Connect the various modules in the test system in sequence to prepare for the execution of the test task;

[0131] Step S114: Start FPGA simulation and output steady-state power frequency voltage;

[0132] Step S116: The host computer automatically sets the fault according to the test case: L1 is grounded via 50Ω;

[0133] Step S118, the FPGA performs special processing according to the test case: when the device sends the L1 trip signal, the FPGA captures the signal, but does not immediately disconnect the L1 circuit breaker, simulating the circuit breaker refusing to operate or the line selection error causing the fault to persist. At this time, the FPGA continues to maintain the fault state.

[0134] In step S120, the device under test should detect that 3U0 has not disappeared after the first trip and, after a 600ms delay, issue a trip L3 signal. The FPGA captures the second trip signal, at which point the L3 circuit breaker is disconnected, but the fault point remains in L1. Since the fault point is still in L1, 3U0 still exists, and the device under test should continue to detect and trip sequentially according to the preset alternative order, with each trip interval of 600ms. The FPGA correctly responds to each trip and updates the circuit breaker status. The host computer counts the number of trips, which matches the set value of "number of selected trip branches". If the first choice is successful, the alternatives do not operate.

[0135] Furthermore, the present invention can also verify the protection functions of the low current grounding line selection device, such as anti-interference blocking function and accelerated tripping function, by configuring test cases. Moreover, the invention can set random fault sequences including different lines and different resistances through automatic test program, so that the device under test 60 can run continuously for long-term stability testing.

[0136] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0137] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of the claims of the present invention pending approval.

Claims

1. A real-time simulation and testing system for a low-current grounding device based on FPGA, characterized in that, include: Host computer, FPGA, analog output module, power amplifier, digital I / O module, and device under test; The host computer is equipped with an electromagnetic transient model for simulating the primary side of the power distribution network. The electromagnetic transient model includes: busbars, lines, arc suppression coils, fault modules, and circuit breakers. The fault module is used to set the fault line, fault phase, grounding resistance, fault initial phase angle, fault duration, and grounding resistance to a fixed value or time-varying value. The electromagnetic transient model uses the Bergeron model to describe the circuit and compensates for the frequency effect through a segmented frequency compensation method. The frequency is estimated by counting the number of current sign changes, and the series resistance in the model is dynamically adjusted according to the dominant frequency of the current transient. The FPGA is connected to the host computer via Ethernet. The electromagnetic transient model is converted into HDL code running on the FPGA for real-time simulation. Test parameters are input through the host computer, and the FPGA calculates the corresponding voltage / current digital quantities based on the test parameters. The voltage / current digital quantities are then input to the analog output module. The analog output module converts digital voltage / current quantities into analog signals, which are then amplified by a power amplifier to the rated secondary value of the device under test and input to the device under test. The circuit breaker is used to interact with the device under test; The digital I / O module is used to receive the trip contact signal from the device under test. The trip contact signal is transmitted to the host computer via the FPGA to control the circuit breaker. The electromagnetic transient model modifies the admittance matrix of the circuit breaker at the corresponding position to the open circuit state, and at the same time updates the circuit breaker position signal and outputs it to the input interface of the device under test via FPGA and digital I / O module.

2. The real-time simulation test system for a low-current grounding device based on FPGA according to claim 1, characterized in that, The host computer is equipped with a top-level system state machine and a fault injection and trip response state machine. The top-level system state machine is used to manage the overall operation mode of the simulation system, including idle, fault testing, tripping, and FPGA and device under test reset. The fault injection and trip response state machine is used to control the occurrence, persistence, and clearing of faults, receive trip node signals from the device under test, and implement multi-round trip logic.

3. The real-time simulation test system for a low-current grounding device based on FPGA according to claim 1, characterized in that, The electromagnetic transient model uses nodal voltage equations to describe the bus; and a dynamic model including inductance L, damping resistor R, and thyristor-tuned branches to describe the arc suppression coil.

4. The real-time simulation test system for a low-current grounding device based on FPGA according to claim 3, characterized in that, The Bergeron model equates a distributed parameter line to two Norton current sources in series with the surge impedance; for a single lossless line, we have: ； ； in, Let be the current flowing into the line from terminal k at time t. For wave impedance, Let be the voltage at terminal k to ground at time t. For the propagation time of the traveling wave, Let be the current flowing into the line from end m at time t. Let m be the voltage at time t to ground, and let historical current be the term. and Calculated from historical values ​​of the voltage and current at the opposite end.

5. The real-time simulation test system for a low-current grounding device based on FPGA according to claim 3, characterized in that, Methods for using the Bergeron model to describe the line and compensating for frequency effects through segmented frequency compensation include: set up: Low frequency: ≤8 times, corresponding to a frequency ≤ 800 Hz; Mid-frequency: 9~30 times, corresponding to frequencies of 900 Hz ~ 3 kHz; High frequency: >30 times, corresponding to a frequency >3 kHz.

6. The real-time simulation test system for a low-current grounding device based on FPGA according to claim 3, characterized in that, Methods for describing arc suppression coils using a dynamic model that includes inductance L, damping resistor R, and thyristor tuning branch include: The Mayr and Cassie models are set up to simulate intermittent electric arcs. The Mayr model assumes that the arc diameter is constant and the temperature changes, which is suitable for describing the breaking process of low-current, high-impedance arcs. The Cassie model assumes that the arc temperature is constant and the diameter changes, which describes the inverse relationship between arc voltage and arc resistance when the current crosses zero, and is suitable for high-current, low-impedance arcs. The Mayr model is described as follows: ; The Cassie model is described as follows: ; in, For the time derivative, The derivative of conductance, The electric arc conductance is represented by the rate of change of conductivity with respect to time, where g is the electric arc conductance. and It is a time constant. U is the heat dissipation power constant, and u is the arc voltage. Let be the arc voltage constant, and i be the arc current.

7. The real-time simulation test system for a low-current grounding device based on FPGA according to claim 6, characterized in that, The FPGA discretizes a complete cycle of arc resistance change over time—that is, the process of arc ignition, extinguishing, and reigniting starting from the zero-crossing point—into a time-resistance value sequence and stores it in ROM. Based on the offset of the current time relative to the most recent current zero-crossing point, the resistance value is obtained by looking up a table. Each time a current zero-crossing point is detected, the FPGA internally resets the cycle counter and reads the resistance value starting from the beginning address of the lookup table.

8. The real-time simulation test system for a low-current grounding device based on FPGA according to claim 1, characterized in that, The FPGA employs fixed-step discrete-time simulation, converting the continuous model into discrete difference equations; the solver uses the back-Euler method, and the inductor components in the circuit satisfy the following: ； Using the backward Euler method, get: ； Because the inductor is connected in series with the resistor, there is , = Substituting, we get: ； Because the capacitor satisfies Then, using the backward Euler method, we have: ； = ； Right now: ; in, For the nth time moment The variable value, Let be the variable value at time n+1. For the next moment, Step size, =h, For varying time periods, Let L be the voltage across the inductor and L be the inductance. For the time derivative, For the differential of the current, For the current at the next moment, The current at the current moment, The branch voltage at the next moment. To input the node voltage for the next time step. This represents the capacitor voltage at the next moment. For resistance voltage drop, For segmented inductors, For segmented resistors, For capacitor current, For capacitance, The derivative of the capacitor voltage, The capacitor voltage at the current moment. This represents the capacitor current at the next moment.

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