Array substrate, display panel and display device
By introducing a discharge capacitor and an ion attachment layer on the array substrate, the problem of the formation of a built-in electric field by charged impurity particles in the liquid crystal display panel is solved, resulting in better display effect and simplified process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HKC CORP LTD
- Filing Date
- 2026-05-15
- Publication Date
- 2026-07-21
AI Technical Summary
Charged impurity particles in a liquid crystal display panel are adsorbed under the action of a driving electric field, forming a built-in electric field, which causes image retention and affects the display effect.
By introducing discharge capacitors and ion attachment layers on the array substrate, the built-in electric field formed by charged impurity particles is reduced or eliminated by charging and discharging before each row of sub-pixels is displayed.
It effectively reduces or eliminates the built-in electric field, improves the display effect of the display panel, avoids image retention, increases the pixel aperture ratio, and simplifies the manufacturing process.
Smart Images
Figure CN122194514B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, specifically relating to an array substrate, a display panel, and a display device. Background Technology
[0002] Liquid crystal display (LCD) panels are widely used in various consumer electronics products such as mobile phones, televisions, and laptops due to their advantages such as high image quality, energy saving, thin body, and mature and stable manufacturing process, making them the mainstream display panel.
[0003] The liquid crystal display panel includes an array substrate, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. A driving electric field is formed between the pixel electrode on one side of the array substrate and the common electrode on the opposing substrate. The liquid crystal material in the liquid crystal layer is deflected under the action of the driving electric field, controlling the amount of backlight passing through. Combined with the color filter layer on the array substrate or the opposing substrate, color display is achieved.
[0004] It is difficult to achieve absolute purity in a liquid crystal layer. Charged impurity particles inevitably mix into the liquid crystal material. Under the influence of the driving electric field, these particles adhere to the array substrate and the opposing substrate, forming a built-in electric field. This built-in electric field formed by the charged impurity particles cannot be quickly cleared during the display process, resulting in image retention on the display panel and affecting its display performance. Summary of the Invention
[0005] The purpose of this application is to provide an array substrate, a display panel, and a display device to improve the display effect of the display panel.
[0006] To achieve the above objectives, this application provides an array substrate, including a substrate, the array substrate further comprising:
[0007] A driving circuit layer is formed on one side of the substrate. An insulating protective layer is formed on the side of the drive circuit layer away from the substrate. A pixel electrode, wherein a plurality of the pixel electrodes are formed on the side of the insulating protective layer away from the substrate, and the pixel electrodes pass through the insulating protective layer and are connected to the driving circuit layer; An alignment layer is formed at least on the side of the pixel electrode away from the substrate. A discharge capacitor is formed on the side of the alignment layer away from the substrate. The discharge capacitor includes a first electrode and a second electrode spaced apart. At least the orthogonal projection of the central region of the pixel electrode onto the discharge capacitor is located between the first electrode and the second electrode. The driving circuit layer is capable of charging and discharging the discharge capacitor.
[0008] Optionally, the array substrate further includes an ion-attachment layer formed on the side of the alignment layer away from the substrate. The ion-attachment layer includes a groove that exposes at least the central region of the pixel electrode. Both the first electrode and the second electrode are disposed in the ion-attachment layer. The ion-attachment layer includes an insulating material and an ion adsorbent uniformly mixed in the insulating material. The ion adsorbent includes cellulose-based ions.
[0009] Optionally, the driving circuit layer includes multiple rows of scan lines, multiple columns of data lines, multiple driving transistors, and multiple discharge transistors. The orthogonal projection of the pixel electrode on the driving circuit layer is located within the area enclosed by the scan lines and the data lines. The first electrode and the second electrode are spaced apart along the row direction. The driving transistor includes a first gate, a first source, and a first drain. The first gate is connected to the scan line of the row it belongs to, the first source is connected to the data line of the column it belongs to, and the first drain is connected to the pixel electrode. The discharge transistor includes a second gate, a second source, and a second drain. The second gate of the Nth row is connected to the scan line of the (N-1)th row, the second source is connected to the first electrode, the second drain is connected to the scan line of the (N-1)th row, and the second electrode is connected to a high-level signal line.
[0010] Optionally, the discharge capacitor is configured to correspond one-to-one with each pixel electrode; or In the row direction, a discharge capacitor is provided for every two pixel electrodes. The space occupied by one pixel electrode is separated between adjacent discharge capacitors, and the electric field direction formed by adjacent discharge capacitors is the same.
[0011] Optionally, the driving transistor is configured in a one-to-one correspondence with the pixel electrode, and a discharge transistor is configured for each row of pixel electrodes. The first electrode in the same row is connected to the second source of the same discharge transistor.
[0012] Optionally, the array substrate includes a display area and a pseudo-pixel area, the pseudo-pixel area being disposed at least on one side of the display area in the row direction, the driving transistor being disposed in the display area, and the discharge transistor being disposed in the pseudo-pixel area.
[0013] Optionally, the driving circuit layer includes a first metal layer, a gate insulating layer, a semiconductor layer, and a second metal layer. The first metal layer is formed on one side of the substrate and includes the scan line, the first gate, and the second gate. The gate insulating layer is formed on the side of the first metal layer away from the substrate. The semiconductor layer is formed on the side of the gate insulating layer away from the substrate and includes a first channel portion and a second channel portion. The first channel portion is located on the side of the first gate away from the substrate, and the second channel portion is located on the side of the second gate away from the substrate. The second metal layer includes the data line, a first source, a first drain, a second source, and a second drain. The first source and the first drain are spaced apart on the side of the first channel portion away from the substrate, and the second source and the second drain are spaced apart on the side of the second channel portion away from the substrate.
[0014] This application also provides a display panel, including: The array substrate; A counter substrate is disposed on one side of the array substrate; A liquid crystal layer is disposed between the array substrate and the opposing substrate.
[0015] Optionally, the array substrate further includes an ion-attachment layer formed on the side of the alignment layer away from the substrate. The ion-attachment layer includes a groove that exposes at least the central region of the pixel electrode. The first electrode and the second electrode are both disposed in the ion-attachment layer. The ion-attachment layer includes an insulating material and an ion adsorbent uniformly mixed in the insulating material. The ion adsorbent includes cellulose-based ions. At least a portion of the ion-attachment layer is in contact with the opposing substrate.
[0016] This application also provides a display device, including: Backlight module; The display panel is located on the light-emitting side of the backlight module.
[0017] The array substrate, display panel, and display device disclosed in this application have the following beneficial effects: In this application, the array substrate includes a substrate, a driving circuit layer, an insulating protective layer, pixel electrodes, an alignment layer, and a discharge capacitor. The driving circuit layer is formed on one side of the substrate, the insulating protective layer is formed on the side of the driving circuit layer away from the substrate, multiple pixel electrodes are formed on the side of the insulating protective layer away from the substrate, the alignment layer is formed at least on the side of the pixel electrodes away from the substrate, and the discharge capacitor is formed on the side of the alignment layer away from the substrate. The discharge capacitor includes a first electrode and a second electrode spaced apart. The driving circuit layer is capable of charging and discharging the discharge capacitor. Before each row of sub-pixels displays the image, the discharge capacitor is first charged and then discharged, which can reduce or eliminate the built-in electric field formed by charged impurity particles and improve the display effect of the display panel.
[0018] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.
[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0021] Figure 1 This is a cross-sectional schematic diagram of the array substrate in Embodiment 1 of this application.
[0022] Figure 2 This is a schematic diagram of the structure of a pixel unit in Embodiment 1 of this application.
[0023] Figure 3 yes Figure 2 Schematic diagram of section AA.
[0024] Figure 4 This is a schematic diagram of the circuit structure of the driving circuit layer in Embodiment 1 of this application.
[0025] Figure 5 This is a circuit diagram showing the setting of discharge capacitors on some pixel electrodes in Embodiment 1 of this application.
[0026] Figure 6 This is a structural diagram of a partial pixel electrode with a discharge capacitor in Embodiment 1 of this application.
[0027] Figure 7 This is a schematic diagram of a discharge transistor arranged in each row in Embodiment 1 of this application.
[0028] Figure 8 This is a schematic diagram of multiple rows of discharge capacitors controlled by a single discharge transistor in Embodiment 1 of this application.
[0029] Figure 9 This is a schematic diagram of the display panel structure in Embodiment 2 of this application.
[0030] Figure 10 This is a schematic diagram of the display device in Embodiment 2 of this application.
[0031] Explanation of reference numerals in the attached figures: 100, Substrate; 200, Driving circuit layer; 201, Driving transistor; 202, Discharge transistor; 210, First metal layer; 211, Scan line; 212, First gate; 213, Second gate; 220, Gate insulating layer; 230, Semiconductor layer; 231, First channel; 232, Second channel; 240, Second metal layer; 241, Data line; 242, First source; 243, First drain; 244, Second source; 245, Second drain; 250, High-level signal line; 300, Insulating protective layer; 310, Passivation layer; 320, First planarization layer; 330, Second planarization layer; 410, Pixel electrode; 420, Alignment layer; 510, Discharge capacitor; 511, First electrode; 512, Second electrode; 520, Ion adhesion layer; 600, Common line; 10. Array substrate; 20. Opposite substrate; 21. Black matrix; 30. Liquid crystal layer; 1. Display panel; 2. Backlight module. Detailed Implementation
[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.
[0033] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.
[0034] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.
[0035] Example 1 See Figures 1 to 3 As shown, in this embodiment, the array substrate 10 includes a substrate 100, a driving circuit layer 200, an insulating protective layer 300, a pixel electrode 410, an alignment layer 420, and a discharge capacitor 510. The substrate 100 may include a transparent substrate such as a glass substrate or a polyimide substrate. The driving circuit layer 200 is formed on one side of the substrate 100, and the insulating protective layer 300 is formed on the side of the driving circuit layer 200 away from the substrate 100.
[0036] Multiple pixel electrodes 410 are formed on the side of the insulating protective layer 300 away from the substrate 100. The multiple pixel electrodes 410 are arranged in an array along the row and column directions, and each pixel electrode 410 forms a sub-pixel. The pixel electrodes 410 pass through the insulating protective layer 300 and are connected to the driving circuit layer 200. The pixel electrodes 410 are made of a transparent conductive material such as indium tin oxide (ITO). An alignment layer 420 is formed at least on the side of the pixel electrodes 410 away from the substrate 100.
[0037] A discharge capacitor 510 is formed on the side of the alignment layer 420 away from the substrate 100. The discharge capacitor 510 can be made of a metallic material or a transparent conductive material such as indium tin oxide to improve the pixel aperture ratio. The discharge capacitor 510 includes a first electrode 511 and a second electrode 512 spaced apart, with at least the orthogonal projection of the central region of the pixel electrode 410 onto the discharge capacitor 510 located between the first electrode 511 and the second electrode 512. That is, the first electrode 511 and the second electrode 512 are disposed on both sides of the central region of the pixel electrode 410 in the row or column direction. The first electrode 511 and the second electrode 512 can partially overlap with the pixel electrode 410, and the first electrode 511 and the second electrode 512 can also be disposed on both sides of the entire pixel electrode 410 in the row or column direction. The driving circuit layer 200 is capable of charging and discharging the discharge capacitor 510.
[0038] Before each row of sub-pixels displays the image, the driving circuit layer 200 first controls the discharge capacitor 510 of the sub-pixel in that row to charge and form a horizontal electric field. The horizontal electric field can drive charged impurity particles to move towards the first electrode 511 and the second electrode 512. Positively charged impurity particles move in the direction of the electric field, and negatively charged impurity particles move against the direction of the electric field. Then, the driving circuit layer 200 controls the discharge capacitor 510 to discharge, neutralizing the charge of the charged impurity particles and reducing or eliminating the built-in electric field formed by the charged impurity particles. Finally, the gate driving circuit of that row controls the scanning line of that row to turn on, so that the sub-pixel in that row can display the image.
[0039] It is difficult to achieve absolute purity in a liquid crystal layer. Charged impurity particles inevitably mix into the liquid crystal material. Under the influence of the driving electric field, these particles adhere to the array substrate and the opposing substrate, forming a built-in electric field. This built-in electric field formed by the charged impurity particles cannot be quickly cleared during the display process, resulting in image retention on the display panel and affecting its display performance.
[0040] In this embodiment, the array substrate 10 includes a substrate 100, a driving circuit layer 200, an insulating protective layer 300, pixel electrodes 410, an alignment layer 420, and a discharge capacitor 510. The driving circuit layer 200 is formed on one side of the substrate 100, the insulating protective layer 300 is formed on the side of the driving circuit layer 200 away from the substrate 100, multiple pixel electrodes 410 are formed on the side of the insulating protective layer 300 away from the substrate 100, the alignment layer 420 is formed at least on the side of the pixel electrodes 410 away from the substrate 100, and the discharge capacitor 510 is formed on the side of the alignment layer 420 away from the substrate 100. The discharge capacitor 510 includes a first electrode 511 and a second electrode 512 spaced apart. The driving circuit layer 200 can charge and discharge the discharge capacitor 510. Before each row of sub-pixels displays the image, the discharge capacitor 510 is first charged and then discharged, which can reduce or eliminate the built-in electric field formed by charged impurity particles and improve the display effect of the display panel 1.
[0041] In some embodiments, the array substrate 10 further includes an ion-attachment layer 520, which is formed on the side of the alignment layer 420 away from the substrate 100. The ion-attachment layer 520 includes a groove that exposes at least the central region of the pixel electrode 410, and both the first electrode 511 and the second electrode 512 are disposed in the ion-attachment layer 520. The ion-attachment layer 520 includes an insulating material and an ion adsorbent uniformly mixed in the insulating material. The ion adsorbent includes cellulose-based ions, which are used to adsorb charged impurity particles. The insulating material of the ion-attachment layer 520 can be a light-transmitting material or an opaque material, and the ion-attachment layer 520 is correspondingly a light-transmitting or opaque film layer.
[0042] An ion-attachment layer 520 is formed on the side of the alignment layer 420 away from the substrate 100. The ion-attachment layer 520 can adsorb charged impurity particles in the liquid crystal material, and the auxiliary discharge capacitor 510 plays the role of reducing or eliminating the built-in electric field formed by charged impurity particles.
[0043] In some embodiments, see Figures 1 to 4 As shown, the driving circuit layer 200 includes multiple rows of scan lines 211, multiple columns of data lines 241, multiple driving transistors 201, and multiple discharge transistors 202. The orthogonal projection of the pixel electrode 410 onto the driving circuit layer 200 is located within the area enclosed by the scan lines 211 and the data lines 241. The driving transistors 201 can be disposed on one side of the pixel electrode 410 in the column direction. The first electrode 511 and the second electrode 512 are spaced apart along the row direction.
[0044] The driving transistor 201 includes a first gate 212, a first source 242, and a first drain 243. The first gate 212 is connected to the scan line 211 of the row it belongs to, the first source 242 is connected to the data line 241 of the column it belongs to, and the first drain 243 is connected to the pixel electrode 410. The discharging transistor 202 includes a second gate 213, a second source 244, and a second drain 245. The second gate 213 of the Nth row is connected to the scan line 211 of the (N-1)th row, the second source 244 is connected to the first electrode 511, and the second drain 245 is connected to the scan line 211 of the (N-1)th row, where N is an integer greater than 1. The second electrode 512 is connected to the high-level signal line 250. The voltage VGH of the high-level signal line 250 is equal to the high-level voltage at which the scan line 211 turns on the driving transistor 201 and the discharging transistor 202.
[0045] Before the scan signal of row N-1 is a high-level voltage, the discharge transistor 202 of row N is turned off, the voltage of the second electrode 512 is the voltage VGH of the high-level signal line 250, and the discharge capacitor 510 is charged to form a horizontal electric field. When the scan signal of row N-1 is a high-level voltage, the discharge transistor 202 of row N is turned on, the voltage of the second electrode 512 is the voltage VGH of the high-level signal line 250, the voltage of the first electrode 511 is the high-level voltage of the scan line 211, the voltage of the first electrode 511 is equal to the voltage of the second electrode 512, the charge stored in the discharge capacitor 510 is released, and the built-in electric field formed by charged impurity particles is eliminated.
[0046] It should be noted that the second drain 245 is connected to the scan line 211 of the (N-1)th row, and the second electrode 512 is connected to the high-level signal line 250. However, this is not the only connection; the second drain 245 can also be connected to a separately configured amplification signal line, and the second electrode 512 can also be connected to the ground line, depending on the specific situation. Before the scan signal of the (N-1)th row is at a high level, the discharge transistor 202 of the Nth row is turned off, and the voltage of the amplification signal line is greater than or less than the ground line voltage. When the scan signal of the (N-1)th row is at a high level, the discharge transistor 202 of the Nth row is turned on, the voltage of the amplification signal line rises or falls to the ground line voltage, and the charge stored in the discharge capacitor 510 is released.
[0047] The second gate 213 of the Nth row is connected to the scan line 211 of the (N-1)th row, the second source 244 is connected to the first electrode 511, and the second drain 245 is connected to the scan line 211 of the (N-1)th row. This ensures that the built-in electric field is eliminated in advance when the sub-pixel displays the image in each row, and no additional control signal is required, which simplifies the routing of the array substrate 10.
[0048] In some embodiments, the discharge capacitor 510 is provided in a one-to-one correspondence with the pixel electrode 410, and each pixel electrode 410 is provided with a discharge capacitor 510 on the side away from the substrate 100.
[0049] The discharge capacitor 510 is set in a one-to-one correspondence with the pixel electrode 410, so that the charged impurity particles in the liquid crystal material on the side of the pixel electrode 410 away from the substrate 100 are removed more thoroughly.
[0050] It should be noted that the discharge capacitor 510 is set in a one-to-one correspondence with the pixel electrode 410, but it is not limited to this. Alternatively, one discharge capacitor 510 can be set for every two pixel electrodes 410 in the row direction, with a space occupied by one pixel electrode 410 between adjacent discharge capacitors 510. The electric field formed by adjacent discharge capacitors 510 has the same direction, such as... Figure 5 and Figure 6 As shown.
[0051] Although no discharge capacitor 510 is provided above the pixel electrode 410, the second electrode 512 of the discharge capacitor 510 on the left side of the pixel electrode 410 and the first electrode 511 of the discharge capacitor 510 on the right side of the pixel electrode 410 can still form a slight electric field. Reducing the number of discharge capacitors 510 can reduce the power consumption of the array substrate 10.
[0052] It should be noted that for the pixel electrode 410 near the edge region of the array substrate 10, the distance from the sealant is small and the concentration of charged impurity particles is relatively larger. Each pixel electrode 410 can be provided with a discharge capacitor 510. For the pixel electrode 410 far from the edge region of the array substrate 10, the concentration of charged impurity particles is relatively smaller. One discharge capacitor 510 can be provided for every two pixel electrodes 410.
[0053] In some embodiments, driving transistors 201 are configured in a one-to-one correspondence with pixel electrodes 410, and each row of pixel electrodes 410 is configured with a corresponding discharge transistor 202. The first electrode 511 of the same row is connected to the second source 244 of the same discharge transistor 202, such as... Figure 7 As shown.
[0054] Each row of pixel electrodes 410 is provided with a corresponding discharge transistor 202, that is, the same row of sub-pixels share a discharge transistor 202. This design can improve the pixel aperture ratio of the display panel 1.
[0055] It should be noted that each row of pixel electrodes 410 can be provided with a corresponding discharge transistor 202, and the same row of sub-pixels can share a discharge transistor 202. However, it is not limited to this. Each pixel electrode 410 can also be provided with a separate discharge transistor 202, depending on the situation.
[0056] In some embodiments, each row of pixel electrodes 410 is provided with a corresponding discharge transistor 202, that is, the same row of sub-pixels shares a single discharge transistor 202. The array substrate 10 includes a display area and a pseudo-pixel area. The pseudo-pixel area is at least disposed on one side of the display area in the row direction. The driving transistor 201 and the pixel electrode 410 are disposed in the display area, and the discharge transistor 202 is disposed in the pseudo-pixel area.
[0057] The discharge transistor 202 is located in the pseudo-pixel area and does not occupy the design space of the driving transistor 201 in the display area. This can improve the pixel aperture ratio of the display panel 1. The discharge transistor 202 can utilize the original pseudo-pixels. Since the pseudo-pixels do not need to be actually displayed, the connection method of the pseudo-pixels can be changed to convert them into discharge transistors 202, thereby simplifying the manufacturing process.
[0058] In some embodiments, the driving circuit layer 200 includes a first metal layer 210, a gate insulating layer 220, a semiconductor layer 230, and a second metal layer 240. The first metal layer 210 is formed on one side of the substrate 100 and includes a scan line 211, a first gate 212, and a second gate 213. The gate insulating layer 220 is formed on the side of the first metal layer 210 away from the substrate 100.
[0059] A semiconductor layer 230 is formed on the side of the gate insulating layer 220 away from the substrate 100. The semiconductor layer 230 includes a first channel portion 231 and a second channel portion 232. The first channel portion 231 is located on the side of the first gate 212 away from the substrate 100, and the second channel portion 232 is located on the side of the second gate 213 away from the substrate 100.
[0060] The second metal layer 240 includes a data line 241, a first source 242, a first drain 243, a second source 244, and a second drain 245. The first source 242 and the first drain 243 are disposed at intervals on the side of the first channel portion 231 away from the substrate 100, and the second source 244 and the second drain 245 are disposed at intervals on the side of the second channel portion 232 away from the substrate 100.
[0061] By having the driving transistor 201 and the discharge transistor 202 arranged on the same layer, the number of film layers in the array substrate 10 can be reduced, thereby lowering the manufacturing cost of the array substrate 10.
[0062] It should be noted that the driving transistor 201 and the discharge transistor 202 can be arranged on the same layer, but are not limited to this. The driving transistor 201 and the discharge transistor 202 can also be arranged overlappingly, depending on the specific situation.
[0063] In some embodiments, the insulating protective layer 300 includes a passivation layer 310, a first planarization layer 320, and a second planarization layer 330. The passivation layer 310 is formed on the side of the second metal layer 240 away from the substrate 100. The first planarization layer 320 is formed on the side of the passivation layer 310 away from the substrate 100, and the first planarization layer 320 at least covers a portion of the pixel electrode 410 near the substrate 100. The second planarization layer 330 is formed on the side of the passivation layer 310 and the first planarization layer 320 away from the substrate 100. The pixel electrode 410 is connected to the first drain 243 through the passivation layer 310 and the second planarization layer 330.
[0064] The passivation layer 310 can protect the discharge transistor 202, the driving transistor 201, and the exposed metal traces, improving the electrical stability and structural reliability of the device. The first planarization layer 320 and the second planarization layer 330 can protect the discharge transistor 202, the driving transistor 201, and the exposed metal traces, while increasing the planarization bearing surface to improve the thickness uniformity of subsequent film layers such as the pixel electrode 410 and the alignment layer 420.
[0065] In some embodiments, the array substrate 10 further includes a common line 600 disposed between the first planarization layer 320 and the second planarization layer 330. The common line 600 is located on the first planarization layer 320 on the side of the pixel electrode 410 closest to the substrate 100. The common line 600 and the pixel electrode 410 constitute a storage capacitor. The common line 600 may be made of a metallic material and a transparent conductive material.
[0066] It should be noted that the common line 600 can be disposed between the first planarization layer 320 and the second planarization layer 330, but is not limited thereto. The common line 600 can also be disposed in the first metal layer 210. The common line 600 is disposed in the same layer as the scan line 211, the first gate 212 and other structures, depending on the specific situation.
[0067] The common line 600 is located between the first flat layer 320 and the second flat layer 330, that is, the common line 600 is set on a separate layer, and the storage capacity can be designed to be larger.
[0068] In some embodiments, see Figure 8 As shown, the second gate 213 of the Nth row is connected to the scan line 211 of the (N-1)th row, the second gate 213 of the N+1th row is connected to the scan line 211 of the N-1th row, the first electrode 511 of the Nth row is connected to the second source 244 of the Nth row, and the first electrode 511 of the N+1th row is connected to the second source 244 of the Nth row. That is, the discharge capacitor 510 of the Nth row and the discharge capacitor 510 of the N+1th row can be controlled by a single discharge transistor 202, and the discharge transistor 202 controlling the discharge capacitors 510 of the Nth row and the N+1th row is connected to the scan line 211 of the N-1th row.
[0069] The multiple rows of discharge capacitors 510 are controlled by a discharge transistor 202, which can further reduce the number of discharge transistors 202.
[0070] Example 2 This application also provides a display panel 1, see [link] Figure 9 As shown, the display panel 1 includes the array substrate 10, the opposing substrate 20 and the liquid crystal layer 30 disclosed in Embodiment 1. The opposing substrate 20 is disposed on one side of the array substrate 10, and the liquid crystal layer 30 is disposed between the array substrate 10 and the opposing substrate 20.
[0071] In this embodiment, the display panel 1 includes an array substrate 10, which includes a substrate 100, a driving circuit layer 200, an insulating protective layer 300, pixel electrodes 410, an alignment layer 420, and a discharge capacitor 510. The driving circuit layer 200 is formed on one side of the substrate 100, the insulating protective layer 300 is formed on the side of the driving circuit layer 200 away from the substrate 100, multiple pixel electrodes 410 are formed on the side of the insulating protective layer 300 away from the substrate 100, the alignment layer 420 is formed at least on the side of the pixel electrodes 410 away from the substrate 100, and the discharge capacitor 510 is formed on the side of the alignment layer 420 away from the substrate 100. The discharge capacitor 510 includes a first electrode 511 and a second electrode 512 spaced apart. The driving circuit layer 200 can charge and discharge the discharge capacitor 510. Before each row of sub-pixels displays the image, the discharge capacitor 510 is first charged and then discharged to reduce or eliminate the built-in electric field formed by charged impurity particles, thereby improving the display effect of the display panel 1.
[0072] In some embodiments, the array substrate 10 further includes an ion-attachment layer 520, which is formed on the side of the alignment layer 420 away from the substrate 100. The ion-attachment layer 520 includes a groove that exposes at least the central region of the pixel electrode 410, and both the first electrode 511 and the second electrode 512 are disposed in the ion-attachment layer 520. The ion-attachment layer 520 includes an insulating material and an ion adsorbent uniformly mixed in the insulating material. The ion adsorbent includes cellulose-based ions, which are used to adsorb charged impurity particles. The insulating material of the ion-attachment layer 520 can be a light-transmitting material or an opaque material, and the ion-attachment layer 520 is correspondingly a light-transmitting or opaque film layer. At least a portion of the ion-attachment layer 520 is in contact with the opposing substrate 20, that is, the ion-attachment layer 520 can serve as a spacer for the display panel 1.
[0073] The ion-attached layer 520 serves as a spacer for the display panel 1, which simplifies the structure of the display panel 1.
[0074] In some embodiments, the opposing substrate 20 includes a black matrix 21 located on the side of the opposing substrate 20 closest to the liquid crystal layer 30. The black matrix 21 is used to block the discharge transistor 202, the driving transistor 201, and the opaque metal traces on one side of the array substrate 10. The black matrix 21 is also used to block the ion-attached layer 520 and the discharge capacitor 510.
[0075] The ion-attached layer 520 and the discharge capacitor 510 are disposed in the non-transparent area of the display area, which can improve the pixel aperture ratio of the display panel 1.
[0076] Example 3 This application also provides a display device, see [link to relevant documentation] Figure 10As shown, the display device includes a display panel 1 and a backlight module 2 as disclosed in Embodiment 2, with the display panel 1 disposed on the light-emitting side of the backlight module 2.
[0077] In this embodiment, the display device includes a display panel 1, which includes an array substrate 10. Therefore, the display device has all the beneficial effects of the display panel 1 and the array substrate 10, which will not be repeated here.
[0078] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0079] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0080] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0081] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.
Claims
1. An array substrate, comprising a substrate, characterized in that, The array substrate further includes: A driving circuit layer is formed on one side of the substrate. An insulating protective layer is formed on the side of the drive circuit layer away from the substrate. A pixel electrode, wherein a plurality of the pixel electrodes are formed on the side of the insulating protective layer away from the substrate, and the pixel electrodes pass through the insulating protective layer and are connected to the driving circuit layer; An alignment layer is formed at least on the side of the pixel electrode away from the substrate. A discharge capacitor is formed on the side of the alignment layer away from the substrate. The discharge capacitor includes a first electrode and a second electrode that are spaced apart. At least the orthogonal projection of the central region of the pixel electrode onto the discharge capacitor is located between the first electrode and the second electrode. The driving circuit layer is capable of charging and discharging the discharge capacitor. The driving circuit layer includes multiple rows of scan lines, multiple columns of data lines, multiple driving transistors, and multiple discharge transistors. The orthogonal projection of the pixel electrode on the driving circuit layer is located within the area enclosed by the scan lines and the data lines. The first electrode and the second electrode are spaced apart along the row direction. The driving transistor includes a first gate, a first source, and a first drain. The first gate is connected to the scan line of the row it belongs to, the first source is connected to the data line of the column it belongs to, and the first drain is connected to the pixel electrode. The discharge transistor includes a second gate, a second source, and a second drain. The second gate of the Nth row is connected to the scan line of the (N-1)th row, the second source is connected to the first electrode, the second drain is connected to the scan line of the (N-1)th row, and the second electrode is connected to a high-level signal line.
2. The array substrate according to claim 1, characterized in that, The array substrate further includes an ion attachment layer formed on the side of the alignment layer away from the substrate. The ion attachment layer includes a groove that exposes at least the central region of the pixel electrode. The first electrode and the second electrode are both disposed in the ion attachment layer. The ion attachment layer includes an insulating material and an ion adsorbent uniformly mixed in the insulating material. The ion adsorbent includes cellulose-based ions.
3. The array substrate according to claim 2, characterized in that, The discharge capacitor is configured in a one-to-one correspondence with the pixel electrode; or In the row direction, a discharge capacitor is provided for every two pixel electrodes. The space occupied by one pixel electrode is separated between adjacent discharge capacitors, and the electric field direction formed by adjacent discharge capacitors is the same.
4. The array substrate according to claim 3, characterized in that, The driving transistor is configured in a one-to-one correspondence with the pixel electrode, and a discharge transistor is configured for each row of pixel electrodes. The first electrode in the same row is connected to the second source of the same discharge transistor.
5. The array substrate according to claim 2, characterized in that, The array substrate includes a display area and a pseudo-pixel area. The pseudo-pixel area is at least disposed on one side of the display area in the row direction. The driving transistor is disposed in the display area, and the discharge transistor is disposed in the pseudo-pixel area.
6. The array substrate according to claim 2, characterized in that, The driving circuit layer includes a first metal layer, a gate insulating layer, a semiconductor layer, and a second metal layer. The first metal layer is formed on one side of the substrate and includes the scan line, the first gate, and the second gate. The gate insulating layer is formed on the side of the first metal layer away from the substrate. The semiconductor layer is formed on the side of the gate insulating layer away from the substrate and includes a first channel portion and a second channel portion. The first channel portion is located on the side of the first gate away from the substrate, and the second channel portion is located on the side of the second gate away from the substrate. The second metal layer includes the data line, a first source, a first drain, a second source, and a second drain. The first source and the first drain are spaced apart on the side of the first channel portion away from the substrate, and the second source and the second drain are spaced apart on the side of the second channel portion away from the substrate.
7. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 6; A counter substrate is disposed on one side of the array substrate; A liquid crystal layer is disposed between the array substrate and the opposing substrate.
8. The display panel according to claim 7, characterized in that, The array substrate further includes an ion-attachment layer formed on the side of the alignment layer away from the substrate. The ion-attachment layer includes a groove that exposes at least the central region of the pixel electrode. The first electrode and the second electrode are both disposed in the ion-attachment layer. The ion-attachment layer includes an insulating material and an ion adsorbent uniformly mixed in the insulating material. The ion adsorbent includes cellulose-based ions. At least a portion of the ion-attachment layer is in contact with the opposing substrate.
9. A display device, characterized in that, include: Backlight module; The display panel as described in claim 7 or 8 is disposed on the light-emitting side of the backlight module.