Lrdimm memory module, lrdimm memory module self-test method, and access system

Abstract

The application discloses an LRDIMM memory module, an LRDIMM memory module self-checking method and an access system, and relates to storage technology. The LRDIMM memory module comprises a data buffer and a storage unit. The LRDIMM memory module self-checking method comprises the following steps: acquiring an access instruction output by a storage controller; when it is determined according to the access instruction that the access instruction is a write access instruction, controlling the data buffer to store data input by the storage controller and outputting the data input by the storage controller to a storage address corresponding to the storage unit; controlling the data buffer to perform consistency comparison on the stored data and the data output to the storage unit, and feeding back a comparison result; and when it is determined according to the comparison result that the storage address of the storage unit is a fault address, controlling the data buffer to shield a data transmission path between the fault address of the storage unit and the storage controller. The application is beneficial to improving the reliability and stability of a memory system.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to an LRDIMM memory module, an LRDIMM memory module self-testing method, and an access system. Background Technology

[0002] In an LRDIMM (Load-Reduced Dual In-line Memory Module), there is typically a data cache and at least one DRAM (Dynamic Random Access Memory) chip. The DRAM chip comprises billions of memory cells, each with varying data retention capabilities. Furthermore, some memory cells may contain failover cells. Failover cells may fail due to manufacturing process differences, hardware damage, or software errors. The address of a failed memory cell can result in a fixed address error, which can negatively impact the reliability and stability of the memory system.

[0003] To address the issue of memory chip failure, related technologies (CN103019873A) employ ECC algorithms for error correction during data reading and set up a replacement memory to store the correct data corresponding to the faulty cell in the memory. In other words, an additional memory needs to be added to the storage system as a backup memory to back up the faulty cell. Summary of the Invention

[0004] The main objective of this invention is to propose an LRDIMM memory module, an LRDIMM memory module self-testing method, and an access system, aiming to improve the reliability and stability of memory systems.

[0005] To achieve the above objectives, this invention proposes a self-testing method for an LRDIMM memory module. The LRDIMM memory module includes a data buffer and a storage unit. The self-testing method for the LRDIMM memory module includes: Obtain the access command output by the storage controller; When the access instruction is determined to be a write access instruction, the data buffer is controlled to store the data input by the storage controller and output the data input by the storage controller to the storage address corresponding to the storage unit. The data cache is controlled to perform a consistency comparison between the stored data and the data read from the storage unit, and the comparison result is fed back. When the storage address of the storage unit is determined to be a fault address based on the comparison result, the data cache is controlled to block the data transmission path between the fault address of the storage unit and the storage controller.

[0006] In one embodiment, the step of controlling the data cache to perform a consistency comparison between the stored data and the data read from the storage unit, and then feeding back the comparison result, specifically includes: When the amount of data stored in the data cache reaches a preset amount, the data cache is controlled to perform a consistency comparison between the preset amount of data stored and the data read from the storage unit, and the comparison result is fed back.

[0007] In one embodiment, the step of controlling the data cache to perform a consistency comparison between the stored data and the data read from the storage unit, and then feeding back the comparison result, specifically includes: When the data cache stores a preset number of data, it controls the data cache to perform a consistency comparison between the stored preset number of data and the data read from the storage unit, and feeds back the comparison result.

[0008] In one embodiment, the step of controlling the data cache to perform a consistency comparison between the stored data and the data read from the storage unit, and then feeding back the comparison result, specifically includes: Detect the remaining space in the storage area of ​​the data cache; When the remaining space in the data cache is less than a preset threshold, the data cache is controlled to perform a consistency comparison between the preset number of stored data and the data read from the storage unit, and the comparison result is fed back.

[0009] In one embodiment, the LRDIMM memory module self-test method further includes: When the storage address of the storage unit is determined to be a fault address based on the comparison result, the fault address is written to the replaced address in the address mapping table, and the replacement address of the data cache is written to the replacement address in the address mapping table. This allows the replacement address of the data cache to be accessed when the fault address is accessed, based on the fault address and the address lookup table. The address lookup table includes a fault storage unit index table and a fault storage unit mapping table. The fault storage unit index table is used to look up fault addresses; the address mapping table is used to store the correspondence between fault addresses and replacement addresses.

[0010] In one embodiment, the LRDIMM memory module self-test method further includes: When the storage address of the storage unit is determined to be a normal address based on the comparison result, the data buffer is controlled to delete the data input from the storage controller corresponding to the storage address of the storage unit.

[0011] In one embodiment, the access instruction includes a rewrite access instruction; the LRDIMM memory module self-test method further includes: When the access instruction is determined to be a rewrite access instruction based on the access instruction, the data buffer is controlled to operate in data replacement mode; wherein... In the data replacement mode, the data cache stores the data output by the storage controller as shadow data according to the access address corresponding to the write access instruction, and stores the shadow data in the storage area of ​​the data cache corresponding to the access address.

[0012] In one embodiment, each time a write access instruction is received, the data buffer is controlled to store the data input by the storage controller and output the data input by the storage controller to the storage address corresponding to the storage unit. The data cache is controlled to perform one or more consistency comparisons between the stored data and the data read from the storage unit, and the comparison results are fed back. When the storage address of the storage unit is determined to be a fault address based on the comparison result, the data cache is controlled to block the data transmission path between the fault address of the storage unit and the storage controller.

[0013] In one embodiment, when the access instruction is determined to be a write access instruction and the storage address of the storage unit corresponding to the write access instruction is an unwritten data storage address, the data buffer is controlled to store the data input by the storage controller and output the data input by the storage controller to the storage address corresponding to the storage unit. The data cache is controlled to perform a consistency comparison between the stored data and the data read from the storage unit, and the comparison result is fed back. When the storage address of the storage unit is determined to be a fault address based on the comparison result, the data cache is controlled to block the data transmission path between the fault address of the storage unit and the storage controller.

[0014] In one embodiment, the access instruction includes a read access instruction; the LRDIMM memory module self-test method further includes: When the access instruction is determined to be a read access instruction based on the access instruction, the data buffer is controlled to operate in data replacement mode; wherein... In the data replacement mode, the data cache outputs the shadow data corresponding to the access address stored in the data cache to the storage controller according to the access address corresponding to the read access instruction.

[0015] The present invention also proposes an LRDIMM memory module, the LRDIMM memory module comprising: A memory chip, the memory chip comprising multiple memory cells; A data buffer, wherein the data buffer has a data transmission channel and a storage area; A register clock driver is connected to both the data cache and the storage controller. The register clock driver is used to obtain access commands output by the storage controller. When the access instruction is determined to be a write access instruction, the data buffer is controlled to store the data input by the storage controller and output the data input by the storage controller to the storage address corresponding to the storage unit. The data cache is controlled to perform a consistency comparison between the stored data and the data read from the storage unit, and the comparison result is fed back. When the storage address of the storage unit is determined to be a fault address based on the comparison result, the data cache is controlled to block the data transmission path between the fault address of the storage unit and the storage controller.

[0016] The present invention also proposes an LRDIMM memory module access system, wherein the LRDIMM memory module access includes a storage controller and the LRDIMM memory module as described above.

[0017] This invention acquires access instructions output by the memory controller. When the access instruction is determined to be a write access instruction, it controls the data buffer to store the data input by the memory controller and outputs the data to the memory address corresponding to the memory cell. The data buffer also performs a consistency comparison between the stored data and the data output to the memory cell, and feeds back the comparison result. If the memory address of the memory cell is determined to be a fault address based on the comparison result, the data buffer blocks the data transmission path between the fault address of the memory cell and the memory controller. This invention achieves runtime consistency detection of data in memory cells of the DRAM chip by introducing a register clock driver and data buffer collaborative control mechanism within the LRDIMM module, thereby automatically detecting fault addresses. This invention does not require modification of the DRAM chip structure, nor does it rely on internal DRAM redundancy repair resources; fault detection can be achieved solely through the internal logic control of the LRDIMM module, thereby improving the reliability and stability of the memory system. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating an embodiment of the LRDIMM memory module self-test method of the present invention; Figure 2 This is a flowchart illustrating another embodiment of the LRDIMM memory module self-test method of the present invention; Figure 3 This is a flowchart illustrating another embodiment of the LRDIMM memory module self-test method of the present invention; Figure 4 This is a flowchart illustrating another embodiment of the LRDIMM memory module self-test method of the present invention; Figure 5 This is a flowchart illustrating another embodiment of the LRDIMM memory module self-test method of the present invention; Figure 6 This is a schematic diagram of the circuit structure of an embodiment of the LRDIMM memory module applied to an LRDIMM memory module access system according to the present invention; Figure 7 This is a schematic diagram of the data transmission path in an embodiment of the LRDIMM memory module access system of the present invention; Figure 8 This is a schematic diagram of the circuit structure of an embodiment of the LRDIMM memory module of the present invention; Figure 9 This is a schematic diagram of the timing mechanism for data replacement in an embodiment of the LRDIMM memory module access system of the present invention.

[0020] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0023] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0024] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0025] This invention proposes a self-testing method for LRDIMM memory modules, specifically DDR5 LRDIMM memory modules. In a DDR5 LRDIMM memory module, the memory module includes a data buffer and DRAM (Dynamic Random Access Memory) chips. The number of data buffers and DRAM chips can correspond, with each DRAM chip corresponding to one data buffer. During write operations, data is written to the DRAM via the data buffer (DB), and during read operations, data is returned from the DRAM to the memory controller via the data buffer. In existing LRDIMM architectures, the DB primarily handles data buffering and signal re-driving functions, but lacks the ability to store DRAM data and perform consistency checks. DRAM chips comprise numerous memory cells, numbering in the billions, each with varying data storage capabilities. Furthermore, some memory cells may contain failed memory cells. Failed memory cells may fail due to storage errors caused by differences in memory chip manufacturing processes, hardware damage, or software malfunctions. The address of a failed memory cell may result in a fixed address error (Fail Address). Existing technologies typically rely on ECC or system-level testing to detect memory errors. However, ECC is primarily used for data verification and error correction, making it difficult to accurately pinpoint specific fault addresses, and it also cannot continuously monitor and manage fault addresses within the DIMM module. Therefore, the existing LRDIMM architecture lacks a mechanism that can automatically detect DRAM fault addresses within the module and manage or provide alternative access to fault address data.

[0026] To solve the above problems, refer to Figure 1 , Figures 6 to 9 In one embodiment of the present invention, the LRDIMM memory module self-test method includes: Step S100: Obtain the access command output by the storage controller; In this embodiment, the register clock driver communicates with the memory controller via a Command and Address (CA) bus. The register clock driver receives access instructions from the memory controller, which instruct the memory cells in the memory module to perform specific operations; these instructions can be read or write operations. Based on the access instructions, the register clock driver determines the specific operation the memory controller needs to access, as well as the specific address of the memory cell to be accessed. For example, based on the access instructions, it can be determined that the memory controller needs to read data from the nth row of the mth memory cell in the i-th DRAM chip of the memory module, or that it needs to write data to the nth row of the mth memory cell in the i-th DRAM chip. Here, i, m, and n are all positive integers greater than or equal to 1.

[0027] Step S200: When the access instruction is determined to be a write access instruction according to the access instruction, the data buffer is controlled to store the data input by the storage controller and output the data input by the storage controller to the storage address corresponding to the storage unit. In this embodiment, the data buffer has data transmission capabilities and is equipped with multiple data transmission channels. Through these channels, a data transmission path can be established between the storage unit and the storage controller. That is, when the storage controller needs to store data, the storage unit performs a write operation, and the data is written to the DRAM via the data buffer (DB). When the storage controller needs to read data, the storage unit performs a read operation, and the data is returned to the storage controller from the DRAM via the data buffer.

[0028] Understandably, the data buffer contains a storage area, which can specifically be Static Random-Access Memory (SRAM). This storage area is calculated based on the probability of a faulty memory cell appearing in the DRAM chip and the total number of row addresses within the DRAM chip. The probability of a faulty memory cell can be obtained through experimental testing or empirical analysis. This SRAM can be used to store the data required at the faulty address. That is, when a faulty memory cell is determined to exist, its faulty address is mapped to a replacement address in the SRAM of the data buffer, and the data that would normally be stored at the faulty address is moved to the replacement address.

[0029] LRDIMM memory modules are used in electronic devices such as computers, servers, and other electronic devices. When the storage controller needs to write data to an LRDIMM memory module, it can determine whether there is a faulty memory address in the storage cell using a write-read-compare method. Therefore, during the initial data write, if it is uncertain whether there is a faulty memory address, the data buffer outputs the data to the corresponding memory address of the accessed memory cell, and simultaneously stores the data in the storage area of ​​the data buffer.

[0030] Step S300: Control the data cache to perform a consistency comparison between the stored data and the data read from the storage unit, and feed back the comparison result; When the register clock driver receives a read control command, the data buffer compares the data stored in the storage area with the data read from the storage cell and feeds back the comparison result to the register clock driver. If the register clock driver determines that the data stored in the two storage areas are inconsistent based on the comparison result fed back by the data buffer, it can determine that the storage address of the storage cell is a fault address.

[0031] Step S400: When the storage address of the storage unit is determined to be a fault address based on the comparison result, the data cache is controlled to block the data transmission path between the fault address of the storage unit and the storage controller.

[0032] In this embodiment, the register clock driver can control the data buffer to shield the data transmission path between the fault address of the memory cell and the memory controller, meaning the memory controller no longer accesses the fault address. When the memory controller needs to access the fault address, the data buffer and the memory controller directly perform data read / write interactions. The memory controller directly reads data from the storage area of ​​the data buffer or writes data directly to the storage area of ​​the data buffer. The data output by the memory controller will no longer be written to the fault address or read from the fault address, thereby replacing the data interaction between the memory controller and the memory cell. For example, when the memory controller needs to read data, the data buffer reads data from the address corresponding to the nth row address in the storage area and outputs it to the memory controller. When the memory controller needs to write data, the data buffer writes the data to the address corresponding to the nth row address in the storage area. This invention introduces a collaborative control mechanism between the register clock driver and the data buffer within the LRDIMM module to achieve runtime consistency detection of DRAM chip data, thereby automatically detecting fault addresses.

[0033] This invention acquires access instructions output by the memory controller. When the access instruction is determined to be a write access instruction, it controls the data buffer to store the data input by the memory controller and outputs the data to the memory address corresponding to the memory cell. The data buffer also performs a consistency comparison between the stored data and the data output to the memory cell, and feeds back the comparison result. If the memory address of the memory cell is determined to be a fault address based on the comparison result, the data buffer blocks the data transmission path between the fault address of the memory cell and the memory controller. This invention achieves runtime consistency detection of data in memory cells of the DRAM chip by introducing a register clock driver and data buffer collaborative control mechanism within the LRDIMM module, thereby automatically detecting fault addresses. This invention does not require modification of the DRAM chip structure, nor does it rely on internal DRAM redundancy repair resources; fault detection can be achieved solely through the internal logic control of the LRDIMM module, thereby improving the reliability and stability of the memory system.

[0034] In one embodiment, the step of controlling the data cache to perform a consistency comparison between the stored data and the data read from the storage unit, and then feeding back the comparison result, specifically includes: When the amount of data stored in the data cache reaches a preset amount, the data cache is controlled to perform a consistency comparison between the preset amount of data stored and the data read from the storage unit, and the comparison result is fed back.

[0035] In this embodiment, the preset quantity can be half the storage capacity of the memory in the data cache, one-third of the storage capacity, or one-quarter of the storage capacity. Taking half the storage capacity of the memory in the data cache as an example, when the amount of data stored in the data cache reaches half the storage capacity of the preset quantity memory, the data stored in the memory and the data stored in the storage cell are compared row by row for consistency. If the data stored in the data cache and the data stored in the storage cell are inconsistent, the comparison result is fed back to the register timing driver. The register timing driver establishes a mapping relationship between the replacement address of the data cache and the fault address of the storage cell based on the feedback result, mapping the fault address of the faulty storage cell to the replacement address in the static random access memory in the data cache, thereby realizing the storage of data that should have been stored at the fault address to the replacement address. Furthermore, the register clock driver controls the data cache to block the data transmission path between the storage controller and the row corresponding to the fault address.

[0036] Alternatively, when the data cache stores a preset number of data, it controls the data cache to perform a consistency comparison between the stored preset number of data and the data read from the storage unit, and feeds back the comparison result.

[0037] The preset number can be one row, three rows, or five rows. Taking one row as an example, each time a row of data is stored in the data cache and the storage unit, the data buffer performs a consistency comparison between the row of data stored in the data cache and the row of data stored in the storage unit. If the data stored in the data cache and the data stored in the storage unit are inconsistent, the comparison result is fed back to the register timing driver. Based on this feedback result, the register timing driver establishes a mapping relationship between the replacement address of the data cache and the fault address of the storage unit, mapping the fault address of the faulty storage unit to the replacement address in the static random access memory of the data buffer, thus realizing the storage of data that should have been stored at the faulty address to the replacement address. Furthermore, the register clock driver controls the data buffer to block the data transmission path between the storage controller and the row corresponding to the faulty address.

[0038] Alternatively, the remaining space in the storage area of ​​the data cache is detected, and when the remaining space in the data cache is less than a preset threshold, the data cache is controlled to perform a consistency comparison between the preset number of stored data and the data read from the storage unit, and the comparison result is fed back.

[0039] Understandably, since the data cache's essential function is not storage, the internal storage area of ​​the data cache may be smaller than the DRAM chip's storage space. When the remaining space is zero, meaning the entire storage area is occupied, a row-by-row consistency comparison is performed between the data stored in the memory and the data stored in the memory cell. If the data in the data cache and the data in the memory cell are inconsistent, the comparison result is fed back to the register timing driver. Based on this feedback, the register timing driver establishes a mapping relationship between the replacement address of the data cache and the fault address of the memory cell, mapping the fault address of the faulty memory cell to the replacement address in the static random access memory (SRAM) of the data cache. This allows the data that would otherwise be stored at the faulty address to be stored at the replacement address. Furthermore, the register clock driver controls the data cache to block the data transmission path between the memory controller and the row corresponding to the faulty address.

[0040] It should be noted that the triggering of the comparison mechanism can be selected and switched based on the shadow data stored in the data cache. For example, in the early stages of data writing, the data cache stores little or no shadow data. In this case, the remaining space in the data cache's storage area can be compared with a preset threshold to determine when to trigger the comparison mechanism. In the middle stages of data writing, when the amount of shadow data stored in the data cache reaches a certain level, possibly one-third or one-quarter of the storage capacity, the amount of data stored in the data cache can be compared with a preset amount to determine when to trigger the comparison mechanism. In the later stages of data writing, when the amount of shadow data stored in the data cache reaches a certain level, possibly two-thirds or three-quarters of the storage capacity, a row-by-row comparison method can be selected to compare the consistency between the data stored in the storage unit and the data stored in the memory. In other words, this invention can also determine which comparison triggering mechanism to select based on the storage status of shadow data in the data cache.

[0041] Reference Figure 2 In one embodiment, the LRDIMM memory module self-test method further includes: Step S500: When the storage address of the storage unit is determined to be a fault address based on the comparison result, the fault address is written into the replaced address in the address mapping table, and the replacement address of the data cache is written into the replacement address in the address mapping table, so that when accessing the fault address, the replacement address of the data cache is accessed according to the fault address and the address lookup table; wherein, The address lookup table includes a fault storage unit index table and a fault storage unit mapping table. The fault storage unit index table is used to look up fault addresses; the address mapping table is used to store the correspondence between fault addresses and replacement addresses.

[0042] In this embodiment, the register clock driver can store an address lookup table, a fault memory cell index table including an index number and a fault memory cell address, and an address mapping table including a mapped address column and a mapped address column. The mapped address column is written with the fault memory cell address, and the mapped address column is written with the replacement address of the data buffer. When a fault memory cell is detected, the address of the fault memory cell is written to the mapped address column, and the replacement address of a data buffer is written to the mapped address column. This replaces the memory cell address with the replacement address of the data buffer, and data is written to the replacement address of the data buffer. When it is necessary to access the fault memory cell address, the replacement address of the data buffer that has a mapping relationship with the fault memory cell address can be indexed through the fault memory cell address and the address lookup table. By establishing a mapping relationship between the fault addresses of memory cells in the DRAM chip and the replacement addresses of data buffers, the system can quickly locate the actual DRAM fault address, achieving accurate identification and recording of the fault address.

[0043] In one embodiment, the LRDIMM memory module self-test method further includes: When the storage address of the storage unit is determined to be a normal address based on the comparison result, the data buffer is controlled to delete the data input from the storage controller corresponding to the storage address of the storage unit.

[0044] In this embodiment, when it is determined that the storage unit has storage capacity, the data cache does not need to back up the data of the storage unit. It can delete the data temporarily stored in the data cache corresponding to the address of the storage unit. Thus, when it is determined that the access address in the storage unit corresponding to the access instruction is a normal address according to the access instruction, the data cache is controlled to work in data buffering mode. In the data buffering mode, the data cache connects the data transmission path between the storage unit and the storage controller to enable data interaction between the storage unit and the storage controller.

[0045] In practical applications, when the address that the memory controller needs to access does not match the fault address table, the system transmits data according to the standard data transmission path of LRDIMM: during a write operation (WR), data is transmitted from the memory controller to the memory cell of the DRAM via the data buffer; during a read operation (RD), data is returned from the memory cell of the DRAM to the memory controller via the data buffer. At this time, the data buffer only performs normal TX (data transmission) / RX (data reception) direction control and data buffering functions.

[0046] Reference Figure 3 and Figure 7In one embodiment, the access instruction includes a rewrite access instruction; the LRDIMM memory module self-test method further includes: Step S610: When it is determined that the access instruction is a rewrite access instruction based on the access instruction, the data buffer is controlled to operate in data replacement mode; wherein, Step S620: In the data replacement mode, the data cache stores the data output by the storage controller as shadow data according to the access address corresponding to the write access instruction, and stores the shadow data in the storage area of ​​the data cache corresponding to the access address.

[0047] In this embodiment, when the nth row in the memory cell is determined to be a fault address, the register clock driver, upon receiving an access instruction from the memory controller, determines that the memory controller needs to rewrite data in the nth row of the mth memory cell in the i-th DRAM chip. Since the nth row lacks the capability to store the data required by the external memory controller, it cannot store the data to be written by the external memory controller. At this time, the register clock driver controls the data buffer to block the data transmission path between the memory controller and the row corresponding to the fault address. Furthermore, the data buffer and the memory controller directly interact with each other, with the memory controller directly writing data to the storage area of ​​the data buffer. The data output by the memory controller will no longer be written to the fault address, thus replacing the data interaction between the memory controller and the memory cell. For example, when the memory controller needs to write data, the data buffer writes the data to the address corresponding to the nth row in the storage area.

[0048] Reference Figure 4 and Figure 9 Optionally, the LRDIMM memory module self-test method further includes: Step S710: In the replacement mode, according to the read access instruction, control the corresponding storage unit to output a data strobe signal to the data buffer, so that the data buffer uses the data strobe signal as a timing reference signal; Step S720: Based on the timing reference signal and the access address corresponding to the read access instruction, output the shadow data corresponding to the access address stored in the data buffer to the storage controller.

[0049] In this embodiment, under data replacement mode, the DRAM simply stops reading the data that was originally intended to be stored in the faulty memory cell. The access instructions of the memory controller, corresponding to the command and address instructions, still point to the data that needs to be written to or read from the faulty address. Therefore, the DRAM still outputs a DQS (Data Strobe) signal as a timing reference according to the normal read operation process. The data buffer shields the data transmission path from the memory cell and outputs the replaced data from its internal storage area, ensuring that it is timing-aligned with the DQS signal output by the memory cell. This guarantees that the memory controller can sample according to the normal LRDIMM read timing. By maintaining the DQS timing reference signal provided by the DRAM chip, this invention ensures the compatibility of the system's read timing, allowing the solution to be deployed in existing systems without changing the memory controller design.

[0050] Reference Figure 5 In one embodiment, the LRDIMM memory module self-test method further includes: Step S810: Each time a write access instruction is obtained, the data buffer is controlled to store the data input by the storage controller and output the data input by the storage controller to the storage address corresponding to the storage unit. Step S820: Control the data buffer to perform one or more consistency comparisons between the stored data and the data read from the storage unit, and feed back the comparison results; Step S830: When the storage address of the storage unit is determined to be a fault address based on the comparison result, the data cache is controlled to block the data transmission path between the fault address of the storage unit and the storage controller.

[0051] In this embodiment, each time a write access instruction is received, the data buffer is controlled to store data once and write the data to the storage address corresponding to the storage unit. Then, the data buffer is controlled to perform a consistency comparison between the data read from the storage unit and the data stored in its storage area, and the comparison result is fed back to the register clock driver. When the register clock driver determines that the data stored in the two are inconsistent based on the comparison result fed back by the data buffer, it can determine that the storage address of the storage unit is a fault address.

[0052] Alternatively, the control data buffer can perform multiple consistency comparisons between the data read and stored in the storage unit and the data stored in its storage area until the comparison results fed back by the data buffer determine that the two stored data are inconsistent. In this case, the storage address of the storage unit can be determined to be a fault address and the comparison can be stopped. Alternatively, when the register clock driver determines that the two stored data are consistent based on the comparison results fed back by the data buffer and the number of comparisons reaches a preset number, the register clock driver controls the data buffer to delete the data input by the storage controller corresponding to the storage address of the storage unit.

[0053] In one embodiment, when the access instruction is determined to be a write access instruction and the storage address of the storage unit corresponding to the write access instruction is an unwritten data storage address, the data buffer is controlled to store the data input by the storage controller and output the data input by the storage controller to the storage address corresponding to the storage unit. The data cache is controlled to perform a consistency comparison between the stored data and the data read from the storage unit, and the comparison result is fed back. When the storage address of the storage unit is determined to be a fault address based on the comparison result, the data cache is controlled to block the data transmission path between the fault address of the storage unit and the storage controller.

[0054] In this embodiment, when the register clock driver receives a write access instruction, it can first determine whether the memory address to be accessed by the write access instruction is a memory address that has already been written to. If no data has been written to the memory address, it cannot be determined whether the address is a fault address. Therefore, fault address detection is required, that is, the data buffer needs to be controlled to perform a consistency comparison between the stored data and the data read from the memory cell, and the comparison result is fed back. When the register clock driver determines that the memory address of the memory cell is a fault address based on the comparison result, it controls the data buffer to block the data transmission path between the fault address of the memory cell and the memory controller. When it determines that the memory address of the memory cell is a normal address, it can control the data buffer to provide a normal data transmission path for writing to the memory cell.

[0055] When the access instruction is determined to be a write access instruction, and the storage address of the storage unit corresponding to the write access instruction is a storage address that has already been written with data, the data cache can be controlled to provide a normal data transmission path for writing to the storage unit. The data writing performed at this time can be a data update.

[0056] When the access instruction is determined to be a write access instruction and the storage address of the storage unit corresponding to the write access instruction is a fault address, the data buffer can be controlled to shield the data transmission path between the storage unit and the storage controller. The data buffer stores the stored data as shadow data in its internal storage area. When the register clock driver receives a read access instruction to perform a read operation on the fault address, the data buffer directly outputs the stored shadow data to the storage controller.

[0057] In one embodiment, a read access instruction; the LRDIMM memory module self-test method further includes: When the access instruction is determined to be a read access instruction based on the access instruction, the data buffer is controlled to operate in data replacement mode; In the data replacement mode, the data cache outputs the shadow data corresponding to the access address stored in the data cache to the storage controller according to the access address corresponding to the read access instruction.

[0058] In this embodiment, when the nth row of the memory cell is determined to be a fault address, the register clock driver, upon receiving an access instruction from the memory controller, determines that the memory controller needs to read data from the nth row of the mth memory cell in the i-th DRAM chip of the memory module. Since the nth row lacks the capability to store the data required by the external memory controller, it either does not store the data the external memory controller needs to read, or it cannot store the data the external memory controller needs to write. In this case, the register clock driver controls the data buffer to block the data transmission path between the memory controller and the row corresponding to the fault address. Furthermore, the data buffer and the memory controller directly perform data read / write interactions. The memory controller directly reads data from the storage area of ​​the data buffer, without reading data from the fault address, thus replacing the data interaction between the memory controller and the memory cell. For example, when the memory controller needs to read data, the data buffer reads the data from the address corresponding to the nth row in the storage area and outputs it to the memory controller.

[0059] This invention also proposes an LRDIMM memory module, referring to... Figures 6 to 9 The LRDIMM memory module includes: A memory chip, the memory chip comprising multiple memory cells; A data buffer, wherein the data buffer has a data transmission channel and a storage area; A register clock driver is connected to both the data cache and the storage controller. The register clock driver is used to obtain access commands output by the storage controller. When the access instruction is determined to be a write access instruction, the data buffer is controlled to store the data input by the storage controller and output the data input by the storage controller to the storage address corresponding to the storage unit. The data cache is controlled to perform a consistency comparison between the stored data and the data read from the storage unit, and the comparison result is fed back. When the storage address of the storage unit is determined to be a fault address based on the comparison result, the data cache is controlled to block the data transmission path between the fault address of the storage unit and the storage controller.

[0060] In this embodiment, the register clock driver communicates with the memory controller via a Command and Address (CA) bus. The register clock driver receives access instructions from the memory controller, which instruct the memory cells in the memory module to perform specific operations; these instructions can be read or write operations. Based on the access instructions, the register clock driver determines the specific operation the memory controller needs to access, as well as the specific address of the memory cell to be accessed. For example, based on the access instructions, it can be determined that the memory controller needs to read data from the nth row of the mth memory cell in the i-th DRAM chip of the memory module, or that it needs to write data to the nth row of the mth memory cell in the i-th DRAM chip. Here, i, m, and n are all positive integers greater than or equal to 1.

[0061] Understandably, the data buffer contains a storage area, which can specifically be Static Random-Access Memory (SRAM). This storage area is calculated based on the probability of a faulty memory cell appearing in the DRAM chip and the total number of row addresses within the DRAM chip. This SRAM can be used to store the data required at the faulty address. That is, when a faulty memory cell is determined to exist, its faulty address is mapped to a replacement address in the SRAM of the data buffer, and the data that would normally be stored at the faulty address is moved to the replacement address.

[0062] LRDIMM memory modules are used in electronic devices such as computers, servers, and other electronic devices. When the storage controller needs to write data to an LRDIMM memory module, it can determine whether there is a faulty memory address in the storage cell using a write-read-compare method. Therefore, during the initial data write, if it is uncertain whether there is a faulty memory address, the data buffer outputs the data to the corresponding memory address of the accessed memory cell, and simultaneously stores the data in the storage area of ​​the data buffer.

[0063] When the register clock driver receives a read control command, the data buffer compares the data stored in the storage area with the data read from the storage cell and feeds back the comparison result to the register clock driver. If the register clock driver determines that the data stored in the two storage areas are inconsistent based on the comparison result fed back by the data buffer, it can determine that the storage address of the storage cell is a fault address.

[0064] In this embodiment, the register clock driver can control the data buffer to shield the data transmission path between the fault address of the memory cell and the memory controller, meaning the memory controller no longer accesses the fault address. When the memory controller needs to access the fault address, the data buffer and the memory controller directly perform data read / write interactions. The memory controller directly reads data from the storage area of ​​the data buffer or writes data directly to the storage area of ​​the data buffer. The data output by the memory controller will no longer be written to the fault address or read from the fault address, thereby replacing the data interaction between the memory controller and the memory cell. For example, when the memory controller needs to read data, the data buffer reads data from the address corresponding to the nth row address in the storage area and outputs it to the memory controller. When the memory controller needs to write data, the data buffer writes the data to the address corresponding to the nth row address in the storage area. This invention introduces a collaborative control mechanism between the register clock driver and the data buffer within the LRDIMM module to achieve runtime consistency detection of DRAM chip data, thereby automatically detecting fault addresses.

[0065] This invention also proposes an LRDIMM memory module access system, referring to... Figures 6 to 9 The LRDIMM memory module access includes the storage controller and the LRDIMM memory module as described above.

[0066] The detailed structure of the LRDIMM memory module self-test method can be referred to the above embodiments, and will not be repeated here. It can be understood that since the above LRDIMM memory module self-test method is used in the LRDIMM memory module access system of the present invention, the embodiments of the LRDIMM memory module access system of the present invention include all the technical solutions of all embodiments of the above LRDIMM memory module self-test method, and the technical effects achieved are also completely the same, and will not be repeated here.

[0067] In practical applications, replacing DRAM chips with data buffers for data transmission can specifically include the following processes: During the initial write operation (WR), data from the memory controller is simultaneously written to the DRAM chip and the data buffer under the control of the register clock driver. The data buffer stores shadow data corresponding to the address in its internal memory area, such as SRAM, for subsequent data consistency checks. Simultaneously, the register clock driver records the mapping relationship between the addresses of memory cells in the DRAM chip and the internal memory addresses of the data buffer, establishing an address mapping table between the DRAM chip and the data buffer.

[0068] During a read operation (RD), the data returned by the DRAM chip first enters the data buffer, while the data buffer reads the shadow data for the corresponding address from its internal SRAM. The data buffer compares the data from the DRAM chip with the shadow data. When they match, the data at that address is considered normal; when they do not match, the data buffer sends a mismatch message to the register clock driver. Based on the information returned by the data buffer, the register clock driver determines the actual DRAM address using the address mapping table between the DRAM chip and the data buffer, records this address as a fault address, and stores it in the fault address lookup table.

[0069] When the memory controller accesses the memory cell again, if the access address does not match the fault address table, the register clock driver controls the data buffer to transmit data according to the standard LRDIMM data path: during a write operation (WR), data is transferred from the memory controller to the DRAM chip via the data buffer; during a read operation (RD), data is returned from the DRAM chip to the memory controller via the data buffer. At this time, the data buffer only performs normal TX / RX direction control and data buffering functions.

[0070] When a write operation address matches a fault address in the fault address table, a shadow data creation process is triggered. The register clock driver determines the corresponding SRAM storage address in the data buffer based on the mapping table and controls the data buffer to enter replacement mode. At this time, data from the memory controller is no longer written to the DRAM chip, but instead to the corresponding storage location in the SRAM within the data buffer, thus forming shadow data corresponding to the fault address. During a read operation, when the access address matches the fault address table, the register clock driver controls the data buffer to read the corresponding shadow data from its internal SRAM and outputs this data as read data to the memory controller, instead of forwarding the original data from the DRAM chip, thereby achieving the replacement reading of the fault address data.

[0071] In summary, when the system accesses this address again, the register clock driver first determines whether the accessed address is a faulty address. If the address is a normal address, the system accesses it according to the normal data path of the LRDIMM; if the address is a faulty address, the register clock driver controls the data buffer to initiate a data substitution mechanism. During read operations, the data buffer no longer outputs the data returned by the DRAM chip, but directly reads the shadow data of the corresponding address from the internal SRAM and outputs it to the memory controller, thereby realizing the substitution access to the faulty address data. The first address lookup table can be deleted, retaining only the faulty address, or the faulty address can be stored separately.

[0072] The above description is merely an optional embodiment of the present invention and does not limit the scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of protection of the present invention.

Claims

1. A self-test method for an LRDIMM memory module, characterized in that, The LRDIMM memory module includes a register clock driver, a data buffer, and a storage unit. The data buffer includes a storage area for storing the data required to store the fault address. The LRDIMM memory module self-test method includes: The register clock driver obtains the access instruction output by the memory controller. The access instruction is used to instruct the memory cell in the LRDIMM memory module to perform a read operation instruction or a write operation instruction. The access instruction is used to determine whether the memory controller needs to read the data of the nth row of the mth memory cell in the i-th DRAM chip in the LRDIMM memory module, or to determine whether the memory controller needs to write data to the nth row of the mth memory cell in the i-th DRAM chip. When the access instruction is determined to be a write access instruction based on the access instruction, the data buffer is controlled to store the data input by the storage controller into the storage area, and the data input by the storage controller is output to the storage address corresponding to the storage unit; The data buffer is controlled to perform a consistency comparison between the stored data and the data read from the storage unit, and the comparison result is fed back to the register clock driver to realize runtime consistency detection of the data in the storage unit; When the register clock driver determines that the storage address of the storage cell is a fault address based on the comparison result, it maps the fault address to the replacement address in the storage area of ​​the data buffer, stores the data that should have been stored at the fault address to the replacement address, and controls the data buffer to shield the data transmission path between the fault address of the storage cell and the storage controller, and the data buffer and the storage controller directly perform data read and write interactions. The DRAM still outputs the DQS signal as a timing reference according to the normal read operation process, and the data buffer outputs the replaced data from the storage area to keep it in timing alignment with the DQS signal output by the storage cell. The data cache has multiple preset comparison mechanisms for comparing the stored data with the data read from the storage unit. The triggering of these multiple comparison mechanisms is selected and switched according to the amount of data stored in the data cache.

2. The LRDIMM memory module self-test method as described in claim 1, characterized in that, The step of controlling the data cache to perform a consistency comparison between the stored data and the data read from the storage unit, and then feeding back the comparison result, specifically includes: When the amount of data stored in the data cache reaches a preset amount, the data cache is controlled to perform a consistency comparison between the preset amount of data stored and the data read from the storage unit, and the comparison result is fed back.

3. The LRDIMM memory module self-test method as described in claim 1, characterized in that, The step of controlling the data cache to perform a consistency comparison between the stored data and the data read from the storage unit, and then feeding back the comparison result, specifically includes: When the data cache stores a preset number of data, it controls the data cache to perform a consistency comparison between the stored preset number of data and the data read from the storage unit, and feeds back the comparison result.

4. The LRDIMM memory module self-test method as described in claim 1, characterized in that, The step of controlling the data cache to perform a consistency comparison between the stored data and the data read from the storage unit, and then feeding back the comparison result, specifically includes: Detect the remaining space in the storage area of ​​the data cache; When the remaining space in the data cache is less than a preset threshold, the data cache is controlled to perform a consistency comparison between the preset number of stored data and the data read from the storage unit, and the comparison result is fed back.

5. The LRDIMM memory module self-test method as described in claim 1, characterized in that, The LRDIMM memory module self-test method also includes: When the storage address of the storage unit is determined to be a fault address based on the comparison result, the fault address is written into the replaced address in the address lookup table, and the replacement address of the data cache is written into the replacement address in the address lookup table. This allows the replacement address of the data cache to be accessed when the fault address is accessed, based on the fault address and the address lookup table. The address lookup table includes a fault storage unit index table and a fault storage unit mapping table. The fault storage unit index table is used to look up fault addresses; the fault storage unit mapping table is used to store the correspondence between fault addresses and replacement addresses.

6. The LRDIMM memory module self-test method as described in claim 1, characterized in that, The LRDIMM memory module self-test method also includes: When the storage address of the storage unit is determined to be a normal address based on the comparison result, the data buffer is controlled to delete the data input from the storage controller corresponding to the storage address of the storage unit.

7. The LRDIMM memory module self-test method as described in claim 1, characterized in that, The access instructions include rewrite access instructions; The LRDIMM memory module self-test method also includes: When the access instruction is determined to be a rewrite access instruction based on the access instruction, the data buffer is controlled to operate in data replacement mode; wherein... In the data replacement mode, the data cache stores the data output by the storage controller as shadow data according to the access address corresponding to the write access instruction, and stores the shadow data in the storage area of ​​the data cache corresponding to the access address.

8. The LRDIMM memory module self-test method as described in claim 1, characterized in that, The LRDIMM memory module self-test method also includes: Upon receiving a write access instruction, the data buffer is controlled to store the data input by the storage controller and output the data input by the storage controller to the storage address corresponding to the storage unit. The data cache is controlled to perform one or more consistency comparisons between the stored data and the data read from the storage unit, and the comparison results are fed back. When the storage address of the storage unit is determined to be a fault address based on the comparison result, the data cache is controlled to block the data transmission path between the fault address of the storage unit and the storage controller.

9. An LRDIMM memory module, characterized in that, The LRDIMM memory module includes: A memory chip, the memory chip comprising multiple memory cells; A data buffer, wherein the data buffer has a data transmission channel and a storage area; A register clock driver is connected to the data buffer and the memory controller respectively. The register clock driver is used to obtain the access instruction output by the memory controller. The access instruction is used to instruct the memory cell in the LRDIMM memory module to perform a read operation instruction or a write operation instruction. The access instruction is used to determine that the memory controller needs to read the data of the nth row of the mth memory cell in the i-th DRAM chip in the LRDIMM memory module, or to determine that the memory controller needs to write data to the nth row of the mth memory cell in the i-th DRAM chip. When the access instruction is determined to be a write access instruction based on the access instruction, the data buffer is controlled to store the data input by the storage controller into the storage area, and the data input by the storage controller is output to the storage address corresponding to the storage unit; The data cache is controlled to perform a consistency comparison between the stored data and the data read from the storage unit, and the comparison result is fed back to achieve runtime consistency detection of the data in the storage unit; When the storage address of the storage unit is determined to be a fault address based on the comparison result, the fault address is mapped to the replacement address in the storage area of ​​the data cache, the data that originally needed to be stored at the fault address is stored at the replacement address, and the data cache is controlled to shield the data transmission path between the fault address of the storage unit and the storage controller, and the data cache and the storage controller directly perform data read and write interaction. The DRAM still outputs the DQS signal as a timing reference according to the normal read operation process, and the data buffer outputs the replaced data from the storage area to keep it in timing alignment with the DQS signal output by the storage cell. The data cache has multiple preset comparison mechanisms for comparing the stored data with the data read from the storage unit. The triggering of these multiple comparison mechanisms is selected and switched according to the amount of data stored in the data cache.

10. An LRDIMM memory module access system, characterized in that, The LRDIMM memory module access system includes a storage controller and the LRDIMM memory module as described in claim 9.

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