An energy internet of things-oriented low-power-consumption NPU chip system and a scheduling method
By designing a low-power NPU chip system and employing dedicated operator acceleration, hybrid quantization, and intelligent scheduling mechanisms, the problems of high power consumption, high cost, and low inference efficiency of edge NPU chips in the energy IoT have been solved. This achieves low-power, low-latency, and highly compatible AI inference capabilities, making it suitable for scenarios such as smart metering and smart meter reading.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUNAN TENGFA MICROELECTRONICS CO LTD
- Filing Date
- 2026-05-15
- Publication Date
- 2026-07-14
AI Technical Summary
Existing NPU chips suffer from high power consumption, high cost, and low inference efficiency in energy IoT edge applications, making it difficult to meet the long-term operation requirements of battery-powered devices. Furthermore, their heterogeneous integration interfaces are complex, resulting in large data interaction delays and a lack of hardware support for TinyML models.
A low-power NPU chip system was designed, including a lightweight computing core, a simplified heterogeneous interface module, an intelligent collaborative scheduling module, and a dynamic layout adaptation module. It adopts a dedicated operator acceleration unit, hybrid quantization processing, a dual-interface architecture, and an intelligent scheduling mechanism to support the dynamic loading and fast switching of TinyML models, thereby achieving low-latency data transmission and efficient resource management.
It achieves standby power consumption of less than 1μW and inference power consumption of less than 5mW, reduces interface area by 90%, inference latency of less than 1ms, and reduces adaptation cost by 80%, making it suitable for smart metering and smart meter reading scenarios.
Smart Images
Figure CN122195622B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of energy Internet of Things (IoT) technology, and particularly relates to a low-power NPU chip system and scheduling method for energy IoT. Background Technology
[0002] With the development of energy IoT technology, the demand for AI inference functions in edge devices such as smart metering and smart meter reading is becoming increasingly urgent. This necessitates the local deployment of lightweight neural network models to achieve functions such as abnormal data detection and meter character recognition. Neural Processing Units (NPUs), as dedicated AI acceleration hardware, have become the core carrier of edge AI due to their high computing power density. However, edge devices are limited by battery power and physical space, placing stringent requirements on the NPU's power consumption, area, and heterogeneous integration capabilities (integrating chips with different functions (such as NPUs, MCUs, and communication chips) into a single system through interfaces and scheduling mechanisms to achieve functional complementarity). They must achieve low-power operation, seamless compatibility with existing MCUs and communication chips, and efficient support for lightweight models such as TinyML while ensuring inference accuracy. Currently, most NPU chips in the industry are designed for cloud or edge servers, making it difficult to directly adapt to the specific needs of energy IoT edge scenarios.
[0003] Existing technologies typically employ the following solutions: General-purpose low-power NPU solutions: These utilize the Da Vinci AI core architecture, supporting inference for various neural network models, achieving an INT8 computing power of 22 TOPS with a power consumption of 12W. While this solution achieves low power consumption through hardware scheduling and operator optimization, it is not customized for the small data volume and low-frequency inference scenarios of the energy IoT. Its heterogeneous integration interface (PCIe) is complex, unsuitable for the compact layout of edge devices, and lacks sufficient adaptability to TinyML models, resulting in computing power redundancy. Heterogeneous integration acceleration solutions (such as edge AI solutions based on FPGA+MCU): These accelerate AI algorithms through FPGA, while the MCU handles system scheduling and data interaction. Although this solution meets some low-power requirements, FPGA development has a long development cycle, poor flexibility, and an imperfect collaborative scheduling mechanism with communication chips, leading to high data transmission latency and difficulty in achieving real-time inference. Another relevant solution is HopScotch's NPU data layout optimization technology, which reduces layout reordering overhead through architecture-compiler co-design. However, this solution is geared towards general DNN models, does not consider the lightweight characteristics of edge TinyML models and the low power consumption constraints of the energy IoT, and does not involve heterogeneous integration design with MCUs and communication chips.
[0004] In summary, existing technical solutions generally suffer from the following technical problems in energy IoT edge applications: excessive power consumption, making it difficult to meet the long-term operational needs of battery-powered equipment; complex heterogeneous integration interfaces, resulting in high adaptation costs and significant data interaction latency; insufficient hardware support for TinyML models, leading to low inference efficiency and redundant computing power; and a lack of data layout optimization mechanisms for small-data-volume scenarios, resulting in additional power consumption and latency overhead. These problems severely restrict the large-scale deployment and application of artificial intelligence technology in energy IoT edge devices. Summary of the Invention
[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a low-power NPU chip system for the energy Internet of Things (IoT), thereby solving the problems of high power consumption, high cost, and low inference efficiency in the existing edge-side NPU architecture for the energy IoT. In addition, this invention also provides a scheduling method for a low-power NPU chip system for the energy IoT.
[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0007] In a first aspect, the present invention provides a low-power NPU chip system for the energy Internet of Things, comprising:
[0008] The lightweight computing core is used to perform inference computation of lightweight machine learning models. The lightweight computing core includes a dedicated operator acceleration unit, a hybrid quantization processing module, and a model dynamic loading unit. The dedicated operator acceleration unit is used for depthwise separable convolution, temporal feature extraction, and pooling operations. The hybrid quantization processing module supports dynamic quantization and dequantization processing with mixed precision of INT4 and INT8. The model dynamic loading unit is used for dynamic loading and fast switching of multi-scenario TinyML models (lightweight and its learning model, suitable for low-power, small-volume neural network models on edge devices).
[0009] A simplified heterogeneous interface module is used to realize data interaction between the NPU and the microcontroller and communication chip. The simplified heterogeneous interface module includes a control interface and a data interface. The control interface adopts a simplified serial interface to realize low-latency instruction interaction, and the data interface adopts a direct memory access architecture to realize high-speed data transfer.
[0010] The intelligent collaborative scheduling module is used to control the working state and resource allocation of the NPU. The intelligent collaborative scheduling module includes a task triggering unit, a state management unit, and a resource allocation unit. The task triggering unit is used to detect inference task requests and trigger the NPU to wake up from the sleep state. The state management unit is used to control the switching between working state and sleep state of each module inside the NPU. The resource allocation unit is used to dynamically adjust the clock frequency according to the task type and coordinate the parallel execution of computing and data transmission.
[0011] A dynamic layout adaptation module is used to optimize the memory layout of input data. The dynamic layout adaptation module has a pre-built layout template library that stores commonly used tensor memory layout formats. The dynamic layout adaptation module dynamically adjusts the layout parameters according to the actual dimensions of the input data so that the data arrangement order matches the memory access mode of the computing core.
[0012] Furthermore, the dedicated operator acceleration unit integrates a depth-separable convolution acceleration circuit, a temporal feature extraction circuit, and a pooling operation circuit, and reduces the number of memory accesses by reusing the weight buffer.
[0013] Furthermore, the control interface is a 2-wire SPI interface, connected to the microcontroller, used to transmit model loading instructions and inference start instructions, with an interface latency of less than 50 nanoseconds; the data interface is a DMA interface (Direct Memory Access, which enables direct data transfer between devices without CPU intervention, reducing latency and power consumption), connected to the microcontroller and communication chip, used to achieve direct data transfer with a data transmission rate of not less than 800Mbps and an interaction latency of less than 100 nanoseconds.
[0014] Furthermore, the simplified heterogeneous interface module also includes an automatic negotiation mechanism for adaptively matching the timing and electrical characteristics of different microcontrollers and communication chips.
[0015] Furthermore, the state management unit only wakes up the lightweight computing core and the minimalist heterogeneous interface module when the inference task is executed, while the other modules remain in sleep mode; after the task is completed, it controls the NPU to enter sleep mode, so that the static power consumption is less than 1 microwatt.
[0016] Furthermore, the resource allocation unit increases the NPU clock frequency to 200MHz when performing inference tasks and decreases the clock frequency to 1MHz when idle.
[0017] Furthermore, the tensor memory layout formats pre-stored in the layout template library include NHWC and NCHW.
[0018] Furthermore, the dynamic layout adaptation module also integrates an on-chip cache optimization unit, which is used to implement a tiered storage strategy based on data access frequency.
[0019] Secondly, the present invention also provides a scheduling method for a low-power NPU chip system for the energy Internet of Things, comprising the following steps:
[0020] S10. The microcontroller sends an initialization command to the NPU through the control interface. The NPU dynamically loads the specified TinyML model from the external memory into the internal model storage unit. After loading is completed, the NPU enters a low-power sleep state.
[0021] S20: The communication chip receives sensor data and transmits it to the data buffer unit inside the NPU through the data interface. After the data transmission is completed, the intelligent collaborative scheduling module is triggered to wake up the NPU.
[0022] S30, the dynamic layout adaptation module adjusts the memory layout format of the input data in the cache to adapt it to the memory access mode of the computing core; the lightweight computing core performs inference calculations, including quantization processing, special operators to accelerate calculations, and intermediate result fusion.
[0023] S40. The inference results are transmitted back to the communication chip via the data interface, and the communication chip uploads the results. After the task is completed, the intelligent collaborative scheduling module controls the NPU to switch back to the sleep state, waiting for the next task to be triggered.
[0024] Furthermore, the communication chip can communicate using one or more of LoRa and Wi-Fi.
[0025] The low-power NPU chip system and scheduling method for the energy Internet of Things provided by this invention have at least the following advantages compared with the prior art:
[0026] Existing edge-side NPU architectures in the energy IoT suffer from high power consumption, high cost, and low inference efficiency. This invention addresses these pain points in edge-side NPUs regarding power consumption, compatibility, and inference efficiency through customized microarchitecture design, simplified heterogeneous integration, and intelligent scheduling mechanisms.
[0027] Significant low power consumption advantages: The triple low power design of "dedicated operator acceleration + hybrid quantization + dynamic sleep" makes the standby power consumption <1μW and the inference power consumption <5mW, which is significantly lower than the power consumption of existing general-purpose low power NPU (12W level) and fully meets the battery power supply requirements of edge devices.
[0028] Strong heterogeneous integration and compatibility: The dual-interface (SPI+DMA) architecture and automatic negotiation mechanism can be adapted to mainstream MCUs and communication chips, reducing interface area by 90% and adaptation cost by 80%;
[0029] High inference efficiency: Dedicated operator acceleration unit and hybrid quantization technology, compatible with INT4 / INT8 hybrid quantization, make TinyML model inference latency <1ms, which is more than 50% higher than FPGA+MCU solution, and supports dynamic switching of models in multiple scenarios;
[0030] Strong scenario adaptability: The dynamic layout adaptation module is optimized for small data volume scenarios in the energy Internet of Things, reducing layout reordering overhead by 90% and further improving energy efficiency ratio. It can be widely used in edge AI scenarios such as smart metering and smart meter reading. Attached Figure Description
[0031] To more clearly illustrate the solutions of the present invention, a brief introduction will be given to the drawings used in the description of the embodiments below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0032] Figure 1 An overall architecture diagram of a low-power NPU chip system for the energy Internet of Things is provided in this embodiment of the invention;
[0033] Figure 2 A block diagram of the lightweight computing core internal structure of a low-power NPU chip system for the Internet of Energy, provided in an embodiment of the present invention;
[0034] Figure 3 A simplified heterogeneous interface module topology diagram of a low-power NPU chip system for the energy Internet of Things provided in this embodiment of the invention;
[0035] Figure 4 A state machine diagram of an intelligent collaborative scheduling module for a low-power NPU chip system for the Internet of Things in the energy sector, provided in an embodiment of the present invention;
[0036] Figure 5 A flowchart of the dynamic layout adaptation module of a low-power NPU chip system for the Internet of Energy provided in this embodiment of the invention;
[0037] Figure 6 A flowchart illustrating a scheduling method for a low-power NPU chip system for the Internet of Things in the energy sector, provided as an embodiment of the present invention. Detailed Implementation
[0038] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
[0040] This invention provides a low-power NPU chip system for the energy Internet of Things (IoT), applied to the NPU power consumption control and scheduling process of battery-powered devices in the energy IoT. The low-power NPU chip system for the energy IoT includes:
[0041] The lightweight computing core performs inference computations for lightweight machine learning models. It includes a dedicated operator acceleration unit, a hybrid quantization processing module, and a model dynamic loading unit. The dedicated operator acceleration unit handles depthwise separable convolution, temporal feature extraction, and pooling operations. The hybrid quantization processing module supports dynamic quantization and dequantization processing with mixed INT4 and INT8 precision. The model dynamic loading unit handles dynamic loading and rapid switching of TinyML models across multiple scenarios. A simplified heterogeneous interface module facilitates data interaction between the NPU and the microcontroller and communication chips. This module includes a control interface and a data interface. The control interface uses a simplified serial interface for low-latency instruction interaction, while the data interface uses a direct memory access architecture for high-speed data transfer. An intelligent collaborative scheduling module is also included. The module controls the NPU's working state and resource allocation. The intelligent collaborative scheduling module includes a task triggering unit, a state management unit, and a resource allocation unit. The task triggering unit detects inference task requests and triggers the NPU to wake up from its sleep state. The state management unit controls the switching between working and sleep states for each module within the NPU. The resource allocation unit dynamically adjusts the clock frequency according to the task type and coordinates the parallel execution of computation and data transmission. The dynamic layout adaptation module optimizes the memory layout of the input data. It has a pre-built layout template library that stores commonly used tensor memory layout formats. The module dynamically adjusts the layout parameters according to the actual dimensions of the input data to match the data arrangement order with the memory access mode of the computing core.
[0042] This invention solves the technical problems of high power consumption, high cost, poor heterogeneous integration compatibility, and low inference efficiency of existing NPU chips in edge applications. It can be widely used in edge AI inference scenarios of energy Internet of Things such as smart metering and smart meter reading.
[0043] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
[0044] This invention provides a low-power NPU chip system for the energy Internet of Things (IoT), applied to the NPU power consumption control and scheduling process of battery-powered devices in the energy IoT, combined with... Figures 1 to 5 In this embodiment, the low-power NPU chip system for the energy Internet of Things includes:
[0045] The lightweight computing core is used to perform inference computations for lightweight machine learning models, and is specifically designed for the operator features of TinyML models, such as... Figure 2 As shown, the lightweight computing core includes a dedicated operator acceleration unit, a hybrid quantization processing module, and a model dynamic loading unit. The dedicated operator acceleration unit is used for depthwise separable convolution, temporal feature extraction (adapted to LSTM), and pooling operations. It integrates lightweight circuitry for these operations and significantly reduces memory accesses by reusing the weight buffer, resulting in a 40% reduction in area and a 50% reduction in power consumption compared to general-purpose computing units. The hybrid quantization processing module supports dynamic quantization and dequantization of mixed precision INT4 and INT8 through hardware circuitry, reducing model storage footprint by 75% and inference power consumption by 60%. The model dynamic loading unit is used for dynamic loading and rapid switching of multi-scenario TinyML models. It communicates with external Flash via an SPI interface, supporting dynamic loading and rapid switching of multi-scenario TinyML models (such as anomaly detection and character recognition). The model loading latency is less than 500 microseconds. These three sub-modules work together to achieve efficient and low-power edge model inference.
[0046] Specifically, in this embodiment, the hybrid quantization processing module possesses layer-level sensitivity adaptive capability. During the dynamic model loading process, the model dynamic loading unit parses the parameters of each layer of the TinyML model and extracts the accuracy requirement label for that layer. For the initial convolutional layer in the model, which is more sensitive to accuracy, the hybrid quantization processing module automatically configures it to INT8 mode to ensure recognition accuracy; for the temporal feature extraction layer, which has a large computational load but redundant accuracy, it automatically switches to INT4 mode to reduce memory access pressure and inference power consumption. Through this hardware-native multi-precision dynamic switching, the optimal balance between power consumption and accuracy is achieved in the small sample scenario of the energy Internet of Things.
[0047] In some other embodiments, a hybrid architecture of "simplified GPU core + dedicated accelerator" can be adopted, with the simplified GPU core responsible for general computing and the dedicated accelerator responsible for accelerating core operators, which is suitable for scenarios with higher requirements for model compatibility.
[0048] The simplified heterogeneous interface module is used to realize data interaction between the NPU and the microcontroller and communication chip. The module includes a control interface and a data interface. The control interface uses a simplified serial interface to achieve low-latency instruction interaction, while the data interface uses a direct memory access architecture to achieve high-speed data transfer. Specifically, the simplified heterogeneous interface module adopts a dual-interface architecture design to adapt to different types of data interaction scenarios within the system, such as... Figure 3As shown, the control interface uses a simplified 2-wire SPI interface, dedicated to low-latency instruction interaction between the MCU and NPU (such as model loading, inference startup, and other control commands). Its interface latency is less than 50 nanoseconds, and compared to general-purpose high-speed interfaces like PCIe, its circuit area is reduced by 90%. The data interface employs a high-efficiency DMA direct memory access architecture, supporting high-speed, direct data transfer between the NPU, MCU, and communication chip without frequent intervention from the main control CPU. Data transfer rates can reach 800Mbps, with an interaction latency of less than 100 nanoseconds. Furthermore, this interface features an auto-negotiation mechanism, adaptively matching the timing and electrical characteristics of different MCU and communication chip models, enhancing system compatibility and ease of use.
[0049] In some other embodiments, the SPI control interface can be replaced with an I2C interface and the DMA data interface can be replaced with a UART interface, which can also achieve low-latency heterogeneous integration and is suitable for scenarios with low transmission rate requirements.
[0050] The intelligent collaborative scheduling module controls the NPU's working state and resource allocation. It includes a task triggering unit, a state management unit, and a resource allocation unit. The task triggering unit detects inference task requests and wakes the NPU from sleep mode. The state management unit controls the switching between working and sleep states for each module within the NPU. The resource allocation unit dynamically adjusts the clock frequency based on task type and coordinates the parallel execution of computation and data transmission. Specifically, the intelligent collaborative scheduling module employs a three-stage scheduling strategy of "task triggering - state switching - resource allocation" to achieve efficient management and energy-saving control of system hardware resources. Figure 4 As shown, the task triggering unit continuously monitors control command signals from the MCU and data input signals from the communication chip. Once a valid inference task request is detected, it triggers the NPU to wake up from deep sleep. The state management unit finely controls the working state of each module within the NPU. During inference task execution, only the necessary lightweight computing cores and data interface modules are woken up, while the remaining modules remain in sleep mode to save power. After the task is completed, the entire NPU is quickly switched back to sleep mode, at which point the static power consumption is less than 1 microwatt. The resource allocation unit dynamically allocates system resources according to the task type (such as data acquisition, model inference, and result uploading). During inference execution, the NPU clock frequency is increased to 200MHz to ensure performance, while during idle periods, the frequency is reduced to 1MHz to reduce dynamic power consumption. At the same time, this unit coordinates the parallel execution of data transmission and computing tasks, reducing idle time in the pipeline and thus improving overall processing efficiency.
[0051] In some other embodiments, a scheduling strategy of "round-robin scheduling + priority preemption" can be adopted. Round-robin scheduling ensures task fairness, while priority preemption ensures real-time response to urgent tasks, which is suitable for multi-task concurrent scenarios.
[0052] The dynamic layout adaptation module optimizes the memory layout of input data. It has a built-in layout template library storing commonly used tensor memory layout formats. The module dynamically adjusts layout parameters based on the actual dimensions of the input data to match the data arrangement order with the memory access patterns of the computational core. Specifically, for example... Figure 5 As shown, the dynamic layout adaptation module is specifically designed for small data volume characteristics (such as tensors of size 32×32×8) commonly found in scenarios such as the Energy Internet of Things. It implements a fixed, configurable layout mapping mechanism to reduce the overhead of data processing and movement. The core of this mechanism lies in its layout template library, which pre-stores commonly used tensor memory layout formats (such as NHWC and NCHW) in TinyML models, eliminating the need for dynamic template searching at runtime, thus significantly reducing the complexity and overhead of hardware implementation. Its adaptive adjustment unit can dynamically fine-tune the layout parameters according to the actual dimensions of the input data, ensuring that the final arrangement order of the data in memory highly matches the memory access pattern of the computing core, thereby completely avoiding expensive data reordering operations. In addition, the module integrates a 256KB on-chip cache optimization unit, which implements a hierarchical storage strategy based on the analysis of data access frequency, enabling a hit rate of up to 95% for frequently accessed hot data, effectively reducing the number of accesses to high-power off-chip memory, and reducing the overall system power consumption.
[0053] In some other embodiments, a hybrid mechanism of "static layout + local dynamic adjustment" can be adopted. The static layout ensures basic overhead, while the local dynamic adjustment adapts to changes in data dimensions, which is suitable for scenarios with large fluctuations in data dimensions.
[0054] This invention also provides a scheduling method for a low-power NPU chip system for the energy Internet of Things, applied to the low-power NPU chip system for the energy Internet of Things described in the above embodiments, combined with... Figures 1 to 6 In this embodiment, the scheduling method for the low-power NPU chip system for the energy Internet of Things includes the following steps:
[0055] S10. During the initialization phase, the microcontroller sends an initialization command to the NPU through the SPI control interface. The NPU dynamically loads the specified TinyML model from the external memory into the internal model storage unit. After loading is complete, the NPU enters a low-power sleep state.
[0056] S20. During the data acquisition phase, the communication chip (such as a LoRa or Wi-Fi module) receives raw data from the sensor (such as meter current and meter reading images) and transmits the data to the data buffer unit inside the NPU through a high-speed DMA data interface. After the data transmission is completed, the intelligent collaborative scheduling module is triggered to wake up the NPU.
[0057] Specifically, in this embodiment, to achieve extremely low power consumption control of less than 1 microwatt of static power consumption, an asynchronous interrupt wake-up mechanism is adopted. When the communication chip receives sensor data, it first sends a pulse signal to the intelligent collaborative scheduling module via a hardware wake-up pin. After the task triggering unit recognizes this signal, the state management unit first raises the NPU's internal core voltage and restores the clock supply. Once the NPU is ready, high-speed data transfer is initiated via the DMA data interface, thereby avoiding data loss during deep sleep and ensuring the real-time performance and reliability of the system response.
[0058] S30. Entering the inference phase, the dynamic layout adaptation module adjusts the memory layout format of the input data in the cache to adapt it to the memory access mode of the computing core; the lightweight computing core performs inference calculations, including quantization processing, special operator acceleration of calculations, and fusion of intermediate results.
[0059] S40. During the result output stage, the inference result is sent back to the communication chip via the DMA data interface, and the communication chip uploads the result to the cloud server. After the task is completed, the intelligent collaborative scheduling module controls the NPU to switch back to the sleep state, waiting for the next task to be triggered with extremely low static power consumption, thus completing a complete work cycle.
[0060] Example 1
[0061] Smart metering anomaly detection scenario
[0062] System configuration: The NPU chip uses TSMC 7nm process with a core area of 0.3mm²; the MCU is STM32L476 (low power type), and the communication chip is LoRa module (SX1278); Model configuration: Load TinyML lightweight anomaly detection model (based on depthwise separable convolution + LSTM), model size 90KB, INT8 quantization.
[0063] Implementation Process: The complete workflow of this system in an energy monitoring scenario is as follows: First, during the data acquisition phase, the LoRa communication module collects meter current data every 10 seconds, forming a 32×32×8 tensor, which is then directly transmitted to the NPU's data cache unit via the DMA data interface. This operation simultaneously triggers the scheduling module, waking the NPU from its low-power sleep state. Next, the inference calculation phase begins. The NPU's dynamic layout adaptation module uses a preset NHWC layout template to optimize the input data format. The hybrid quantization processing module then quantizes the data to INT8 precision, and a dedicated operator acceleration unit executes the core neural network inference calculation. The entire inference process takes approximately 0.8 milliseconds. Finally, in the result output phase, the calculated "normal" or "abnormal" judgment result is directly transmitted back to the LoRa module via the DMA interface, which then uploads it to the cloud server. Simultaneously, the intelligent collaborative scheduling module controls the NPU to quickly switch back to sleep mode until the next acquisition cycle, thus forming an efficient, low-power closed-loop workflow.
[0064] The low-power NPU chip system and scheduling method for the energy Internet of Things described in the above embodiments address the shortcomings of existing technologies, such as high power consumption, high cost, and low inference efficiency in the edge-side NPU architecture of the energy Internet of Things. This invention solves the pain points of existing technologies in terms of power consumption, compatibility, and inference efficiency through customized microarchitecture design, simplified heterogeneous integration, and intelligent scheduling mechanisms: Significant low-power advantages: The triple low-power design of "dedicated operator acceleration + hybrid quantization + dynamic sleep" results in standby power consumption <1μW and inference power consumption <5mW, significantly reducing power consumption compared to existing general-purpose low-power NPUs (12W level), fully meeting the battery power requirements of edge devices; Strong heterogeneous integration compatibility: The dual-interface (SPI+DMA) architecture and automatic negotiation mechanism are compatible with mainstream MCUs and communication chips, reducing interface area by 90% and adaptation costs by 80%; High inference efficiency: The dedicated operator acceleration unit and hybrid quantization technology are compatible with INT4 / INT8. Hybrid quantization enables TinyML model inference latency to be less than 1ms, which is more than 50% better than the FPGA+MCU solution, and supports dynamic switching of models in multiple scenarios; strong scenario adaptability: the dynamic layout adaptation module is optimized for small data volume scenarios of energy IoT, reducing layout reordering overhead by 90%, further improving energy efficiency ratio, and can be widely used in edge AI scenarios such as smart metering and smart meter reading.
[0065] Obviously, the embodiments described above are merely preferred embodiments of the present invention, and not all embodiments. The accompanying drawings illustrate preferred embodiments of the present invention, but do not limit the scope of the patent. The present invention can be implemented in many different forms; rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this invention.
Claims
1. A low-power NPU chip system for the energy Internet of Things, characterized in that, include: The lightweight computing core is used to perform inference computation of lightweight machine learning models. The lightweight computing core includes a dedicated operator acceleration unit, a hybrid quantization processing module, and a model dynamic loading unit. The dedicated operator acceleration unit is used for depthwise separable convolution, temporal feature extraction, and pooling operations. The hybrid quantization processing module supports dynamic quantization and dequantization processing of mixed precision INT4 and INT8. The model dynamic loading unit is used for dynamic loading and fast switching of TinyML models in multiple scenarios. A simplified heterogeneous interface module is used to realize data interaction between the NPU and the microcontroller and communication chip. The simplified heterogeneous interface module includes a control interface and a data interface. The control interface adopts a simplified serial interface to realize low-latency instruction interaction, and the data interface adopts a direct memory access architecture to realize high-speed data transfer. The intelligent collaborative scheduling module is used to control the working state and resource allocation of the NPU. The intelligent collaborative scheduling module includes a task triggering unit, a state management unit, and a resource allocation unit. The task triggering unit is used to detect inference task requests and trigger the NPU to wake up from the sleep state. The state management unit is used to control the switching between working state and sleep state of each module inside the NPU. The resource allocation unit is used to dynamically adjust the clock frequency according to the task type and coordinate the parallel execution of computing and data transmission. A dynamic layout adaptation module is used to optimize the memory layout of input data. The dynamic layout adaptation module has a pre-built layout template library that stores commonly used tensor memory layout formats. The dynamic layout adaptation module dynamically adjusts the layout parameters according to the actual dimensions of the input data so that the data arrangement order matches the memory access mode of the computing core.
2. The low-power NPU chip system for the energy Internet of Things according to claim 1, characterized in that, The dedicated operator acceleration unit integrates a depthwise separable convolution acceleration circuit, a temporal feature extraction circuit, and a pooling operation circuit, and reduces the number of memory accesses by reusing the weight buffer.
3. A low-power NPU chip system for the energy Internet of Things according to claim 1, characterized in that, The control interface is a 2-wire SPI interface, which connects to the microcontroller and is used to transmit model loading instructions and inference start instructions, with an interface latency of less than 50 nanoseconds; the data interface is a DMA interface, which connects to the microcontroller and the communication chip and is used to achieve direct data transfer with a data transmission rate of not less than 800Mbps and an interaction latency of less than 100 nanoseconds.
4. A low-power NPU chip system for the energy Internet of Things according to claim 3, characterized in that, The simplified heterogeneous interface module also includes an automatic negotiation mechanism for adaptively matching the timing and electrical characteristics of different microcontrollers and communication chips.
5. A low-power NPU chip system for the energy Internet of Things according to claim 1, characterized in that, The state management unit only wakes up the lightweight computing core and the minimalist heterogeneous interface module when the inference task is executed, while the other modules remain in sleep mode; after the task is completed, it controls the NPU to enter sleep mode, so that the static power consumption is less than 1 microwatt.
6. A low-power NPU chip system for the energy Internet of Things according to claim 1, characterized in that, The resource allocation unit increases the NPU clock frequency to 200MHz when performing inference tasks and decreases the clock frequency to 1MHz when idle.
7. A low-power NPU chip system for the energy Internet of Things according to claim 1, characterized in that, The layout template library pre-stores tensor memory layout formats including NHWC and NCHW.
8. A low-power NPU chip system for the energy Internet of Things according to claim 7, characterized in that, The dynamic layout adaptation module also integrates an on-chip cache optimization unit, which is used to implement a tiered storage strategy based on data access frequency.
9. A scheduling method for the system as described in any one of claims 1 to 8, characterized in that, Includes the following steps: S10. The microcontroller sends an initialization command to the NPU through the control interface. The NPU dynamically loads the specified TinyML model from the external memory into the internal model storage unit. After loading is completed, the NPU enters a low-power sleep state. S20: The communication chip receives sensor data and transmits it to the data buffer unit inside the NPU through the data interface. After the data transmission is completed, the intelligent collaborative scheduling module is triggered to wake up the NPU. S30. The dynamic layout adaptation module adjusts the memory layout format of the input data in the cache to adapt it to the memory access mode of the computing core. The lightweight computing core performs inference computation, including quantization processing, accelerated computation by dedicated operators, and fusion of intermediate results; S40. The inference results are transmitted back to the communication chip via the data interface, and the communication chip uploads the results. After the task is completed, the intelligent collaborative scheduling module controls the NPU to switch back to the sleep state, waiting for the next task to be triggered.
10. The scheduling method according to claim 9, characterized in that, The communication chip uses one or more of the following communication methods: LoRa and Wi-Fi.