基于FPGA分阶段串联配置PCIe的超时容错方法、系统和介质
By using a timeout counter and LTSSM status monitoring in a closed-loop control system, real-time perception and automatic fault-tolerant processing of the PCIe link establishment status are achieved. This solves the problem of link establishment failure in the FPGA-based phased serial configuration of PCIe, and improves the system's reliability and self-healing capabilities.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHONGKEXIN MAGNETIC TECH (ZHUHAI) CO LTD
- Filing Date
- 2026-05-18
- Publication Date
- 2026-07-17
AI Technical Summary
Existing FPGA-based phased serial PCIe configuration solutions cannot self-heal when link establishment fails, resulting in poor startup reliability, ineffective dynamic power consumption, and wasted hardware resources, failing to meet the requirements of high-reliability scenarios.
Through closed-loop control with timeout counter and LTSSM status awareness, the PCIe link establishment status can be monitored in real time. If the establishment fails, subsequent bit stream loading will be automatically interrupted. Multi-mode decision logic is used to perform rollback retry, downgrade bit stream switching or terminate configuration.
It improves the system's startup reliability and self-healing capability, avoids invalid dynamic power consumption and abnormal loading, and meets the requirements of high reliability scenarios.
Smart Images
Figure CN122195722B_ABST