Processor power consumption test method and device, electronic equipment, chip and medium

Abstract

The application provides a processor power consumption test method and device, electronic equipment, a chip and a medium, and relates to the technical field of testing. The method comprises the following steps: dividing a calculation unit based on the number of calculation units and the position distribution information of the calculation units in a processor to be tested, to obtain at least one calculation unit group; sequentially activating a calculation unit group to be activated in the at least one calculation unit group based on the activation sequence of the at least one calculation unit group and the real-time power consumption change rate of the calculation unit group after the activation of the activated calculation unit group; and obtaining at least one power consumption index of the processor to be tested under the condition that the at least one calculation unit group is all activated calculation unit groups, to generate a power consumption test report according to the at least one power consumption index. The safe and stable measurement of the full-load power consumption of the processor is realized by the grouping activation mode, the instantaneous current impact and the local hot spot problem are effectively avoided, and the test accuracy is improved.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to a processor power consumption testing method, apparatus, electronic device, chip, and medium. Background Technology

[0002] With the rapid development of artificial intelligence (AI) technology, high-performance processors such as graphics processing units (GPUs) are being deployed on a large scale in data centers, with the thermal design power (TDP) of a single processor chip reaching hundreds to thousands of watts. Accurate measurement of processor power consumption under full load has become a key requirement for data center power planning and thermal design.

[0003] Currently, processor power consumption testing typically employs a global synchronous activation method, activating all computing units at once to measure the processor's full-load power consumption. However, activating all computing units simultaneously generates a sudden surge of high current, which can easily trigger overcurrent protection or cause the processor to throttle, making it impossible to measure the true full-load power consumption. Furthermore, the central area of ​​the processor chip has poor heat dissipation, and simultaneous activation can create localized hotspots, affecting test accuracy and hardware lifespan. Summary of the Invention

[0004] This application provides a processor power consumption testing method, apparatus, electronic device, chip, and medium to solve the problem in related technologies where the instantaneous current surge and local hot spots caused by activating all computing units at once result in the inability to measure the true full-load power consumption.

[0005] The first aspect of this application proposes a processor power consumption testing method, which includes: dividing the computing units into at least one computing unit group based on the number of computing units and the location distribution information of the computing units in the processor under test; sequentially activating the unactivated computing unit groups in the at least one computing unit group based on the activation order of the at least one computing unit group and the real-time power consumption change rate of the activated computing unit groups in the at least one computing unit group; and, when it is determined that the at least one computing unit group is an activated computing unit group, obtaining at least one power consumption index of the processor under test, so as to generate a power consumption test report based on the at least one power consumption index.

[0006] In some embodiments of this application, the computing units are divided based on the number of computing units and the location distribution information of the computing units in the processor under test to obtain at least one group of computing units. Prior to this, the method includes: determining the target processor and initializing the target processor to obtain the processor under test; using a preset query interface to obtain the device attribute information of the processor under test, and determining the number of computing units and location distribution information from the device attribute information.

[0007] In some embodiments of this application, sequentially activating at least one computing unit group to be activated based on the activation order of at least one computing unit group and the real-time power consumption change rate after activation of the activated computing unit group in at least one computing unit group includes: when it is determined that the real-time power consumption change rate is less than or equal to a preset power consumption threshold, activating a first computing unit group based on the activation order of at least one computing unit group and a preset computing load scale to obtain a first activated computing unit group, wherein the first computing unit group is the waiting-to-be-activated computing unit group in at least one computing unit group, and the preset computing load scale is used to indicate the computing task size of the computing units in the first computing unit group; determining a first real-time power consumption change rate of the processor under test after activation of the first activated computing unit group; generating an activation strategy for a second computing unit group based on the first real-time power consumption change rate, so as to activate the second computing unit group according to the activation strategy, wherein the second computing unit group is the computing unit group in at least one computing unit group whose activation order is adjacent to that of the first computing unit group.

[0008] In some embodiments of this application, generating an activation strategy for the second computing unit group based on a first real-time power consumption change rate includes: determining the number of computing units to be activated in the second computing unit group and a preset waiting activation time for the second computing unit group; when the first real-time power consumption change rate is greater than a preset power consumption threshold, updating the number of computing units to be activated and the preset waiting activation time to obtain an updated number of computing units to be activated and an updated waiting activation time, and integrating the updated number of computing units to be activated and the updated waiting activation time to obtain an activation strategy.

[0009] In some embodiments of this application, at least one power consumption indicator includes at least one first power consumption indicator and at least one second power consumption indicator. When it is determined that at least one computing unit group is an activated computing unit group, obtaining at least one power consumption indicator of the processor under test to generate a power consumption test report based on the at least one power consumption indicator includes: when it is determined that at least one computing unit group is an activated computing unit group, obtaining at least one first power consumption indicator corresponding to at least one computing precision at a preset sampling frequency, based on at least one computing precision, wherein the at least one first power consumption indicator includes at least first power consumption data and first temperature data of the processor under test; performing a recovery operation on at least one activated computing unit group sequentially based on the activation order of the at least one computing unit group to obtain at least one second power consumption indicator during the recovery process of the at least one activated computing unit group, wherein the at least one second power consumption indicator includes at least second power consumption data and second temperature data; and generating a power consumption test report based on the first power consumption data, the first temperature data, the second power consumption data, and the second temperature data.

[0010] In some embodiments of this application, generating a power consumption test report based on first power consumption data, first temperature data, second power consumption data, and second temperature data includes: after determining that at least one group of activated computing units has completed the recovery operation, generating a power consumption time series and a temperature time series of the processor under test based on the first power consumption data, first temperature data, second power consumption data, and second temperature data; determining the target power consumption value and the target temperature value corresponding to the target power consumption value of the processor under test based on the power consumption time series and the temperature time series; and integrating the power consumption time series, temperature time series, target power consumption value, and target temperature value to obtain a power consumption test report.

[0011] A second aspect of this application provides a processor power consumption testing apparatus, the apparatus comprising:

[0012] The division unit is used to divide the computing units based on the number of computing units and the location distribution information of the computing units in the processor under test, so as to obtain at least one group of computing units. An activation unit is used to sequentially activate at least one computing unit group to be activated based on the activation order of at least one computing unit group and the real-time power consumption change rate after activation of the activated computing unit group in at least one computing unit group. The acquisition unit is used to acquire at least one power consumption indicator of the processor under test when it is determined that at least one computing unit group is an activated computing unit group, so as to generate a power consumption test report based on the at least one power consumption indicator.

[0013] A third aspect of this application provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of this application.

[0014] A fourth aspect of this application provides a chip including one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of an electronic device and send signals to the processors, the signals including computer instructions stored in the memory, which, when executed by the processors, cause the electronic device to perform the methods described in the first aspect of this application.

[0015] A fifth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the first aspect of this application.

[0016] In summary, the processor power consumption testing method proposed in this application first divides the computing units into at least one computing unit group based on the number and location distribution information of the computing units in the processor under test. Then, it performs ordered group activation by combining the activation order of each computing unit group and the real-time power consumption change rate after activation of the activated computing unit groups. After all computing unit groups have been activated, power consumption indicators are collected and a power consumption test report is generated. This method achieves safe and stable measurement of the processor's full-load power consumption, effectively avoiding the instantaneous current surge and local hotspot problems caused by activating all computing units at once. It also prevents the processor from affecting the test results due to overcurrent protection or frequency reduction, thereby obtaining accurate full-load power consumption data and improving test accuracy.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0019] Figure 1 A flowchart illustrating a processor power consumption testing method provided in this application embodiment; Figure 2 This application provides a schematic diagram of the distribution of a multi-core processor computing unit array. Figure 3 A flowchart illustrating the second processor power consumption testing method provided in this application embodiment; Figure 4 A flowchart illustrating the third processor power consumption testing method provided in this application embodiment; Figure 5 A flowchart illustrating the fourth processor power consumption testing method provided in this application embodiment; Figure 6 A schematic diagram illustrating a specific processor power consumption test process provided in this application embodiment; Figure 7 This is a schematic diagram of the structure of a processor power consumption testing device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; Detailed Implementation The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0020] With the rapid development of generative AI models, the number of AI model parameters has jumped from billions to trillions, leading to an exponential increase in the demand for computing power from high-performance processors such as GPUs. However, with the large-scale deployment of high-performance processors, the TDP of a single processor chip has reached hundreds of watts or even thousands of watts, and the total power consumption of an 8-card server can reach 3.2kW to 10kW. Energy costs have thus increased significantly as a percentage of total data center operating costs. At the same time, stringent reporting requirements for data center energy consumption and carbon emissions have been imposed globally. Therefore, accurately measuring the actual full-load power consumption of processors has become a critical requirement for data center power budget planning, cooling system design, energy configuration, carbon emission accounting, and reliability testing.

[0021] Currently, when testing the full-load power consumption of a processor, related technologies typically activate all computing units of the processor at once, and then measure the power consumption when all computing units are at full load. However, activating all computing units at once can easily cause the processor chip's power supply circuit to be subjected to a huge surge current, which can easily trigger overcurrent protection or even burn out the circuit. It also causes a sudden drop in supply voltage, forcing the processor to reduce its frequency, thus making it impossible to measure the processor's true full-load power consumption. Furthermore, when activating all computing units at once, a large amount of heat quickly accumulates in the central area of ​​the chip due to poor heat dissipation, easily forming localized hotspots. These hotspots can lead to processor frequency reduction, performance degradation, and even shorten the processor chip's lifespan, thus affecting the accuracy of the test.

[0022] To address the aforementioned issues, this application proposes a processor power consumption testing method. Based on the number and location distribution of computing units in the processor under test, the computing units are rationally grouped. Combining the activation order of each computing unit group with the real-time power consumption change rate reported by the activated unit groups, the remaining unactivated computing unit groups are activated sequentially. After all computing unit groups are activated, multiple power consumption indicators of the processor under test are collected, and a complete power consumption test report is generated based on the collected data. This method achieves safe and stable loading of the processor's computing units, effectively avoiding instantaneous current surges and localized hotspots, ensuring stable processor operation, reducing hardware damage, and effectively improving the accuracy and reliability of full-load power consumption test results.

[0023] The processor power consumption test method provided in this application will be described in detail below with reference to the accompanying drawings.

[0024] Figure 1 This is a flowchart illustrating a processor power consumption testing method provided in an embodiment of this application. Figure 1 As shown, the processor power consumption test method includes steps 101-103.

[0025] Step 101: Based on the number of computing units and the location distribution information of computing units in the processor under test, the computing units are divided to obtain at least one group of computing units.

[0026] In the embodiments of this application, the processor under test includes, but is not limited to, processor chips with arrayed multi-core structures such as GPUs, Field-Programmable Gate Arrays (FPGAs), and array-arranged multi-core AI chips. The processor under test integrates multiple computing units, which are arranged in a regular array in physical space, with differences in heat dissipation between the edge and center regions.

[0027] The computing unit is a basic, independently schedulable, array-arranged computational module within the processor under test. For example, in a GPU, it is a Streaming Multiprocessor (SM); in an FPGA, it is a Configurable Logic Block (CLB); and in an array-type AI chip, it is a tile. This application does not limit the scope of the embodiments. This application uses the SM in a GPU as an example to describe the processor power consumption testing method in detail.

[0028] The grouping principle of computing units in this application is as follows: based on the physical topology of the computing units (i.e., the spatial distribution of computing units on the chip), the computing units are divided according to differences in heat dissipation conditions. The computing units are divided in an alternating manner, so that the computing units within the same activation batch are distributed on the chip rather than continuously clustered. Furthermore, the activation order is priority for edge regions followed by the center region, thereby achieving uniform heat distribution and avoiding localized hotspots during the activation process. For example, such as... Figure 2 The diagram shows a distribution of a multi-core processor computing unit array, according to... Figure 2 The calculation units are grouped by the batch number (1-2-3-4-5).

[0029] The number of computing units contained in each computing unit group after grouping in this application may be the same or different, may be increased or decreased in batches, or may be dynamically adjusted according to the real-time power change rate. This is not limited in the embodiments of this application.

[0030] Step 102: Based on the activation order of at least one computing unit group and the real-time power consumption change rate of the activated computing unit group in at least one computing unit group after activation, activate the computing unit group to be activated in at least one computing unit group in sequence.

[0031] In the embodiments of this application, activating the computing unit group means enabling each computing unit in the computing unit group to enter the working state from the idle state, such as assigning computing tasks (such as matrix multiplication operations) to the SM in the GPU, or applying trigger toggling operations to the CLB in the FPGA.

[0032] The activation order refers to the order in which each group of computing units is activated, following the principle of activating the edge groups first and then the center groups.

[0033] Real-time power consumption change rate refers to the rate of change (dp / dt) of the total power consumption of the processor under test over time after activating a set of computing units. It is used to determine whether the current processor is powered on and loaded smoothly.

[0034] Optionally, during the group activation process, this application first presets a certain waiting activation time for each computing unit group (e.g., the initial waiting activation time for each group is 5 seconds). Simultaneously, during the group activation process of each computing unit group, the real-time power consumption change rate of the processor under test is monitored throughout. When the real-time power consumption change rate is normal (e.g., below the preset power consumption threshold), the computing unit groups to be activated are activated sequentially according to the activation order. When the real-time power consumption change rate is too high (e.g., exceeding the preset power consumption threshold), the activation rate of the next group is slowed down, for example, by extending the waiting activation time of the next group or reducing the number of computing units to be activated in the next group.

[0035] By using the above method, all computing unit groups to be activated are activated sequentially until all computing unit groups are activated.

[0036] Step 103: If at least one computing unit group is determined to be an activated computing unit group, at least one power consumption index of the processor under test is obtained, so as to generate a power consumption test report based on at least one power consumption index.

[0037] In the embodiments of this application, with all computing units activated, each computing unit is made to work continuously for a certain period of time (e.g., 10 minutes) to allow the processor under test to reach and maintain a stable full-load state. During this period, at least one power consumption indicator of the processor under test is continuously collected through a monitoring interface (e.g., the GPU's NVML (NVIDIA Management Library)) at a preset sampling frequency (e.g., once every 500ms). Afterward, all activated unit groups are cooled and restored (i.e., each computing unit is gradually restored to an idle state). During the restoration process, various power consumption indicators of the processor under test are continuously monitored (e.g., the temperature recovery curve and fan speed reduction curve of the processor under test are continuously monitored) until the processor returns to an idle state.

[0038] Among them, at least one power consumption indicator includes data such as power consumption, temperature, frequency, and fan speed of the processor under test during the activation of the computing unit.

[0039] Based on the data collected during the full load phase (i.e., all computing units are in an active state) (power consumption, temperature, etc.) and the cooling recovery phase (power consumption decay characteristics, temperature recovery curve, etc.), a complete power consumption test report is generated. The report includes, but is not limited to: power consumption time series, temperature time series, maximum power consumption value and its corresponding temperature for each phase.

[0040] Optionally, this application can also perform synchronous tests on multiple processors, including comparative experiments on local computing and cross-processor communication. Specifically, the test progress of multiple processors is synchronized through a communication library (such as NCCL (NVIDIA Collective Communications Library)), and the above-mentioned group activation, full-load testing, and cooling recovery processes are executed in parallel. During the test, power consumption and temperature data of each processor are collected independently to analyze the power consumption balance and temperature distribution characteristics across processors. In addition, comparative tests of local computing (each processor independently executes computing tasks) and cross-processor communication can be performed to evaluate the impact of communication operations on power consumption.

[0041] In summary, the processor power consumption testing method proposed in this application first divides the computing units into at least one computing unit group based on the number and location distribution information of the computing units in the processor under test. Then, combining the activation order of each computing unit group and the real-time power consumption change rate after activation, orderly group activation is performed. After all computing unit groups are activated, power consumption indicators are collected and a power consumption test report is generated. This method achieves safe and stable measurement of the processor's full-load power consumption, effectively avoiding the instantaneous current surge and local hotspots caused by activating all computing units at once. It also prevents the processor from affecting the test results due to overcurrent protection or frequency reduction, thereby obtaining accurate full-load power consumption data and improving test accuracy.

[0042] As one possible implementation method, Figure 3 A flowchart of a second processor power consumption testing method provided in an embodiment of this application is shown. Based on the above embodiments, before dividing the computing units into at least one group based on the number and location distribution information of the computing units in the processor under test, the method includes the following steps: Step 201: Determine the target processor and initialize it to obtain the processor under test.

[0043] In the embodiments of this application, the target processor is the original hardware device to be tested for power consumption, which may be in an unknown state (e.g., with residual unfinished computing tasks, in a downclocked or sleep mode, etc.). By performing a series of operations to initialize the target processor, such as resetting, clearing residual computing context, and allocating resources required for testing, it is brought into a definite, idle initial state. After initialization, a processor under test that can be tested under full load power consumption is obtained.

[0044] Specifically, this application uses a GPU as the processor under test and an SM as the computing unit for illustration. First, the target GPU device is selected by calling cudaSetDevice(), and cudaDeviceReset() is called to restore the GPU to its initial state, clearing any residual computing context (such as unfinished kernel programs, error states, etc.) and putting the GPU in an idle and reconfigurable standard state.

[0045] Next, the GEMM (General Matrix Multiplication, in the form C=α×A×B+β×C, is the core computational operation in deep learning and high-performance computing) workload engine calls cublasCreate() to create a cuBLAS handle, and calls the mathematical mode configuration interface to enable the Tensor core (a dedicated hardware computing unit integrated inside SM, specifically used to accelerate matrix multiplication and addition operations, and is the core source of computing power for AI computing) computing mode, ensuring that subsequent GEMM operations are executed by the Tensor core.

[0046] Then, the GEMM load engine allocates storage space for matrices A, B, and C in GPU memory (pre-allocating the memory space required for the largest possible matrix). Matrix A and B are then padded with data, specifically by filling them with a specific non-zero, non-sparse data pattern. Specifically, a pseudo-random number generator is used to generate uniformly distributed non-zero floating-point numbers to fill the matrix elements, ensuring that the matrix data does not trigger the sparsity acceleration path of the Tensor core, thus keeping the Tensor core always at full load.

[0047] Finally, the NVML library is initialized by calling nvmlInit(), which allows for continuous monitoring of power consumption, temperature, and other metrics.

[0048] Through the above initialization operations, the target processor is configured as a GPU under test (processor under test) in a known idle state, with full monitoring and load generation capabilities.

[0049] Step 202: Use a preset query interface to obtain the device attribute information of the processor under test, and determine the number and location distribution information of computing units from the device attribute information.

[0050] In the embodiments of this application, the preset query interface is a standard software interface used to read processor hardware attributes. Device attribute information includes hardware parameters such as processor model, total number of computing units, processor architecture version, maximum number of threads / blocks supported per computing unit, and video memory capacity.

[0051] Specifically, this application queries the device properties of the GPU under test by calling a preset query interface (such as the cudaGetDeviceProperties() function) to obtain the following key parameters of the GPU: number of compute units (obtained through the multiProcessorCount field to get the total number of SMs), GPU architecture version (Compute Capability), auxiliary parameters (including maximum number of threads per SM (maxThreadsPerMultiProcessor), maximum number of blocks per SM (maxBlocksPerMultiProcessor), global memory capacity (totalGlobalMem), etc., used for the configuration of the GEMM load engine).

[0052] Based on the key parameters obtained above, especially the total number of computing units and the architecture version, the number of SMs and the relative physical location of each SM on the processor can be determined, thereby obtaining location distribution information (e.g., which SMs are located in the edge region and which are located in the center region).

[0053] In summary, this application first identifies and initializes the target processor, and then uses a preset query interface to obtain the number and location distribution information of computing units. This provides an accurate data foundation for the subsequent physical topology-based group activation strategy, ensuring that the group division can reflect the difference in heat dissipation between the edge and the center, thereby achieving safe and stable full-load power consumption testing.

[0054] As one possible implementation method, Figure 4 A flowchart of a third processor power consumption testing method provided in an embodiment of this application is shown. Based on the above embodiments, and based on the activation order of at least one computing unit group and the real-time power consumption change rate of the activated computing unit groups in at least one computing unit group after activation, the method sequentially activates the computing unit groups to be activated in at least one computing unit group, including the following steps: Step 301: If the real-time power consumption change rate is less than or equal to the preset power consumption threshold, the first computing unit group is activated based on the activation order of at least one computing unit group and the preset computing load scale, thus obtaining the first activated computing unit group.

[0055] In the embodiments of this application, the real-time power consumption change rate is the rate of change of the total power consumption of the processor under test over time after each set of computing units is activated. The preset power consumption threshold is a pre-set upper limit for the safe power consumption change rate; exceeding this value may trigger power supply protection. The preset computing load scale is used to indicate the size of the computing task of the computing unit, i.e., the complexity of the computing task (for example, for a GPU, the preset computing load scale can be the matrix order N of matrix multiplication operations, such as N=1024 / 4096 / 8192 / 16384).

[0056] Optionally, this application performs a warm-up phase before group activation. Specifically, by configuring the parallel granularity of the computing tasks (e.g., starting a small number of thread blocks), the computing tasks are allocated to only a small number of computing units for execution. That is, a small number of computing units (e.g., 2-4 SMs) are started to perform small-scale computing tasks (e.g., GEMM operations with N=1024), causing the clock frequency of the processor under test to climb from the idle frequency to the operating frequency, and the power supply circuit to switch from light-load mode to normal operating mode. At the same time, power consumption, temperature, and other data are collected at a preset sampling frequency (e.g., 500ms), and the real-time power consumption change rate of the processor under test is determined. The warm-up phase lasts for a certain period of time (e.g., several seconds to tens of seconds) before proceeding to the formal group activation process.

[0057] After warm-up, the formal activation phase begins. Specifically, when the real-time power consumption change rate of the processor under test is less than or equal to a preset power consumption threshold, the next computing unit group to be activated is selected as the first computing unit group according to the activation order. Based on a preset computational load scale (e.g., initial matrix size N=1024), a load engine is configured, and computational tasks are assigned to the computing units in the first computing unit group to activate that group. It should be noted that the computational load scale within the first computing unit group is gradually increased in a gradient manner (e.g., the matrix size N gradually increases from 1024 to 16384), that is, the load intensity of each computing unit in the first computing unit group is gradually increased so that each computing unit in the first computing unit group gradually reaches a full-load state.

[0058] Optionally, if the first computing unit group is the first computing unit group, the first computing unit group is activated based on a preset computing load scale; if the first computing unit group is not the first computing unit group, the real-time power consumption change rate after the activation of the previously activated computing unit group is determined; if the real-time power consumption change rate is less than or equal to a preset power consumption threshold, the first computing unit group is activated based on a preset computing load scale; if the real-time power consumption change rate is greater than the preset power consumption threshold, the activation strategy of the first computing unit group is adjusted to activate the first computing unit group according to the activation strategy, wherein the activation strategy includes updating the preset waiting activation time of the first computing unit group and the number of computing units in the first computing unit group.

[0059] Step 302: Determine the first real-time power consumption change rate of the processor under test after the first activated computing unit group is activated.

[0060] In the embodiments of this application, the first real-time power consumption change rate is the rate at which the total power consumption of the processor under test changes over time after the first computing unit group is activated.

[0061] In one example, taking a GPU as an example, after activating the first computing unit group in step 301, the power consumption data of the processor under test is continuously collected through the NVML interface at a preset time interval (e.g., 500ms). The power consumption values ​​at at least two time points are collected (to ensure accuracy, the power consumption values ​​at multiple consecutive time points can also be collected and averaged), the power consumption difference is calculated, and divided by the time interval to obtain the first real-time power consumption change rate.

[0062] Step 303: Based on the first real-time power consumption change rate, generate an activation strategy for the second computing unit group, and activate the second computing unit group according to the activation strategy.

[0063] In embodiments of this application, the second computing unit group is the next computing unit group to be activated in the activation order of at least one computing unit group that is adjacent to the first computing unit group. The activation strategy is a set of parameters that determine how to activate the next group of computing units, including the waiting activation duration and the number of computing units activated in a single group. The waiting activation duration refers to the interval between the activation of two groups. This application generates different activation strategies for the second computing unit group based on the comparison result of the first real-time power consumption change rate and a preset power consumption threshold. Specifically: If the first real-time power consumption change rate is less than or equal to the preset power consumption threshold, it indicates that the activation process of the current computing unit group (i.e., the first computing unit group) is stable. Then, the original activation strategy is maintained, that is, the second computing unit group is activated according to the preset waiting activation time (e.g., 5 seconds) and the preset number of single-group activations (i.e., the number of computing units to be activated in the second computing unit group).

[0064] If the first real-time power consumption change rate is greater than the preset power consumption threshold, it indicates that there is a risk of current surge during the activation process of the current computing unit group (i.e., the first computing unit group). Therefore, the activation strategy for the next computing unit group (i.e., the second computing unit group) is adjusted, i.e., the activation waiting time is increased (e.g., from 5 seconds to 10 seconds), and / or the number of computing units to be activated in the second computing unit group is reduced (e.g., from 6 to 4). The adjusted parameters (including the updated number of computing units to be activated and the updated activation waiting time) constitute a new activation strategy, and the activation operation for the second computing unit group is performed according to this activation strategy.

[0065] Repeat the above process until all computing unit groups are activated.

[0066] In summary, this application achieves adaptive adjustment of the activation process of the computing unit group according to the real-time power consumption change rate by setting a feedback control mechanism based on the real-time power consumption change rate. That is, it maintains a normal activation rhythm when the activation is stable, and automatically slows down the activation rate when the risk of current surge is detected, thereby effectively avoiding the problems of instantaneous large current surge and local hot spots, and ensuring that the processor can safely and smoothly reach the true full load state.

[0067] As one possible implementation method, Figure 5 A flowchart of a fourth processor power consumption testing method provided in this application embodiment is shown. Based on the above embodiments, at least one power consumption indicator includes at least one first power consumption indicator and at least one second power consumption indicator. When it is determined that at least one computing unit group is an activated computing unit group, at least one power consumption indicator of the processor under test is obtained to generate a power consumption test report based on the at least one power consumption indicator, including the following steps: Step 401: If it is determined that at least one computing unit group is an activated computing unit group, at least one first power consumption index corresponding to at least one computing precision is obtained at a preset sampling frequency based on at least one computing precision. The at least one first power consumption index includes at least the first power consumption data and the first temperature data of the processor under test.

[0068] In the embodiments of this application, the calculation precision refers to the data format used by the processor under test when performing calculations, such as FP64, FP32, TF32, FP16, BF16, FP8, INT8, etc. The power consumption of the processor under test is different under different precisions.

[0069] The first power consumption metric refers to the raw data collected during the full-load phase (i.e., when all computing units are active), including power consumption data and temperature data.

[0070] After all computing unit groups have been activated (i.e., all computing units are in a working state), the processor under test enters the steady-state full-load stage. At this time, all computing units continue to execute computing tasks (such as large-scale computational load (N=16384) GEMM). This application supports multi-precision power consumption testing. Specifically, under full load, different computing precisions are switched sequentially (e.g., from FP16 to FP8, then to FP32, etc.). At each precision, power consumption data (i.e., first power consumption data) and temperature data (i.e., first temperature data) of the processor under test are continuously collected at a preset sampling frequency (e.g., 500ms) for a certain duration (e.g., 10 minutes). The first power consumption data and first temperature data of the full-load stage are obtained.

[0071] Step 402: Based on the activation order of at least one computing unit group, perform a recovery operation on at least one activated computing unit group in sequence to obtain at least one second power consumption index during the recovery process of at least one activated computing unit group. The at least one second power consumption index includes at least second power consumption data and second temperature data.

[0072] In the embodiments of this application, performing a recovery operation on at least one activated computing unit group refers to sequentially stopping the computing tasks in at least one activated computing unit group in reverse order (i.e., restoring the central region first, then the edge regions) according to the activation order, so that the processor under test gradually returns from a fully loaded state to an idle state. The recovery operation includes stopping the submission of new computing tasks, synchronously waiting for all tasks to complete, and natural cooling.

[0073] Specifically, after completing data acquisition during the full-load phase, this application performs a recovery operation. First, it stops submitting new computational tasks (e.g., exiting the GEMM loop). Then, it calls a synchronization function (such as cudaDeviceSynchronize() in a GPU) to wait for all submitted computational tasks on the processor under test to complete. During this synchronization, it continues to collect power consumption data (i.e., second power consumption data) at a preset sampling frequency (e.g., 500ms), recording the decay process from peak power consumption to idle power consumption. After synchronization is complete, all computational loads are stopped. At this point, the processor under test is in a task-free state, relying solely on the cooling system for natural cooling. During this cooling recovery phase, it continuously monitors the temperature data (i.e., second temperature data) and fan speed data of the processor under test until the temperature drops to near ambient temperature and the fan speed returns to idle levels.

[0074] Step 403: Generate a power consumption test report based on the first power consumption data, the first temperature data, the second power consumption data, and the second temperature data.

[0075] In the embodiments of this application, a power consumption test report is generated by summarizing and analyzing the data collected at each stage (full load stage, recovery stage) to evaluate the processor's full load power consumption characteristics and heat dissipation performance.

[0076] Optionally, generating a power consumption test report based on the first power consumption data, the first temperature data, the second power consumption data, and the second temperature data includes: after determining that at least one group of activated computing units has completed the recovery operation, generating a power consumption time series and a temperature time series of the processor under test based on the first power consumption data, the first temperature data, the second power consumption data, and the second temperature data; determining the target power consumption value and the target temperature value corresponding to the target power consumption value of the processor under test based on the power consumption time series and the temperature time series; and integrating the power consumption time series, the temperature time series, the target power consumption value, and the target temperature value to obtain a power consumption test report.

[0077] In the embodiments of this application, firstly, the first power consumption data, the first temperature data, the second power consumption data, and the second temperature data are arranged according to the sampling time to generate a power consumption time series and a temperature time series, respectively. Then, the target power consumption value (i.e., the peak power consumption during the entire power consumption test) is extracted from the power consumption time series. Simultaneously, the temperature value corresponding to the peak power consumption moment is extracted from the temperature time series as the target temperature value. Finally, the power consumption time series, the temperature time series, the target power consumption value, and the target temperature value are integrated to form a complete power consumption test report.

[0078] In summary, this application collects multi-dimensional data, including power consumption and temperature, during both the processor's full-load and cooling recovery phases, and integrates this data to generate a complete test report containing power consumption time series, temperature time series, peak power consumption, and corresponding temperatures. This report comprehensively reflects the processor's power consumption characteristics and heat dissipation performance under full-load conditions, providing accurate and reproducible data for data center power planning, thermal design, and chip reliability assessment.

[0079] Furthermore, to facilitate better understanding, this application provides a schematic diagram of a specific processor power consumption test process. For example... Figure 6 As shown, this application takes a GPU as the processor under test as an example. The overall process of power consumption testing of this processor includes six stages: initialization, warm-up, gradual full load, full core full load, synchronization, and cooling recovery.

[0080] Reference Figure 6 After the test process begins, it is first determined whether multi-card (i.e., multiple processors under test) collaborative testing needs to be performed. If not (i.e., single-card testing), the CUDA (Compute Unified Device Architecture) environment initialization of a single card is performed (corresponding to the initialization of the target processor in this application); if multi-card collaboration is required, the CUDA environment initialization of multiple cards is performed, including establishing a multi-card synchronization mechanism through a communication library.

[0081] After environment initialization is complete, the warm-up phase begins. This phase involves starting a small number of computing units (such as some SMs in a GPU) to perform small-scale computing tasks (such as small-scale GEMMs), gradually increasing the processor clock frequency from the idle frequency to the operating frequency, while simultaneously monitoring power consumption, temperature, and other indicators at a preset sampling frequency.

[0082] After the warm-up phase, the system enters the ramp-up phase. This phase groups computing units based on their physical topology (i.e., location distribution information), prioritizing activation of units at the processor chip's edge regions, followed by the central regions, and activating each group of computing units in batches. During activation, the real-time power consumption rate of the processor under test is monitored. If the real-time power consumption rate exceeds a preset power consumption threshold, the activation strategy for subsequent batches is dynamically adjusted (e.g., extending the activation wait time, reducing the number of computing units activated in a single batch). Simultaneously, the load intensity within each batch of computing units increases in a gradient manner until all computing units are activated.

[0083] The test then enters the Full Load phase, where all computing units are activated and the processor is in a steady-state full-load state. All computing units are continuously and repeatedly executed with the largest possible computational task, and power consumption, temperature, and other data are continuously collected at a fixed frequency (e.g., 500ms), with the duration adjustable as needed (e.g., 10 minutes). Simultaneously, multi-precision energy efficiency traversal can be performed during this phase, sequentially switching between different computational precisions and collecting power consumption and other data at each precision level.

[0084] After the full load test is completed, the cudaDeviceSynchronize synchronization phase begins. Submitting new computation tasks stops, and a synchronization function (such as cudaDeviceSynchronize()) is called to wait for all submitted computation tasks on the processor to complete. During this period, the decay characteristics of power consumption from peak to idle value are recorded.

[0085] Finally, the Cooldown recovery phase begins. All computing loads are stopped, and the temperature recovery curve and fan speed reduction curve of the processor under test are continuously monitored until the processor under test returns to an idle state. The power consumption time series, temperature time series, maximum power consumption value, and corresponding temperature collected in the above stages are integrated to generate a complete power consumption test report.

[0086] Figure 7 This is a schematic diagram of a processor power consumption testing device 500 provided in an embodiment of this application. Figure 7 As shown, the processor power consumption testing device includes: The partitioning unit 510 is used to partition the computing units based on the number of computing units and the location distribution information of the computing units in the processor under test, so as to obtain at least one group of computing units. The activation unit 520 is used to sequentially activate at least one computing unit group to be activated based on the activation order of at least one computing unit group and the real-time power consumption change rate after the activation of the activated computing unit group in at least one computing unit group. The acquisition unit 530 is used to acquire at least one power consumption indicator of the processor under test when it is determined that at least one computing unit group is an activated computing unit group, so as to generate a power consumption test report based on the at least one power consumption indicator.

[0087] In some embodiments of this application, the device includes: a determining unit, configured to divide the computing units into at least one computing unit group based on the number of computing units and the location distribution information of the computing units in the processor under test; prior to this, a target processor is determined and initialized to obtain the processor under test; and the device attribute information of the processor under test is obtained using a preset query interface, and the number and location distribution information of the computing units are determined from the device attribute information.

[0088] In some embodiments of this application, the activation unit 520 is configured to: when it is determined that the real-time power consumption change rate is less than or equal to a preset power consumption threshold, activate a first computing unit group based on the activation order of at least one computing unit group and a preset computing load scale to obtain a first activated computing unit group, wherein the first computing unit group is a waiting-to-be-activated computing unit group among at least one computing unit group, and the preset computing load scale is used to indicate the computing task size of the computing units in the first computing unit group; determine a first real-time power consumption change rate of the processor under test after the first activated computing unit group is activated; and generate an activation strategy for a second computing unit group based on the first real-time power consumption change rate, so as to activate the second computing unit group according to the activation strategy, wherein the second computing unit group is a computing unit group among at least one computing unit group whose activation order is adjacent to that of the first computing unit group.

[0089] In some embodiments of this application, the activation unit 520 is configured to: determine the number of computing units to be activated in the second computing unit group and the preset waiting activation time of the second computing unit group; when the first real-time power consumption change rate is greater than the preset power consumption threshold, update the number of computing units to be activated and the preset waiting activation time to obtain the updated number of computing units to be activated and the updated waiting activation time, and integrate the updated number of computing units to be activated and the updated waiting activation time to obtain the activation strategy.

[0090] In some embodiments of this application, at least one power consumption indicator includes at least one first power consumption indicator and at least one second power consumption indicator. The acquisition unit 530 is configured to: when it is determined that at least one computing unit group is an activated computing unit group, acquire at least one first power consumption indicator corresponding to at least one computing precision at a preset acquisition frequency based on at least one computing precision, wherein the at least one first power consumption indicator includes at least first power consumption data and first temperature data of the processor under test; perform a recovery operation on at least one activated computing unit group sequentially based on the activation order of at least one computing unit group to acquire at least one second power consumption indicator during the recovery process of at least one activated computing unit group, wherein the at least one second power consumption indicator includes at least second power consumption data and second temperature data; and generate a power consumption test report based on the first power consumption data, the first temperature data, the second power consumption data, and the second temperature data.

[0091] In some embodiments of this application, the acquisition unit 530 is configured to: generate a power consumption time series and a temperature time series of the processor under test based on first power consumption data, first temperature data, second power consumption data, and second temperature data, after determining that at least one group of activated computing units has completed the recovery operation; determine the target power consumption value and the target temperature value corresponding to the target power consumption value of the processor under test based on the power consumption time series and the temperature time series; and integrate the power consumption time series, the temperature time series, the target power consumption value, and the target temperature value to obtain a power consumption test report.

[0092] Since the apparatus provided in this application corresponds to the methods provided in the above-mentioned embodiments, the implementation of the methods is also applicable to the apparatus provided in this embodiment, and will not be described in detail in this embodiment.

[0093] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.

[0094] Figure 8 This is a block diagram illustrating an electronic device 600 for implementing the above-described processor power consumption testing method according to an exemplary embodiment. (Refer to...) Figure 8The electronic device 600 may include a communication interface 601, capable of interacting with other devices; a processor 602, connected to the communication interface 601 to interact with other devices and used to execute the methods provided by one or more of the above-mentioned technical solutions when running a computer program; and a memory 603, on which the computer program is stored. Specifically, the specific processing procedure of the processor 602 can refer to the processor power consumption test method described in the above embodiments of this application.

[0095] Of course, in practical applications, the various components in electronic device 600 are coupled together through bus system 604. It can be understood that bus system 604 is used to realize the connection and communication between these components. In addition to a data bus, bus system 604 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, in... Figure 8 The general designated all buses as Bus System 604.

[0096] The memory 603 in this embodiment is used to store various types of data to support the operation of the electronic device 600. Examples of such data include any computer program used to operate on the electronic device 600.

[0097] The methods disclosed in the embodiments of this application can be applied to processor 602, or implemented by processor 602. Processor 602 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 602 or by instructions in the form of software. The processor 602 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 602 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 603. Processor 602 reads the information in memory 603 and combines it with its hardware to complete the steps of the aforementioned method.

[0098] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned method.

[0099] Embodiments of this application also propose a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the processor power consumption testing method described in the above embodiments of this application.

[0100] Embodiments of this application also propose a computer program product, including a computer program, which is executed by a processor using the processor power consumption testing method described in the above embodiments of this application.

[0101] Embodiments of this application also propose a chip including one or more interface circuits and one or more processors; the interface circuits are used to receive signals from the memory of an electronic device and send signals to the processors, the signals including computer instructions stored in the memory, and when the processor executes the computer instructions, the electronic device performs the processor power consumption test method described in the above embodiments of this application.

[0102] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0103] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0104] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0105] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0106] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0107] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0108] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0109] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for testing processor power consumption, characterized in that, The method includes: Based on the number of computing units and the location distribution information of the computing units in the processor under test, the computing units are divided to obtain at least one group of computing units; Based on the activation order of the at least one computing unit group and the real-time power consumption change rate after activation of the activated computing unit group in the at least one computing unit group, the computing unit groups to be activated in the at least one computing unit group are activated sequentially; wherein, the real-time power consumption change rate is the rate of change of the total power consumption of the processor under test over time after each set of computing units is activated. When it is determined that all at least one computing unit group is an activated computing unit group, at least one power consumption index of the processor under test is obtained to generate a power consumption test report based on the at least one power consumption index; wherein, the at least one power consumption index includes at least one first power consumption index and at least one second power consumption index; the at least one first power consumption index includes at least one first power consumption data and one first temperature data of the processor under test, and the at least one second power consumption index includes at least one second power consumption data and one second temperature data; Wherein, when it is determined that all at least one computing unit group is an activated computing unit group, obtaining at least one power consumption indicator of the processor under test, and generating a power consumption test report based on the at least one power consumption indicator, includes: If it is determined that all at least one computing unit group is an activated computing unit group, the at least one first power consumption index corresponding to the at least one computing precision is obtained at a preset sampling frequency based on at least one computing precision. Based on the activation order of the at least one computing unit group, a recovery operation is performed on at least one of the activated computing unit groups in sequence to obtain the at least one second power consumption index during the recovery process of the at least one activated computing unit group. The power consumption test report is generated based on the first power consumption data, the first temperature data, the second power consumption data, and the second temperature data.

2. The method according to claim 1, characterized in that, The method involves dividing the computing units based on the number of computing units and their location distribution information in the processor under test to obtain at least one group of computing units. Prior to this, the method includes: The target processor is determined and initialized to obtain the processor under test; Using a preset query interface, the device attribute information of the processor under test is obtained, and the number of computing units and the location distribution information are determined from the device attribute information.

3. The method according to claim 1, characterized in that, The step of sequentially activating the unactivated computing unit groups in the at least one computing unit group based on the activation order of the at least one computing unit group and the real-time power consumption change rate after activation of the activated computing unit groups in the at least one computing unit group includes: When the real-time power consumption change rate is determined to be less than or equal to a preset power consumption threshold, the first computing unit group is activated based on the activation order of the at least one computing unit group and the preset computing load scale, to obtain the first activated computing unit group. The first computing unit group is the waiting-to-be-activated computing unit group among the at least one computing unit group. The preset computing load scale is used to indicate the computing task size of the computing units in the first computing unit group. Determine the first real-time power consumption change rate of the processor under test after the first activated computing unit group is activated; Based on the first real-time power consumption change rate, an activation strategy for the second computing unit group is generated to activate the second computing unit group according to the activation strategy. The second computing unit group is the computing unit group whose activation order is adjacent to the first computing unit group among the at least one computing unit group.

4. The method according to claim 3, characterized in that, The activation strategy for generating the second computing unit group based on the first real-time power consumption change rate includes: Determine the number of computing units to be activated in the second computing unit group and the preset activation waiting time for the second computing unit group; When the first real-time power consumption change rate is greater than the preset power consumption threshold, the number of computing units to be activated and the preset waiting time for activation are updated to obtain the updated number of computing units to be activated and the updated waiting time for activation. The updated number of computing units to be activated and the updated waiting time for activation are then integrated to obtain the activation strategy.

5. The method according to claim 1, characterized in that, The process of generating the power consumption test report based on the first power consumption data, the first temperature data, the second power consumption data, and the second temperature data includes: If it is determined that at least one of the activated computing unit groups has completed the recovery operation, the power consumption time series and temperature time series of the processor under test are generated based on the first power consumption data, the first temperature data, the second power consumption data and the second temperature data. Based on the power consumption time series and the temperature time series, the target power consumption value of the processor under test and the target temperature value corresponding to the target power consumption value are determined; The power consumption time series, the temperature time series, the target power consumption value, and the target temperature value are integrated to obtain the power consumption test report.

6. A processor power consumption testing device, characterized in that, The device includes: A partitioning unit is used to partition the computing units based on the number of computing units in the processor under test and the location distribution information of the computing units, to obtain at least one group of computing units. An activation unit is configured to sequentially activate the at least one computing unit group to be activated based on the activation order of the at least one computing unit group and the real-time power consumption change rate after the activated computing unit group in the at least one computing unit group is activated; wherein, the real-time power consumption change rate is the rate of change of the total power consumption of the processor under test over time after each group of computing units is activated. An acquisition unit is configured to acquire at least one power consumption indicator of the processor under test when it is determined that all at least one computing unit group is an activated computing unit group, so as to generate a power consumption test report based on the at least one power consumption indicator; wherein, the at least one power consumption indicator includes at least one first power consumption indicator and at least one second power consumption indicator; the at least one first power consumption indicator includes at least one first power consumption data and one first temperature data of the processor under test, and the at least one second power consumption indicator includes at least one second power consumption data and one second temperature data; The acquisition unit is further configured to, when determining that all at least one computing unit group is an activated computing unit group, acquire at least one first power consumption index corresponding to the at least one computing precision at a preset acquisition frequency based on at least one computing precision; perform a recovery operation on at least one activated computing unit group sequentially based on the activation order of the at least one computing unit group to acquire at least one second power consumption index during the recovery process of at least one activated computing unit group; and generate the power consumption test report based on the first power consumption data, the first temperature data, the second power consumption data, and the second temperature data.

7. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

8. A chip, characterized in that, The device includes one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of the electronic device and send the signals to the processors, the signals including computer instructions stored in the memory, which, when executed by the processors, cause the electronic device to perform the method of any one of claims 1-5.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-5.

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