An MCU chip register access method, system and storage medium

Abstract

This invention provides a method, system, and storage medium for accessing registers without an MCU chip. It is applied between a master control chip and a slave chip without an MCU, enabling in-band management through a shared high-speed data interface. Specifically, after receiving the data stream, the identifier is parsed and compared with a preset value to separate management messages. The messages undergo structural verification, sequentially verifying the compliance of the structural feature set. After passing structural verification, operation fields are extracted for operation verification. Once the operation verification passes, it is converted into an internal bus transaction for register access, and the completion status is monitored. Finally, based on the operation result, a success response or a tiered error response is sent back to the master control chip. This achieves multi-layered chain verification and direct register operation, balancing high bandwidth, low latency configuration efficiency, and strong security access control without requiring an independent management interface and MCU, while reducing chip cost and transmission system complexity.

Description

Technical Field

[0001] This invention relates to the field of network communication, and more specifically, to a method, system, and storage medium for accessing registers without an MCU chip. Background Technology

[0002] As network communication and embedded systems develop towards higher speeds and greater integration, in multi-chip network devices (such as PON-OLT, data center switches, and vehicle gateways), the efficient and reliable register configuration and management of dedicated data plane chips without microcontrollers (MCUs) by the main control chip has always been a key technical challenge.

[0003] First, existing solutions using independent management buses (such as I2C and SPI) require additional dedicated pins and PCB traces, increasing hardware costs and layout complexity. Furthermore, their lower bandwidth and higher latency make them unsuitable for the frequent, high-volume configuration needs of high-speed chips. Additionally, low-speed signals are susceptible to interference in complex electromagnetic environments, affecting management reliability. Second, current solutions based on standard in-band management protocols (such as Ethernet OAM and PON OMCI), while reusing data channels and avoiding independent interfaces, rely on software protocol stacks for message parsing and object model mapping. This makes them unsuitable for data plane chips without MCUs and operating systems. Moreover, their operations target abstract Management Information Base (MIB) or Management Entity (ME) attributes, rather than directly accessing physical registers, resulting in poor flexibility, high latency, and additional software maintenance overhead. Furthermore, these protocols are typically designed for device-level maintenance, and their complex handshake and confirmation mechanisms are redundant and inefficient in inter-chip register-level access scenarios. Therefore, there is an urgent need for an inter-chip register direct access technology that can balance high bandwidth, low latency, and high reliability without requiring an MCU or additional physical interfaces. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a method, system and storage medium for accessing MCU chip registers without MCU chip registers. By receiving and identifying specific identifiers in the data stream to separate management messages, and then sequentially executing a complete process of structure verification, operation verification, bus transaction execution and hierarchical error response, the invention achieves direct parsing of management messages and register operations on the shared high-speed data channel at the hardware level, eliminating the dependence on MCU and software protocol stack.

[0005] Specifically, firstly, by comparing multiple thresholds such as message length, version, operation type, and sequence number, abnormal messages such as those with format errors, version mismatches, unauthorized operations, and replay attacks are effectively intercepted, ensuring front-end data security. Secondly, address whitelisting and data value field checks ensure the accuracy and security of each register access, preventing accidental writing or malicious tampering of critical registers. Thirdly, a bus transaction execution and timeout monitoring mechanism ensures reliable completion of hardware access and timely handling of abnormal timeouts. Furthermore, differentiated handling is implemented based on error type and identifier, and physical separation of management and business flows is achieved, along with graded error responses. This results in low latency and precise register-level control of the dedicated bus, and enhances anti-interference, anti-attack, and fault self-handling capabilities.

[0006] The first aspect of this invention provides a method for accessing registers without an MCU chip, applied to a master control chip and a slave chip without an MCU connected via a high-speed data interface, the method comprising: In response to receiving the data stream from the high-speed data interface, the first identifier is obtained through parsing. If the first identifier is the same as the preset reference identifier, the data stream is extracted to obtain the management message; Extract the preset structure fields of the management message to obtain the structure feature set; The structural feature set is compared sequentially with the preset structural threshold set to determine whether the structural verification passes or fails. If the structure verification passes, the preset operation fields of the management message are extracted to obtain the operation feature set; The operation feature set is compared with the preset operation threshold set in turn to determine whether the operation verification passes or fails. If the operation verification passes, the operation feature set is extracted to obtain the operation command; Execute the bus write transaction according to the operation command, and obtain the transaction completion status; If the transaction is completed successfully, a success response message is sent back to the main control chip; If a transaction fails to complete, a structure check fails, or an operation check fails, an error response is triggered based on a preset error classification mechanism.

[0007] In this scheme, the step of sequentially comparing the structural feature set with a preset structural threshold set to determine whether the structural verification passes or fails specifically includes: The structural feature set includes at least the total message length, version information, operation information, and sequence number; Determine whether the total length of the message is within the preset message length range to obtain the first verification result; Based on the version information, the scope of operation permissions is obtained, and it is determined whether the operation information is within the scope of operation permissions to obtain a second verification result. Determine whether the serial number is in the preset local serial number pool to obtain the third verification result; The structure verification is considered successful only if the first verification result, the second verification result, and the third verification result are all successful.

[0008] In this scheme, the step of sequentially comparing the operation feature set with the preset operation threshold set to determine whether the operation verification passes or fails specifically includes: The operation feature set includes at least the target register address and operation data; Based on the operation information, determine the access address whitelist; If the target register address is within the access address whitelist, the address verification is deemed successful. If the operation information is the first write operation, then the valid range of data is determined according to the target register address; Determine whether the operation data is within the valid data range; If so, the operation verification is considered successful; If not, the operation verification is deemed to have failed.

[0009] In this scheme, the step of executing a bus write transaction according to an operation command and obtaining the transaction completion status specifically includes: Based on the operation command and a preset register bus timing specification, a register access signal set is generated. Execute bus operation transactions according to the access signal set, initiate read or write operations on the target register, and start the transaction timeout counter; Monitor bus feedback signals while executing or waiting for bus operation transactions; If the transaction times out or an error signal is received, the transaction is considered to have failed; otherwise, the transaction is considered to have succeeded.

[0010] In this solution, if a transaction fails, a structure check fails, or an operation check fails, an error response is triggered based on a preset error classification mechanism, specifically including: When a transaction fails to complete, a structure check fails, or an operation check fails, a preset error classification mechanism is executed based on the data that triggered the failure and the type of failure to obtain the error level. Based on the error level, the error counter for the corresponding category is incremented to obtain the first error count value; Determine whether the first error count value is lower than the error count threshold for the corresponding category; If so, generate a response message containing the error code; If not, a hardware alarm signal will be triggered based on the error level.

[0011] In this scheme, the step of responding to the data stream received from the high-speed data interface and parsing to obtain the first identifier further includes: Based on the data stream, a first identifier is obtained by parsing a preset identifier field; Determine whether the first identifier is the same as the preset reference identifier; If so, a management path enable signal is generated, the data stream is stored in the management message buffer queue, and the original management message to be processed is obtained; If not, a business path enable signal is generated to guide the data flow to the business data pipeline.

[0012] A second aspect of the present invention provides an MCU-less register access system, applied to a master control chip and an MCU-less slave chip connected via a high-speed data interface, comprising an MCU-less register access method program, wherein the MCU-less register access method program, when executed by the processor, performs the following steps: In response to receiving the data stream from the high-speed data interface, the first identifier is obtained through parsing. If the first identifier is the same as the preset reference identifier, the data stream is extracted to obtain the management message; Extract the preset structure fields of the management message to obtain the structure feature set; The structural feature set is compared sequentially with the preset structural threshold set to determine whether the structural verification passes or fails. If the structure verification passes, the preset operation fields of the management message are extracted to obtain the operation feature set; The operation feature set is compared with the preset operation threshold set in turn to determine whether the operation verification passes or fails. If the operation verification passes, the operation feature set is extracted to obtain the operation command; Execute the bus write transaction according to the operation command, and obtain the transaction completion status; If the transaction is completed successfully, a success response message is sent back to the main control chip; If a transaction fails to complete, a structure check fails, or an operation check fails, an error response is triggered based on a preset error classification mechanism.

[0013] A third aspect of the present invention provides a computer-readable storage medium including a method program for accessing MCU chip registers without an MCU chip, wherein when the method program is executed by a processor, it implements the steps of the method for accessing MCU chip registers without an MCU chip as described in any of the preceding claims.

[0014] This invention provides a method, system, and storage medium for accessing registers without an MCU chip. It is applied between a master control chip and a slave chip without an MCU, enabling in-band management through a shared high-speed data interface. Specifically, after receiving the data stream, the identifier is parsed and compared with a preset value to separate management messages. The messages undergo structural verification, sequentially verifying the compliance of the structural feature set. After passing structural verification, operation fields are extracted for operation verification. Once the operation verification passes, it is converted into an internal bus transaction for register access, and the completion status is monitored. Finally, based on the operation result, a success response or a tiered error response is sent back to the master control chip. This achieves multi-layered chain verification and direct register operation, balancing high bandwidth, low latency configuration efficiency, and strong security access control without requiring an independent management interface and MCU, while reducing chip cost and transmission system complexity. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope.

[0016] Figure 1 A schematic diagram of a management message provided by an embodiment of the present invention is shown; Figure 2 A flowchart of a method for accessing MCU chip registers according to the present invention is shown; Figure 3 A flowchart of a structural verification method provided by an embodiment of the present invention is shown; Figure 4 A flowchart of an operation verification provided by an embodiment of the present invention is shown; Figure 5 A block diagram of an access system for MCU chip registers according to the present invention is shown. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) used in embodiments of this invention shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in a common dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as being interpreted in an idealized or highly formalized sense, unless expressly defined in this embodiment of the invention.

[0019] The terms "first," "second," and similar words used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "an," "a," or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Similarly, terms such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The steps preceding or following the steps in the method of the embodiments of this invention are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0020] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0021] Figure 1 This diagram illustrates a management message provided by an embodiment of the present invention.

[0022] like Figure 1 As shown, a management message includes a message header, an identifier field, a management field, a data field, and a message trailer.

[0023] The message header (14 bytes) includes: The DA field, 6 bytes, is the destination MAC address. This field identifies the receiver of the frame. The SA field, 6 bytes, is the source MAC address. This field identifies the sender of the frame. The TPID field (Tag Protocol Identifier), 2 bytes, indicates the frame type.

[0024] The identifier field (4 bytes) includes: The PRI+CFI+VID field, 2 bytes, includes: the PRI field, 3 bits, indicating the QoS priority of the frame; the CFI field (Canonical Format Indicator), 1 bit, indicating whether the MAC address is in standard format; and the VID field (VLAN ID), 12 bits, indicating the VLAN to which the frame belongs. The EtherType field, 2 bytes, indicates the protocol type.

[0025] The management field (4 bytes) includes: The Ver field, 1 byte, indicates the protocol version; The Msg Type field, 1 byte, indicates the operation type. As one implementation, 0x01 indicates a single register read request, 0x02 indicates a single register write request, 0x03 indicates a bulk read request, 0x04 indicates a bulk write request, 0x81 indicates a read response, 0x82 indicates a write response, and 0xFF indicates an error response. The Seq field, 2 bytes, represents the sequence number (0-65535 cyclically), used for request / response matching and detecting duplicate or out-of-order messages.

[0026] The operation field (8 bytes) includes: The RegAddr field, 4 bytes, represents the base address of a 32-bit register; The Len field, 2 bytes, indicates the data length (in bytes, 4-1024). The Flag field, 1 byte, indicates whether a response is required; The Rsv field, 1 byte, indicates that the extended field is reserved.

[0027] Data fields: The minimum length of the Data field is 4 bytes (single register), and the maximum length is 1024 bytes (256 registers). The length must be aligned to 4 bytes.

[0028] The message tail includes: The CRC32 field, 4 bytes, represents the CRC checksum value, covering from DA to the end of the data field; The Padding field indicates an optional padding field used to ensure that the message is ≥64 bytes (minimum Ethernet frame). As one implementation, the padding content is 0x00.

[0029] In this embodiment, as one implementation, the first identifier is a VLAN ID (Virtual Local Area Network tag), and the reference identifier is 0xFFF. As another implementation, the first identifier is a VLAN ID, and the reference identifier is any IEEE 802.1Q reserved tag value from 0xFF0 to 0xFFE. As yet another implementation, the first identifier is a custom EtherType value (e.g., 0x9000).

[0030] In this embodiment, as one implementation, the high-speed data interface uses XFI (Ethernet Fiber Interface). As another implementation, the high-speed data interface uses SFI (SerDes Framer Interface). As yet another implementation, the high-speed data interface uses XAUI (Ethernet Interface Extender). As yet another implementation, the high-speed data interface uses 25G / 50G SerDes (High-Speed ​​Serial Interface Extender).

[0031] In this embodiment, as one implementation, the register bus protocol uses APB (Advanced Peripheral Bus, ARM standard). As another implementation, the register bus protocol uses AHB (Advanced High-performance Bus). As yet another implementation, the register bus protocol uses AXI-Lite. As yet another implementation, the register bus protocol uses a custom register interface.

[0032] In this embodiment, as one implementation method, the minimum message length is 64 bytes; the typical length is 72 bytes; the extended length is 128 bytes or 256 bytes; and the maximum length is 1500 bytes.

[0033] Figure 2 A flowchart of a method for accessing MCU chip registers according to the present invention is shown.

[0034] like Figure 2 As shown, the first aspect of this invention discloses a method for accessing registers without an MCU chip, applied to a master control chip and a slave chip without an MCU connected via a high-speed data interface, characterized in that the method includes: S202, in response to receiving the data stream from the high-speed data interface, the first identifier is parsed and obtained; S204, If the first identifier is the same as the preset reference identifier, then extract the data stream to obtain the management message; S206, Extract the preset structure fields of the management message to obtain the structure feature set; S208, compare the structural feature set with the preset structural threshold set in turn, and determine whether the structural verification passes or fails; S210, If the structure verification passes, extract the preset operation fields of the management message to obtain the operation feature set; S212, compare the operation feature set with the preset operation threshold set in turn, and determine whether the operation verification passes or fails; S214, If the operation verification passes, the operation feature set is extracted to obtain the operation command; S216, execute the bus write transaction according to the operation command, and obtain the transaction completion status; S218, If the transaction is completed successfully, a success response message is sent back to the main control chip; S220 If the transaction fails to complete, the structure verification fails, or the operation verification fails, an error response is triggered based on the preset error classification mechanism.

[0035] It should be noted that in this embodiment, in the slave chip without an MCU, a mixed data stream from the master control chip is received via a high-speed data interface. First, the first identifier located in the data link layer is parsed from the received Ethernet format data frame. This first identifier is typically the VLAN ID in the VLAN tag. The first identifier is compared with a preset reference identifier. If they match, the message is determined to be a management message, and it is separated from the service data stream to extract the complete message payload for subsequent processing. Then, the management message undergoes structural verification: multiple structural features, including total length, protocol version, operation type, and sequence number, are extracted from a fixed offset position in the message and compared sequentially with a preset set of structural thresholds. This includes checking if the length is compliant, if the version and operation type are valid, and if the sequence number meets the continuity requirements. If all thresholds are met, the structural verification is considered successful. Next, operation features are parsed from the message, mainly including the target register address and the data to be written. Operation verification is performed based on the operation type, such as checking if the target address is within the accessible whitelist range. If it is a write operation, it is also necessary to confirm if the data value is within the allowed value range of the register. After successful operation verification, a specific register access command is generated, converted into a signal conforming to the chip's internal register bus timing, and a read / write transaction is initiated. Bus responses and timeout status are monitored to determine transaction completion. Finally, if the transaction succeeds, a success response message is constructed and returned; if any of the above-mentioned structural verification, operation verification, or transaction execution fails, the corresponding error response process is triggered according to a preset error classification mechanism. This embodiment implements the entire process from message recognition and multi-layer verification to register operation through a hardware pipeline. Without MCU intervention, it ensures a high-bandwidth, low-latency configuration channel while enhancing access security and reliability through a chain-verification mechanism.

[0036] Figure 3 A flowchart of a structural verification method provided by an embodiment of the present invention is shown.

[0037] According to embodiments of the present invention, such as Figure 3 As shown, the step of sequentially comparing the structural feature set with a preset structural threshold set to determine whether the structural verification passes or fails specifically includes: S302, the structural feature set includes at least the total message length, version information, operation information, and sequence number; S304, determine whether the total length of the message is within the preset message length range, and obtain the first verification result; S306, Based on the version information, obtain the scope of operation permissions, determine whether the operation information is within the scope of operation permissions, and obtain a second verification result; S308, determine whether the serial number is in the preset local serial number pool, and obtain the third verification result; S310: The structure verification is deemed to have passed only if the first verification result, the second verification result, and the third verification result are all passed.

[0038] It should be noted that in this embodiment, during the structure verification phase, the total message length, version information, operation type code, and sequence number are first parsed from the management message header to form a structure feature set. The hardware comparator first compares the total message length with the pre-configured valid length range. If the length is too short or too long, it is determined to be invalid, generating a first verification result. Next, the corresponding permission configuration table is indexed according to the version information to check whether the operation type code in the message is within the set, thereby generating a second verification result. At the same time, a dynamic sequence number pool is maintained locally to record the window of recently received valid sequence numbers. The sequence number in the message is matched with this pool. If it is the expected new sequence number or within the allowed retransmission window, a third verification result is generated. Finally, only when all three verification results pass, does the state machine determine that the overall structure verification has passed, allowing the message to enter the subsequent processing stage. This effectively intercepts various abnormal messages such as those with abnormal length, version mismatch, unauthorized operation, and illegal sequence numbers (such as replay attacks).

[0039] Figure 4 A flowchart of an operation verification method provided by an embodiment of the present invention is shown.

[0040] According to embodiments of the present invention, such as Figure 4 As shown, the step of sequentially comparing the operation feature set with the preset operation threshold set to determine whether the operation verification passes or fails specifically includes: S402, the operation feature set includes at least the target register address and operation data; S404, Determine the access address whitelist based on the operation information; S406, If the target register address is within the access address whitelist, then the address verification is deemed successful; S408, if the operation information is a first write operation, then the valid range of data is determined according to the target register address; S410, determine whether the operation data is within the valid data range; S412, if yes, then the operation verification is considered successful; S414, if not, the operation verification is deemed to have failed.

[0041] It should be noted that in this embodiment, during the operation verification phase, the target register address and operation data payload are extracted from the management message. First, based on the operation type indicated in the message, the corresponding address access whitelist is retrieved. This whitelist is stored in hardware in the form of address ranges and masks. By comparing the target register address with all whitelist entries in parallel, if no match is found, the address verification is immediately deemed to have failed. If the address verification passes, and the current operation type is a write operation, data value range verification is further initiated: based on the target register address, pre-configured data valid range rules and bitmask rules are searched. The operation data in the message is compared with the valid range, and after filtering out unwritable bits using a bitmask, it is checked whether there are still data changes. Only write data that fully conforms to the range and only modifies allowed bits is allowed. If the address verification passes, and the current operation type is a read operation, the operation verification is directly passed. This embodiment prevents accidental or malicious writing to critical or reserved registers through the address whitelist mechanism and ensures the rationality of the written values ​​through data value range verification, thereby enhancing the security of register operations.

[0042] According to an embodiment of the present invention, the step of executing a bus write transaction according to an operation command and obtaining a transaction completion status specifically includes: Based on the operation command and a preset register bus timing specification, a register access signal set is generated. Execute bus operation transactions according to the access signal set, initiate read or write operations on the target register, and start the transaction timeout counter; Monitor bus feedback signals while executing or waiting for bus operation transactions; If the transaction times out or an error signal is received, the transaction is considered to have failed; otherwise, the transaction is considered to have succeeded.

[0043] It should be noted that in this embodiment, when executing a bus write transaction, the internally generated operation command is first converted into a set of physical signals conforming to the chip's internal register bus protocol, including address lines, data lines, read / write control signals, and chip select signals. After the transaction starts, the hardware state machine simultaneously starts a configurable timeout counter, which counts based on the bus clock. During transaction execution, the feedback signals returned by the bus are continuously monitored, such as the PREADY and PSLVERR signals on the APB bus. If a ready signal indicating successful operation is received before the timeout counter reaches the threshold, the transaction is immediately determined to be successful. If an error response signal is received before the timeout, or if no valid completion signal is received before the counter times out, the transaction is determined to have failed. This embodiment avoids management channel blockage caused by bus hangs or unresponsive slave devices through a timeout monitoring mechanism.

[0044] According to an embodiment of the present invention, if the transaction fails, the structure verification fails, or the operation verification fails, an error response is triggered based on a preset error classification mechanism, specifically including: When a transaction fails to complete, a structural check fails, or a semantic check fails, a preset error classification mechanism is executed based on the data that triggered the failure and the failure type to obtain the error level. Based on the error level, the error counter for the corresponding category is incremented to obtain the first error count value; Determine whether the first error count value is lower than the error count threshold for the corresponding category; If so, generate a response message containing the error code; If not, a hardware alarm signal will be triggered based on the error level.

[0045] It should be noted that in this embodiment, the error handling process is immediately activated when any stage of structural verification, operational verification, or bus transaction execution fails. First, based on the specific data field that triggered the failure (such as an illegal address, out-of-limit data, or erroneous bus signal) and its failure type (such as format error, permission error, or timeout error), the failure is categorized into one of several preset error levels using predefined classification mapping rules, such as temporary errors, configuration errors, or security errors. Then, the hardware counter corresponding to the error level is accessed and incremented to obtain the latest error count value. The error count value is compared with a threshold configured for that error level: if the count value is below the threshold, a response message containing a specific error code is generated and returned to the main control chip for diagnosis; if the count value has reached or exceeded the threshold, indicating that such errors have been occurring continuously or frequently, a hardware-level alarm signal is triggered to raise the alarm pin level or interrupt the main control chip. The hierarchical response mechanism provided in this embodiment can distinguish between occasional anomalies and potential attacks or faults, providing clear early warning signals for system-level monitoring.

[0046] According to an embodiment of the present invention, the step of parsing to obtain the first identifier in response to receiving the data stream from the high-speed data interface further includes: Based on the data stream, a first identifier is obtained by parsing a preset identifier field; Determine whether the first identifier is the same as the preset reference identifier; If so, a management path enable signal is generated, the data stream is stored in the management message buffer queue, and the original management message to be processed is obtained; If not, a business path enable signal is generated to guide the data flow to the business data pipeline.

[0047] It should be noted that in this embodiment, during the initial processing phase of the data stream, a first identifier is extracted from the received Ethernet frame. Subsequently, a dedicated hardware comparator compares this identifier with a pre-stored reference identifier (e.g., 0x0FFF) in real time. If they match, the hardware logic generates a management path enable signal, controlling the data switch to store the entire content of the current data frame into an independent management message buffer queue, thereby completing the extraction and temporary storage of management messages. If they differ, a service path enable signal is generated, guiding the data frame directly into the pipeline responsible for processing regular service data, without causing any delay or interference to the management path. This embodiment achieves real-time separation of management traffic and service traffic at the physical layer through hardware-level parallel identification and path switching, avoiding the delay and resource overhead caused by software discrimination.

[0048] It is worth mentioning that after extracting the data stream to obtain the management message, the process also includes: Extract the preset tail field of the management message to obtain the first checksum; Based on the management message, a second verification code is obtained using a preset encryption and verification algorithm; Determine whether the first check code and the second check code are consistent; If so, the message is considered complete; If not, the message is deemed corrupted, an error response is triggered, and the message is discarded.

[0049] It should be noted that in this embodiment, firstly, a first checksum calculated and filled by the sender is extracted from a predetermined end position of the management message. Simultaneously, based on the received message content, a second checksum is generated in real-time using the same preset encryption or verification algorithm (such as CRC32 or a specific hash algorithm) as the sender. Next, a hardware comparison circuit checks the consistency between the first and second checksums. If they are completely identical, the message is determined to have been undamaged during transmission and is allowed to proceed to the subsequent structure verification process; if they are inconsistent, the message integrity is determined to have been compromised, and the system immediately triggers an error response mechanism, discarding the message and optionally generating an error report indicating verification failure. This embodiment, by adding an integrity verification layer, reduces data corruption caused by channel noise, transmission errors, or intermediate tampering, thereby improving the protocol's anti-interference capability.

[0050] It is worth mentioning that, after the structural verification passes but before the operational verification is performed, the following steps are also included: Based on the operation information of the structural feature set and the target register address of the operation feature set, and based on the preset operation criticality evaluation logic, the priority information of the management operation is obtained. Based on the priority information, the feature set of operations to be verified in the operation verification queue is sorted. Based on the adjusted operation verification queue, operation verification is performed sequentially.

[0051] It should be noted that in this embodiment, a pre-set operation criticality evaluation rule table is queried based on the operation type (such as read / write operations, batch operations) and the target register address in the verified structural feature set. This rule table defines the urgency and resource requirements corresponding to different operation and address combinations, thus providing priority information for the current management operation assignment. Subsequently, based on this priority information, all pending operation feature sets in the operation verification waiting queue are reordered, with high-priority operations moved to the front of the queue. This embodiment, through priority scheduling, ensures lower processing latency for access to critical configuration registers or urgent control commands, enabling important management operations to be completed first, thereby enhancing the real-time performance and flexibility of management control.

[0052] It is worth mentioning that it also includes: Based on the data and failure type that triggered the failure, one or more candidate recovery action sequences are generated based on a preset root cause analysis and recovery strategy matching model. Based on a pre-defined assessment of available resources, the first recovery action to be executed is selected from the candidate recovery action sequence; After performing the first recovery action, the error state is cleaned up and the operation command that triggered the error response is re-executed and recorded in the recovery log.

[0053] It should be noted that in this embodiment, firstly, based on the original data of the failed trigger, the failure type, and historical operation logs, analysis is performed using a pre-defined root cause analysis and recovery strategy matching model; where the matching model is a set of predefined discrimination rules or a lightweight state decision machine. One or more possible candidate recovery action sequences are generated, such as "reset the local state machine," "retry the last operation," or "rollback to a safe configuration." Then, the current available hardware resource status (such as buffer space and bus idle time) is evaluated, and the execution overhead and success rate of each candidate recovery action are estimated, selecting the most feasible first recovery action. After executing the first recovery action, the error state is cleaned up, and the operation instruction that triggered the error can be re-executed. Simultaneously, the actions and results of the entire recovery process are recorded in a dedicated recovery log. This embodiment enables slave chips without an MCU to possess autonomous fault recovery capabilities, reducing reliance on the main control chip for intervention.

[0054] Figure 5 A block diagram of an access system for MCU chip registers according to the present invention is shown.

[0055] like Figure 5 As shown, a second aspect of the present invention discloses an MCU-less register access system 5, comprising a memory 51 and a processor 52. The memory includes a MCU-less register access method program, which, when executed by the processor, performs the following steps: In response to receiving the data stream from the high-speed data interface, the first identifier is obtained through parsing. If the first identifier is the same as the preset reference identifier, the data stream is extracted to obtain the management message; Extract the preset structure fields of the management message to obtain the structure feature set; The structural feature set is compared sequentially with the preset structural threshold set to determine whether the structural verification passes or fails. If the structure verification passes, the preset operation fields of the management message are extracted to obtain the operation feature set; The operation feature set is compared with the preset operation threshold set in turn to determine whether the operation verification passes or fails. If the operation verification passes, the operation feature set is extracted to obtain the operation command; Execute the bus write transaction according to the operation command, and obtain the transaction completion status; If the transaction is completed successfully, a success response message is sent back to the main control chip; If a transaction fails to complete, a structure check fails, or an operation check fails, an error response is triggered based on a preset error classification mechanism.

[0056] It should be noted that in this embodiment, in the slave chip without an MCU, a mixed data stream from the master control chip is received via a high-speed data interface. First, the first identifier located in the data link layer is parsed from the received Ethernet format data frame. This first identifier is typically the VLAN ID in the VLAN tag. The first identifier is compared with a preset reference identifier. If they match, the message is determined to be a management message, and it is separated from the service data stream to extract the complete message payload for subsequent processing. Then, the management message undergoes structural verification: multiple structural features, including total length, protocol version, operation type, and sequence number, are extracted from a fixed offset position in the message and compared sequentially with a preset set of structural thresholds. This includes checking if the length is compliant, if the version and operation type are valid, and if the sequence number meets the continuity requirements. If all thresholds are met, the structural verification is considered successful. Next, operation features are parsed from the message, mainly including the target register address and the data to be written. Operation verification is performed based on the operation type, such as checking if the target address is within the accessible whitelist range. If it is a write operation, it is also necessary to confirm if the data value is within the allowed value range of the register. After successful operation verification, a specific register access command is generated, converted into a signal conforming to the chip's internal register bus timing, and a read / write transaction is initiated. Bus responses and timeout status are monitored to determine transaction completion. Finally, if the transaction succeeds, a success response message is constructed and returned; if any of the above-mentioned structural verification, operation verification, or transaction execution fails, the corresponding error response process is triggered according to a preset error classification mechanism. This embodiment implements the entire process from message recognition and multi-layer verification to register operation through a hardware pipeline. Without MCU intervention, it ensures a high-bandwidth, low-latency configuration channel while enhancing access security and reliability through a chain-verification mechanism.

[0057] Figure 3 A flowchart of a structural verification method provided by an embodiment of the present invention is shown.

[0058] According to embodiments of the present invention, such as Figure 3 As shown, the step of sequentially comparing the structural feature set with a preset structural threshold set to determine whether the structural verification passes or fails specifically includes: The structural feature set includes at least the total message length, version information, operation information, and sequence number; Determine whether the total length of the message is within the preset message length range to obtain the first verification result; Based on the version information, the scope of operation permissions is obtained, and it is determined whether the operation information is within the scope of operation permissions to obtain a second verification result. Determine whether the serial number is in the preset local serial number pool to obtain the third verification result; The structure verification is considered successful only if the first verification result, the second verification result, and the third verification result are all successful.

[0059] It should be noted that in this embodiment, during the structure verification phase, the total message length, version information, operation type code, and sequence number are first parsed from the management message header to form a structure feature set. The hardware comparator first compares the total message length with the pre-configured valid length range. If the length is too short or too long, it is determined to be invalid, generating a first verification result. Next, the corresponding permission configuration table is indexed according to the version information to check whether the operation type code in the message is within the set, thereby generating a second verification result. At the same time, a dynamic sequence number pool is maintained locally to record the window of recently received valid sequence numbers. The sequence number in the message is matched with this pool. If it is the expected new sequence number or within the allowed retransmission window, a third verification result is generated. Finally, only when all three verification results pass, does the state machine determine that the overall structure verification has passed, allowing the message to enter the subsequent processing stage. This effectively intercepts various abnormal messages such as those with abnormal length, version mismatch, unauthorized operation, and illegal sequence numbers (such as replay attacks).

[0060] Figure 4 A flowchart of an operation verification method provided by an embodiment of the present invention is shown.

[0061] According to embodiments of the present invention, such as Figure 4 As shown, the step of sequentially comparing the operation feature set with the preset operation threshold set to determine whether the operation verification passes or fails specifically includes: The operation feature set includes at least the target register address and operation data; Based on the operation information, determine the access address whitelist; If the target register address is within the access address whitelist, the address verification is deemed successful. If the operation information is the first write operation, then the valid range of data is determined according to the target register address; Determine whether the operation data is within the valid data range; If so, the operation verification is considered successful; If not, the operation verification is deemed to have failed.

[0062] It should be noted that in this embodiment, during the operation verification phase, the target register address and operation data payload are extracted from the management message. First, based on the operation type indicated in the message, the corresponding address access whitelist is retrieved. This whitelist is stored in hardware in the form of address ranges and masks. By comparing the target register address with all whitelist entries in parallel, if no match is found, the address verification is immediately deemed a failure. If the address verification passes, and the current operation type is a write operation, data value range verification is further initiated: based on the target register address, pre-configured data valid range rules and bitmask rules are searched. The operation data in the message is compared with the valid range, and after filtering out unwritable bits using a bitmask, it is checked whether there are still data changes. Only write data that fully conforms to the range and only modifies allowed bits is allowed. This embodiment prevents accidental or malicious writing to critical or reserved registers through the address whitelist mechanism and ensures the rationality of the written values ​​through data value range verification, thereby enhancing the security of register operations.

[0063] According to an embodiment of the present invention, the step of executing a bus write transaction according to an operation command and obtaining a transaction completion status specifically includes: Based on the operation command and a preset register bus timing specification, a register access signal set is generated. Execute bus operation transactions according to the access signal set, initiate read or write operations on the target register, and start the transaction timeout counter; Monitor bus feedback signals while executing or waiting for bus operation transactions; If the transaction times out or an error signal is received, the transaction is considered to have failed; otherwise, the transaction is considered to have succeeded.

[0064] It should be noted that in this embodiment, when executing a bus write transaction, the internally generated operation command is first converted into a set of physical signals conforming to the chip's internal register bus protocol, including address lines, data lines, read / write control signals, and chip select signals. After the transaction starts, the hardware state machine simultaneously starts a configurable timeout counter, which counts based on the bus clock. During transaction execution, the feedback signals returned by the bus are continuously monitored, such as the PREADY and PSLVERR signals on the APB bus. If a ready signal indicating successful operation is received before the timeout counter reaches the threshold, the transaction is immediately determined to be successful. If an error response signal is received before the timeout, or if no valid completion signal is received before the counter times out, the transaction is determined to have failed. This embodiment avoids management channel blockage caused by bus hangs or unresponsive slave devices through a timeout monitoring mechanism.

[0065] According to an embodiment of the present invention, if the transaction fails, the structure verification fails, or the operation verification fails, an error response is triggered based on a preset error classification mechanism, specifically including: When a transaction fails to complete, a structural check fails, or a semantic check fails, a preset error classification mechanism is executed based on the data that triggered the failure and the failure type to obtain the error level. Based on the error level, the error counter for the corresponding category is incremented to obtain the first error count value; Determine whether the first error count value is lower than the error count threshold for the corresponding category; If so, generate a response message containing the error code; If not, a hardware alarm signal will be triggered based on the error level.

[0066] It should be noted that in this embodiment, the error handling process is immediately activated when any stage of structural verification, operational verification, or bus transaction execution fails. First, based on the specific data field that triggered the failure (such as an illegal address, out-of-limit data, or erroneous bus signal) and its failure type (such as format error, permission error, or timeout error), the failure is categorized into one of several preset error levels using predefined classification mapping rules, such as temporary errors, configuration errors, or security errors. Then, the hardware counter corresponding to the error level is accessed and incremented to obtain the latest error count value. The error count value is compared with a threshold configured for that error level: if the count value is below the threshold, a response message containing a specific error code is generated and returned to the main control chip for diagnosis; if the count value has reached or exceeded the threshold, indicating that such errors have been occurring continuously or frequently, a hardware-level alarm signal is triggered to raise the alarm pin level or interrupt the main control chip. The hierarchical response mechanism provided in this embodiment can distinguish between occasional anomalies and potential attacks or faults, providing clear early warning signals for system-level monitoring.

[0067] According to an embodiment of the present invention, the step of parsing to obtain the first identifier in response to receiving the data stream from the high-speed data interface further includes: Based on the data stream, a first identifier is obtained by parsing a preset identifier field; Determine whether the first identifier is the same as the preset reference identifier; If so, a management path enable signal is generated, the data stream is stored in the management message buffer queue, and the original management message to be processed is obtained; If not, a business path enable signal is generated to guide the data flow to the business data pipeline.

[0068] It should be noted that in this embodiment, during the initial processing phase of the data stream, a first identifier is extracted from the received Ethernet frame. Subsequently, a dedicated hardware comparator compares this identifier with a pre-stored reference identifier (e.g., 0x0FFF) in real time. If they match, the hardware logic generates a management path enable signal, controlling the data switch to store the entire content of the current data frame into an independent management message buffer queue, thereby completing the extraction and temporary storage of management messages. If they differ, a service path enable signal is generated, guiding the data frame directly into the pipeline responsible for processing regular service data, without causing any delay or interference to the management path. This embodiment achieves real-time separation of management traffic and service traffic at the physical layer through hardware-level parallel identification and path switching, avoiding the delay and resource overhead caused by software discrimination.

[0069] It is worth mentioning that after extracting the data stream to obtain the management message, the process also includes: Extract the preset tail field of the management message to obtain the first checksum; Based on the management message, a second verification code is obtained using a preset encryption and verification algorithm; Determine whether the first check code and the second check code are consistent; If so, the message is considered complete; If not, the message is deemed corrupted, an error response is triggered, and the message is discarded.

[0070] It should be noted that in this embodiment, firstly, a first checksum calculated and filled by the sender is extracted from a predetermined end position of the management message. Simultaneously, based on the received message content, a second checksum is generated in real-time using the same preset encryption or verification algorithm (such as CRC32 or a specific hash algorithm) as the sender. Next, a hardware comparison circuit checks the consistency between the first and second checksums. If they are completely identical, the message is determined to have been undamaged during transmission and is allowed to proceed to the subsequent structure verification process; if they are inconsistent, the message integrity is determined to have been compromised, and the system immediately triggers an error response mechanism, discarding the message and optionally generating an error report indicating verification failure. This embodiment, by adding an integrity verification layer, reduces data corruption caused by channel noise, transmission errors, or intermediate tampering, thereby improving the protocol's anti-interference capability.

[0071] It is worth mentioning that, after the structural verification passes but before the operational verification is performed, the following steps are also included: Based on the operation information of the structural feature set and the target register address of the operation feature set, and based on the preset operation criticality evaluation logic, the priority information of the management operation is obtained. Based on the priority information, the feature set of operations to be verified in the operation verification queue is sorted. Based on the adjusted operation verification queue, operation verification is performed sequentially.

[0072] It should be noted that in this embodiment, a pre-set operation criticality evaluation rule table is queried based on the operation type (such as read / write operations, batch operations) and the target register address in the verified structural feature set. This rule table defines the urgency and resource requirements corresponding to different operation and address combinations, thus providing priority information for the current management operation assignment. Subsequently, based on this priority information, all pending operation feature sets in the operation verification waiting queue are reordered, with high-priority operations moved to the front of the queue. This embodiment, through priority scheduling, ensures lower processing latency for access to critical configuration registers or urgent control commands, enabling important management operations to be completed first, thereby enhancing the real-time performance and flexibility of management control.

[0073] It is worth mentioning that it also includes: Based on the data and failure type that triggered the failure, one or more candidate recovery action sequences are generated based on a preset root cause analysis and recovery strategy matching model. Based on a pre-defined assessment of available resources, the first recovery action to be executed is selected from the candidate recovery action sequence; After performing the first recovery action, the error state is cleaned up and the operation command that triggered the error response is re-executed and recorded in the recovery log.

[0074] It should be noted that in this embodiment, firstly, based on the original data of the failed trigger, the failure type, and historical operation logs, analysis is performed using a pre-defined root cause analysis and recovery strategy matching model; where the matching model is a set of predefined discrimination rules or a lightweight state decision machine. One or more possible candidate recovery action sequences are generated, such as "reset the local state machine," "retry the last operation," or "rollback to a safe configuration." Then, the current available hardware resource status (such as buffer space and bus idle time) is evaluated, and the execution overhead and success rate of each candidate recovery action are estimated, selecting the most feasible first recovery action. After executing the first recovery action, the error state is cleaned up, and the operation instruction that triggered the error can be re-executed. Simultaneously, the actions and results of the entire recovery process are recorded in a dedicated recovery log. This embodiment enables slave chips without an MCU to possess autonomous fault recovery capabilities, reducing reliance on the main control chip for intervention.

[0075] A third aspect of the present invention provides a computer-readable storage medium including a method program for accessing MCU chip registers without an MCU chip, wherein when the method program is executed by a processor, it implements the steps of the method for accessing MCU chip registers without an MCU chip as described in any of the preceding claims.

[0076] In summary, this invention provides a method, system, and storage medium for accessing registers without an MCU chip. It is applied between a master control chip and a slave chip without an MCU, enabling in-band management through a shared high-speed data interface. Specifically, after receiving the data stream, the identifier is parsed and compared with a preset value to separate management messages. The messages undergo structural verification, sequentially verifying the compliance of the structural feature set. After passing structural verification, operation fields are extracted for operation verification. Once the operation verification passes, it is converted into an internal bus transaction for register access, and the completion status is monitored. Finally, based on the operation result, a success response or a tiered error response is sent back to the master control chip. This achieves multi-layered chain verification and direct register operation, balancing high bandwidth, low latency configuration efficiency, and strong security access control without requiring an independent management interface and MCU, while reducing chip cost and transmission system complexity.

[0077] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for accessing registers without an MCU chip, applied to a master control chip and a slave chip without an MCU connected via a high-speed data interface, characterized in that, The method includes: In response to receiving the data stream from the high-speed data interface, the first identifier is obtained through parsing. If the first identifier is the same as the preset reference identifier, the data stream is extracted to obtain the management message; Extract the preset structure fields of the management message to obtain the structure feature set; The structural feature set is compared sequentially with the preset structural threshold set to determine whether the structural verification passes or fails. If the structure verification passes, the preset operation fields of the management message are extracted to obtain the operation feature set; The operation feature set is compared with the preset operation threshold set in turn to determine whether the operation verification passes or fails. If the operation verification passes, the operation feature set is extracted to obtain the operation command; Execute the bus write transaction according to the operation command, and obtain the transaction completion status; If the transaction is completed successfully, a success response message is sent back to the main control chip; If a transaction fails to complete, a structure check fails, or an operation check fails, an error response is triggered based on a preset error classification mechanism.

2. The method for accessing registers without an MCU chip according to claim 1, characterized in that, The step of sequentially comparing the structural feature set with a preset structural threshold set to determine whether the structural verification passes or fails specifically includes: The structural feature set includes at least the total message length, version information, operation information, and sequence number; Determine whether the total length of the message is within the preset message length range to obtain the first verification result; Based on the version information, the scope of operation permissions is obtained, and it is determined whether the operation information is within the scope of operation permissions to obtain a second verification result. Determine whether the serial number is in the preset local serial number pool to obtain the third verification result; The structure verification is considered successful only if the first verification result, the second verification result, and the third verification result are all successful.

3. The method for accessing registers without an MCU chip according to claim 2, characterized in that, The step of sequentially comparing the operation feature set with the preset operation threshold set to determine whether the operation verification passes or fails specifically includes: The operation feature set includes at least the target register address and operation data; Based on the operation information, determine the access address whitelist; If the target register address is within the access address whitelist, the address verification is deemed successful. If the operation information is the first write operation, then the valid range of data is determined according to the target register address; Determine whether the operation data is within the valid data range; If so, the operation verification is considered successful; If not, the operation verification is deemed to have failed.

4. The method for accessing registers without an MCU chip according to claim 1, characterized in that, The step of executing a bus write transaction according to an operation command and obtaining the transaction completion status specifically includes: Based on the operation command and a preset register bus timing specification, a register access signal set is generated. Execute bus operation transactions according to the access signal set, initiate read or write operations on the target register, and start the transaction timeout counter; Monitor bus feedback signals while executing or waiting for bus operation transactions; If the transaction times out or an error signal is received, the transaction is considered to have failed; otherwise, the transaction is considered to have succeeded.

5. The method for accessing registers without an MCU chip according to claim 1, characterized in that, If the transaction fails, the structure verification fails, or the operation verification fails, an error response is triggered based on a preset error classification mechanism, specifically including: When a transaction fails to complete, a structure check fails, or an operation check fails, a preset error classification mechanism is executed based on the data that triggered the failure and the type of failure to obtain the error level. Based on the error level, the error counter for the corresponding category is incremented to obtain the first error count value; Determine whether the first error count value is lower than the error count threshold for the corresponding category; If so, generate a response message containing the error code; If not, a hardware alarm signal will be triggered based on the error level.

6. The method for accessing registers without an MCU chip according to claim 1, characterized in that, The step of parsing the first identifier in response to receiving the data stream from the high-speed data interface further includes: Based on the data stream, a first identifier is obtained by parsing a preset identifier field; Determine whether the first identifier is the same as the preset reference identifier; If so, a management path enable signal is generated, the data stream is stored in the management message buffer queue, and the original management message to be processed is obtained; If not, a business path enable signal is generated to guide the data flow to the business data pipeline.

7. A register access system without an MCU chip, applied to a master control chip and a slave chip without an MCU connected via a high-speed data interface, characterized in that, The system includes a memory and a processor. The memory includes a method program for accessing MCU chip registers without the MCU chip registers. When the processor executes the method program for accessing MCU chip registers without the MCU chip registers, it performs the following steps: In response to receiving the data stream from the high-speed data interface, the first identifier is obtained through parsing. If the first identifier is the same as the preset reference identifier, the data stream is extracted to obtain the management message; Extract the preset structure fields of the management message to obtain the structure feature set; The structural feature set is compared sequentially with the preset structural threshold set to determine whether the structural verification passes or fails. If the structure verification passes, the preset operation fields of the management message are extracted to obtain the operation feature set; The operation feature set is compared with the preset operation threshold set in turn to determine whether the operation verification passes or fails. If the operation verification passes, the operation feature set is extracted to obtain the operation command; Execute the bus write transaction according to the operation command, and obtain the transaction completion status; If the transaction is completed successfully, a success response message is sent back to the main control chip; If a transaction fails to complete, a structure check fails, or an operation check fails, an error response is triggered based on a preset error classification mechanism.

8. The MCU chip-free register access system according to claim 7, characterized in that, The step of sequentially comparing the structural feature set with a preset structural threshold set to determine whether the structural verification passes or fails specifically includes: The structural feature set includes at least the total message length, version information, operation information, and sequence number; Determine whether the total length of the message is within the preset message length range to obtain the first verification result; Based on the version information, the scope of operation permissions is obtained, and it is determined whether the operation information is within the scope of operation permissions to obtain a second verification result. Determine whether the serial number is in the preset local serial number pool to obtain the third verification result; The structure verification is considered successful only if the first verification result, the second verification result, and the third verification result are all successful.

9. The MCU chip-free register access system according to claim 8, characterized in that, The step of sequentially comparing the operation feature set with the preset operation threshold set to determine whether the operation verification passes or fails specifically includes: The operation feature set includes at least the target register address and operation data; Based on the operation information, determine the access address whitelist; If the target register address is within the access address whitelist, the address verification is deemed successful. If the operation information is the first write operation, then the valid range of data is determined according to the target register address; Determine whether the operation data is within the valid data range; If so, the operation verification is considered successful; If not, the operation verification is deemed to have failed.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer-readable storage medium includes a method program for accessing MCU chip registers without MCU chips. When the method program for accessing MCU chip registers without MCU chips is executed by a processor, it implements the steps of the method for accessing MCU chip registers without MCU chips as described in any one of claims 1 to 6.

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