Signal acquisition device and method
By directly connecting the signal transfer structure and signal acquisition chip between the DRAM and the system platform, the problems of long signal transmission distance and signal distortion are solved, enabling in-situ signal acquisition and full-channel parallel acquisition, and quickly locating the cause of system failure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KINGTIGER TESTING TECH (SZ) LTD
- Filing Date
- 2026-05-14
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, the signal acquisition between DRAM and system platform by connecting the test points of the system platform through flexible cables has the disadvantages of long transmission distance, easy introduction of attenuation and interference, resulting in high-speed signal distortion, and the test points are far away from the DRAM solder ball array, which cannot truly reflect the signal status at the DRAM chip end.
A signal acquisition device is provided, including a dynamic random access memory, a signal transfer structure, and a signal acquisition chip. Through structures such as in-mold through-holes, double-sided slot memory modules, side connectors, or interposers, signals are directly electrically connected from the DRAM solder ball array to the signal acquisition chip, shortening the transmission distance, and the signal acquisition chip performs real-time sampling and processing.
It achieves in-situ signal acquisition and short-distance transmission, truly reflecting the actual working state of the internal circuitry of the DRAM chip, making up for the limitation of the number of channels, and enabling parallel acquisition of address, command, clock, data and data strobe signals across all channels, quickly locating the cause of system failure.
Smart Images
Figure CN122195897B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of signal transmission, and more particularly to a signal acquisition device and method. Background Technology
[0002] In existing technologies, external instruments such as Logic Analyzers are commonly used to collect signals between the DRAM and the system platform by connecting test points to the system platform via flexible cables. This method has significant drawbacks: the long transmission distance of the flexible cables easily introduces attenuation and interference, leading to distortion of high-speed signals; furthermore, the test points are far from the DRAM solder ball array, and the collected signals cannot accurately reflect the actual output state at the DRAM chip end, resulting in insufficient signal coverage and missing in-situ measurements. Summary of the Invention
[0003] In view of this, embodiments of this application provide a signal acquisition device and method that can shorten the transmission distance of a signal from the transmitting point (dynamic random access memory) to the receiving point (signal acquisition chip).
[0004] In a first aspect, this application provides a signal acquisition device, including: a dynamic random access memory, a signal switching structure, and a signal acquisition chip; The signal transfer structure is provided with a first interface and a second interface. The first interface is used to be electrically connected to the dynamic random access memory, and the second interface is used to be electrically connected to the system platform. The signal switching structure is used to receive and transmit communication signals transmitted between the dynamic random access memory and the system platform; The signal acquisition chip is electrically connected to the signal transfer structure and is used to receive the communication signal transmitted from the signal transfer structure. After sampling and processing the communication signal, the chip transmits the processed communication signal to an external data processing system through the signal transmission interface.
[0005] In an optional embodiment, the signal switching structure is an in-mold through-hole structure having at least two in-mold through holes; Each of the in-mold vias vertically penetrates the package of the dynamic random access memory (DRAM). The upper end of each of the in-mold vias is electrically connected to the chip pads of the DRAM, and the lower end is electrically connected to the signal transfer structure. The signal conversion structure is provided with a signal transmission interface, which is electrically connected to the input and output terminals of the signal acquisition chip.
[0006] In an optional implementation, the signal transfer structure is a double-sided slot-type memory module; The dynamic random access memory is mounted on the first surface of the double-sided slot memory module, and the signal acquisition chip is mounted on the second surface of the double-sided slot memory module; The first surface and the second surface are opposite surfaces; The double-sided slotted memory module has an internal conductive path for transmitting the communication signal of the dynamic random access memory to the input terminal of the signal acquisition chip; The dual-sided slotted memory module has a memory direct-insertion interface at one end for electrical connection to the system platform; and a signal transmission interface at the other end for electrical connection to an external data processing system.
[0007] In an optional implementation, the signal switching structure includes a first interposer layer and a side connector; The first intermediary layer is installed on the system platform; the dynamic random access memory is installed on the first intermediary layer. The side connector is a frame structure surrounding the periphery of the dynamic random access memory, and its inner wall is provided with a contact array. The signal acquisition chip is mounted on the top of the side connector, and the input port of the signal acquisition chip is electrically connected to the first interposer through the contact array of the side connector. The solder ball array of the dynamic random access memory and the contact array of the side connector are electrically connected through microbumps.
[0008] In an optional implementation, the signal switching structure is a second intermediary layer; The signal acquisition chip is disposed between the second intermediary layer and the dynamic random access memory; A front redistribution layer substrate is disposed on the front side of the signal acquisition chip, and a back redistribution layer substrate is disposed on the back side of the signal acquisition chip. The upper surface of the front redistribution layer substrate is electrically connected to the second interposer layer; the back redistribution layer substrate is electrically connected to the system platform. The dynamic random access memory is disposed above the second intermediary layer, and a memory signal transmission interface is provided between the dynamic random access memory and the second intermediary layer; the second intermediary layer is provided with a signal transmission interface.
[0009] In an optional implementation, the signal switching structure is a third intermediary layer; The signal acquisition chip and the dynamic random access memory are arranged side by side and spaced apart on the third interposer layer; The signal transmission interface is located near the signal acquisition chip in the third intermediary layer. The third intermediate layer has a conductive path inside, which is used to transmit the communication signal of the dynamic random access memory to the signal acquisition chip; The signal acquisition chip is connected to the external data processing system through the signal transmission interface; The third intermediary layer is connected to the system platform.
[0010] In an optional implementation, the signal switching structure is a fourth intermediary layer; the fourth intermediary layer is disposed between the system platform and the dynamic random access memory. The signal acquisition chip is integrated in the fourth intermediary layer; the signal acquisition chip is electrically connected to the system platform and the dynamic random access memory through the transmission interface of the fourth intermediary layer.
[0011] In an optional implementation, the signal acquisition chip integrates a control module, a signal sampling module, a digital signal acquisition module, and a signal transmission module. The control module is used to set the working mode and operating status of the signal acquisition chip; The signal sampling module is used to perform analog domain sampling on the communication signals transmitted between the dynamic random access memory and the system platform; The digital signal acquisition module is used to receive the analog sampling data output by the signal sampling module, perform data judgment, formatting and packaging, and generate data frames that conform to a preset protocol. The signal transmission module is used to receive the data frames output by the digital signal acquisition module and convert them into physical layer signals adapted to the signal transmission interface for output.
[0012] In an optional implementation, the signal sampling module includes: an address / command signal receiving unit, a clock signal receiving unit, a data strobe signal receiving unit, and a data signal receiving unit, each unit being used to receive the corresponding communication signal; The output of each receiving unit is connected to a multi-phase delay unit and a sampler. The multi-phase delay unit is configured to generate a delay signal with a preset number of phase offsets, and the sampler is configured to synchronously sample the corresponding communication signal based on the delay signal. The output of the sampler is connected to a serial-to-parallel converter, which is configured to convert the sampled high-speed serial data into a parallel data stream.
[0013] Secondly, this application provides a signal acquisition method, applied to the signal acquisition device described in any of the foregoing embodiments, the method comprising: The communication signal output from the dynamic random access memory is received through the first interface of the signal transfer structure. The communication signal is processed by the signal acquisition chip to generate a data frame; The data frame is output to the external data processing system in real time via the signal transmission interface of the signal acquisition chip.
[0014] The embodiments of this application have the following beneficial effects: By setting a first interface and a second interface in the signal transfer structure, with the first interface electrically connected to the dynamic random access memory (DRAM) and the second interface electrically connected to the system platform, the application can simultaneously access the communication signals transmitted between the DRAM and the system platform while maintaining the DRAM as normal system memory, thus achieving parallel and non-interfering signal acquisition and system operation. Since the first interface is directly electrically connected to the DRAM and the signal acquisition chip is electrically connected to the signal transfer structure, the communication signal is guided to the signal acquisition chip for processing after entering the signal transfer structure through the first interface. The entire path does not need to pass through external transfer components such as intermediate layer printed circuit boards, pads, or flexible cables, thereby shortening the transmission distance between the signal source (DRAM) and the receiver (signal acquisition chip). Attached Figure Description
[0015] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and therefore should not be considered as a limitation on the scope of protection of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 A schematic diagram of a signal acquisition device according to an embodiment of this application is shown; Figure 2a A longitudinal section view of the signal acquisition device according to the corresponding embodiment is shown; Figure 2b A top view of the dynamic random access memory corresponding to the embodiment is shown; Figure 2c A top view of the signal acquisition chip corresponding to the embodiment is shown; Figure 3 A schematic diagram of the signal switching structure corresponding to the embodiment is shown; Figure 4 A top view of the signal switching structure according to the corresponding embodiment is shown; Figure 5 A side view of the side connector according to the corresponding embodiment is shown; Figure 6 A schematic diagram of the signal acquisition device according to the corresponding embodiment is shown; Figure 7aA top view of the signal acquisition device according to the corresponding embodiment is shown; Figure 7b A side view of the signal acquisition device according to the corresponding embodiment is shown; Figure 8 A three-dimensional view of the signal acquisition device according to the corresponding embodiment is shown; Figure 9 A side view of the signal acquisition device according to the corresponding embodiment is shown; Figure 10 A schematic diagram of the internal integrated module of the signal switching structure according to an embodiment of this application is shown; Figure 11 A schematic diagram of a signal sampling module according to an embodiment of this application is shown; Figure 12 A schematic flowchart of a signal acquisition method according to an embodiment of this application is shown.
[0017] Key component symbols: 1-Dynamic Random Access Memory; 2-Signal Adapter Structure; 3-Signal Acquisition Chip; 4-External Data Processing System; 5-Through-hole in Mold; 6-Signal Transmission Interface; 7-Double-sided Slot Memory Module; 8-First Surface; 9-Second Surface; 10-Through-hole Memory Interface; 11-First Intermediate Layer; 12-Side Connector; 13-Contact Array; 14-Second Intermediate Layer; 15-Front Redistribution Layer Substrate; 16-Back Redistribution Layer Substrate; 17-Memory Signal Transmission Interface; 18-Padded Block; 19-Third Intermediate Layer; 20-Fourth Intermediate Layer; 21-Frequency Divider; 22- JEDEC interface; 23-System platform; 24-Control module; 25-Signal sampling module; 26-Digital signal acquisition module; 27-Signal transmission module; 28-Address / command signal receiving unit; 29-Clock signal receiving unit; 30-Data strobe signal receiving unit; 31-Data signal receiving unit; 32-Receiver; 33-Delay unit; 34-Sampler; 35-Serial-to-parallel converter. Detailed Implementation
[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0019] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0020] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.
[0021] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.
[0022] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0023] In a computer system, Dynamic Random Access Memory (DRAM) serves as the main memory, interacting with the system platform (such as the CPU and memory controller) at high speed via a standard JEDEC interface. To ensure system stability and performance, it is necessary to monitor and analyze the address, command, clock, data, and data strobe signals transmitted between the DRAM and the system platform in real time to quickly pinpoint the cause of failure.
[0024] Currently, the industry commonly uses external signal acquisition instruments (such as Logic Analyzers) or interposer PCB structures for debugging. Logic Analyzers connect to system platform test points via flexible cables or contact DRAM peripheral circuit traces via probes; interposer PCBs, on the other hand, place an interposer PCB under the DRAM, elevate it with pads, and then lead the signal to external acquisition equipment via flexible cables. However, both methods share common technical drawbacks: 1. Test points are typically large test solder joints extended from under the DRAM via a separate PCB (such as an interposer PCB), making it impossible to extract all the signals to be tested within a limited space; 2. Long cables are required to connect the test points to the signal receiving instrument, resulting in excessively long signal transmission paths and hindering effective sampling of high-frequency signals. Furthermore, existing solutions often integrate signal acquisition functions into system platforms or standalone instruments, with signal access points located far from the DRAM solder ball array. This makes it impossible to achieve in-situ signal measurement originating from the solder ball array at the bottom of the DRAM. However, the DRAM solder ball array is the only physical interface for electrical signal interaction with external circuits. Only by directly acquiring data from this point can the most accurate and timely chip-side signal characteristics be obtained, providing a reliable basis for failure analysis.
[0025] Based on this, this application proposes a signal acquisition device and method that can realize in-situ acquisition, short-distance transmission and real-time output of signals between DRAM and system platform without destroying the standard package of dynamic random access memory 1 and without changing the physical form of the JEDEC interface.
[0026] The signal acquisition device will be described below with reference to some specific embodiments.
[0027] Figure 1 A schematic diagram of a signal acquisition device according to an embodiment of this application is shown. Exemplarily, the signal acquisition device includes: a dynamic random access memory 1, a signal transfer structure 2, and a signal acquisition chip 3.
[0028] The signal transfer structure 2 is provided with a first interface and a second interface. The first interface can be composed of an array of solder ball receiving terminals, which is fully matched with the solder ball array of the dynamic random access memory 1 in terms of spatial location and electrical definition, and achieves a reliable electrical connection through physical contact; the second interface is a standard JEDEC memory interface, which is used to electrically connect with the system platform 23 to establish a normal communication link between the dynamic random access memory 1 and the system platform 23.
[0029] The signal transfer structure 2 is used to receive and transmit communication signals between the dynamic random access memory 1 and the system platform 23. After the communication signal is output from the solder ball array of the dynamic random access memory 1, it directly enters the signal transfer structure 2 through the first interface, avoiding the path of signal transfer through the intermediate layer printed circuit board, pad 18 and long-distance flexible cable in the prior art, so as to significantly shorten the transmission distance between the signal sending point (solder ball array) and the signal receiving point (input port of signal acquisition chip 3); the signal wiring network inside the signal transfer structure 2 guides the communication signal to the signal acquisition chip, and the signal acquisition chip performs analog domain sampling and preliminary digital processing on the communication signal.
[0030] The signal acquisition chip 3 is electrically connected to the signal conversion structure 2. Its input pads are bonded to the signal wiring network inside the signal conversion structure 2 via conductive bumps or gold wire bonding. Its output is electrically connected to the external data processing system 4 via the signal transmission interface 6. Therefore, the processed communication signal is transmitted to the external data processing system 4 in real time through this connection path, allowing the acquired data to be completely saved. Users can retrieve data from any time period for playback and in-depth analysis as needed, thereby quickly locating the root cause of system failure.
[0031] Since the first interface is directly electrically connected to the solder ball array of the dynamic random access memory 1, and the input pad of the signal acquisition chip 3 is directly connected to the signal wiring network inside the signal transfer structure 2, the signal acquisition point is close to the signal output source of the dynamic random access memory 1. The acquired signal truly reflects the actual working state of the internal circuit of the DRAM chip, rather than the distorted waveform after long-distance transmission.
[0032] This structure, through the one-to-one connection between the solder ball receiving terminal array and the through-design of the signal wiring network to connect all communication signal channels, can perform parallel acquisition of address, command, clock, data and data strobe signals across all channels, thereby making up for the shortcomings of logic analyzers or oscilloscopes that cannot capture all signals synchronously due to the limited number of channels. In this embodiment, all connections are achieved through standard packaging interconnection processes such as solder ball contacts, conductive bumps, or gold wire bonding. There is no need to cut, drill, or solder the package of the dynamic random access memory 1. The dynamic random access memory 1 can be reused intact after testing.
[0033] In some implementations, such as Figure 2a , Figure 2b and Figure 2c As shown ( Figure 2a This is a longitudinal section view of the signal acquisition device. Figure 2b This is a top view of Dynamic Random Access Memory 1. Figure 2c(Top view of the signal acquisition chip) The signal transfer structure 2 includes an in-mold via 5 structure with at least two in-mold vias 5. Each in-mold via 5 vertically penetrates the package of the dynamic random access memory 1. The upper end of each in-mold via 5 is electrically connected to the chip pad of the dynamic random access memory 1, and the lower end is electrically connected to the signal transfer structure 2. The signal acquisition chip 3 is mounted on the surface of the signal transfer structure 2. Its input pad is electrically connected to the corresponding wiring network on the signal transfer structure 2 through microbumps or gold wire bonding. Therefore, the signal from the dynamic random access memory 1 is led out through the in-mold vias 5 to the signal transfer structure 2, and then transmitted to the input terminal of the signal acquisition chip 3 through the wiring network inside the signal transfer structure 2, without passing through any printed circuit board traces or flexible cables. The signal transfer structure 2 has a signal transmission interface 6 on its side, which is electrically connected to both the input and output terminals of the signal acquisition chip 3. The communication signal from the dynamic random access memory 1 is transmitted to the input terminal of the signal acquisition chip 3 through the input channel of the signal transmission interface 6 via the internal wiring network of the signal transfer structure 2. The data frame generated by the signal acquisition chip 3 after sampling and processing the communication signal is transmitted to the external data processing system 4 in real time through the output channel of the signal transmission interface 6.
[0034] In this embodiment, the signal transmission process is as follows: the communication signal generated by the dynamic random access memory 1 is first output from the solder ball array at the bottom of its package; the signal enters the in-mold via 5 through the chip pads; the signal is transmitted downward along the in-mold via 5 to the input pad of the signal acquisition chip 3; the signal acquisition chip 3 samples and processes the received signal; the processed communication signal is transmitted to the signal transmission interface 6 through the output terminal of the signal acquisition chip 3; the signal transmission interface 6 outputs the signal to the external data processing system 4. Since the in-mold via 5 vertically penetrates the package of the dynamic random access memory 1, and its upper end is directly connected to the chip pads and its lower end is directly connected to the input pad of the signal acquisition chip 3, the signal does not need to pass through any interlayer printed circuit board, pad 18 or flexible cable. Therefore, the transmission path between the signal emission point (solder ball array) and the signal receiving point (input pad of the signal acquisition chip 3) is the shortest, thereby realizing the effective acquisition of high-speed communication signals between the dynamic random access memory 1 and the system platform 23.
[0035] This structure directly connects the upper end of the through-hole 5 to the chip pad and the lower end to the input pad of the signal acquisition chip 3, making the signal acquisition point close to the signal output source of the DRAM chip. The acquired signal truly reflects the actual working state of the internal circuit of the chip, rather than the distorted waveform after long-distance transmission, thus realizing in-situ signal measurement at the DRAM chip.
[0036] Because the in-mold via 5 structure constructs multiple independent conductive paths within the dynamic random access memory 1 package, and each path corresponds to a chip pad, it can perform parallel acquisition of address, command, clock, data, and data strobe signals across all channels, thereby compensating for the shortcomings of logic analyzers or oscilloscopes that cannot synchronously capture all signals due to the limited number of channels.
[0037] The signal acquisition chip 3 outputs the processed communication signal to the external data processing system 4 in real time via the signal transmission interface 6, so that the acquired data can be completely saved. Users can retrieve data from any time period for playback and in-depth analysis as needed, thereby quickly locating the root cause of system failure.
[0038] In some implementations, such as Figure 3 As shown, signal transfer structure 2 is a double-sided slot memory module 7. The double-sided slot memory module 7 is a rigid printed circuit board, and its dimensions, mounting holes and edge interface definitions all meet the JEDEC standard requirements for dual in-line memory modules (DIMMs), and can be directly inserted into the memory slots of standard server motherboards.
[0039] Furthermore, the Dynamic Random Access Memory (DRAM) 1 is mounted on the first surface 8 of the double-sided slot-type memory module 7, and the first surface 8 has multiple DRAM 1 slots; the signal acquisition chip 3 is mounted on the second surface 9 of the double-sided slot-type memory module 7, and the second surface 9 has multiple signal acquisition chip 3 slots; the first surface 8 and the second surface 9 are opposing surfaces, and they are physically connected and electrically isolated through the substrate of the double-sided slot-type memory module 7. The DRAM 1 slots and the signal acquisition chip 3 slots can be flexible probe-type structures, which can form reliable, low-impedance physical contacts with the solder ball array of the DRAM 1 and the pads of the signal acquisition chip 3.
[0040] The double-sided slot-type memory module 7 has a conductive path inside that connects the dynamic random access memory 1 and the signal acquisition chip 3. This conductive path is a conductive line printed inside the substrate. Its starting point is the contact of the dynamic random access memory 1 slot on the first surface 8, and its ending point is the contact of the signal acquisition chip 3 slot on the second surface 9. This conductive path only undertakes the function of transmitting the communication signal output by the dynamic random access memory 1 to the input terminal of the signal acquisition chip 3.
[0041] It should be noted that the communication signal output by the dynamic random access memory 1 has two independent transmission paths: first, it is transmitted to the signal acquisition chip 3 via the aforementioned conductive path for real-time acquisition and analysis; second, it is transmitted directly from the DRAM slot contacts on the first surface 8 to the memory direct-access interface 10 (DIMM gold fingers) via another set of conductive paths inside the double-sided slot memory module 7, for transmitting the communication signal to the system platform 23 to maintain the normal operation of the dynamic random access memory 1 as system memory. The double-sided slotted memory module 7 has a memory direct-insertion interface 10 at one end, which can be a standard DIMM gold finger. Its contact number, arrangement and electrical characteristics fully comply with the JEDEC specification and are used for electrical connection with the system platform 23. The other end has a signal transmission interface 6, which is a high-speed serial interface and is used for electrical connection with the external data processing system 4. In this embodiment, the signal transmission process is as follows: the communication signal generated by the dynamic random access memory 1 is output from its bottom solder ball array and enters the slot contact of the dynamic random access memory 1 on the first surface 8; the signal is transmitted to the slot contact of the signal acquisition chip 3 on the second surface 9 through the conductive path inside the double-sided slot memory module 7; the signal enters the input terminal of the signal acquisition chip 3; the signal acquisition chip 3 samples and processes the received signal; the processed communication signal is transmitted to the signal transmission interface 6 at the other end of the double-sided slot memory module 7 through the output terminal of the signal acquisition chip 3; the signal transmission interface 6 outputs the signal to the external data processing system 4. Since the conductive path is located inside the double-sided slot-type memory module 7 substrate, and the dynamic random access memory 1 and the signal acquisition chip 3 are connected through opposing surface slots on the same rigid substrate, the signal does not need to pass through external conversion components such as the interlayer printed circuit board, pad 18 or flexible cable. Therefore, the transmission path between the signal emission point (the solder ball array of the dynamic random access memory 1) and the signal reception point (the input terminal of the signal acquisition chip 3) remains compact and direct, thereby realizing the effective acquisition of high-speed communication signals between the dynamic random access memory 1 and the system platform 23.
[0042] This structure places the dynamic random access memory 1 and the signal acquisition chip 3 on opposite surfaces of the same rigid substrate and connects them through an internal conductive path of the substrate. This makes the signal acquisition point physically adjacent to the dynamic random access memory 1. The acquired signal truly reflects the actual working state of the DRAM chip, rather than the distorted waveform after long-distance transmission, thus realizing in-situ signal measurement at the DRAM chip.
[0043] Since the conductive path inside the double-sided slot memory module 7 connects all communication signal channels, and the dynamic random access memory 1 and the signal acquisition chip 3 are both connected through a standard slot interface, the address, command, clock, data and data strobe signals can be acquired in parallel across all channels, thus making up for the shortcomings of logic analyzers or oscilloscopes that cannot capture all signals synchronously due to the limited number of channels.
[0044] Both the dynamic random access memory 1 and the signal acquisition chip 3 are slot-mounted, and all connections are achieved through physical contact between elastic probes and solder balls or pads. There is no need to cut, drill, or solder the package of the dynamic random access memory 1. The dynamic random access memory 1 can be reused perfectly after testing.
[0045] The signal acquisition chip 3 outputs the processed communication signal to the external data processing system 4 in real time via the signal transmission interface 6 on the double-sided slot memory module 7, so that the acquired data can be completely saved. Users can retrieve data from any time period for playback and in-depth analysis as needed, thereby quickly locating the root cause of system failure.
[0046] In some embodiments, such as Figure 4 (Top view of signal transfer structure 2) and Figure 5 As shown in the side view of the side connector 12, the signal conversion structure 2 includes a first interposer layer 11 and a side connector 12. The first interposer layer 11 is an interposer printed circuit board with a first JEDEC standard interface on its upper surface that matches the solder ball array of the dynamic random access memory 1, and a second JEDEC standard interface on its lower surface that matches the system platform 23. The first interposer layer 11 is mounted on the system platform 23 through the second JEDEC standard interface on its lower surface. The dynamic random access memory 1 is electrically connected to the first JEDEC standard interface on the upper surface of the first interposer layer 11 through its bottom solder ball array and is mounted on the first interposer layer 11. The side connector 12 is a frame structure surrounding the periphery of the dynamic random access memory 1, and its inner wall is provided with a contact array 13. The contact array 13 is arranged in a ring, corresponding to the position of the outer area of the solder ball array of the dynamic random access memory 1. The signal acquisition chip 3 is mounted on the top of the side connector 12, and an input pad is provided at the bottom. The input port of the signal acquisition chip 3 can be electrically connected to the pad array on the top of the side connector 12 through gold wire bonding or flip-chip bonding. The pad array on the top of the side connector 12 is electrically connected to the contact array 13 on the inner wall through a vertical conductive through-hole inside the side connector 12. Therefore, the input port of the signal acquisition chip 3 is electrically connected to the contact array 13 through the conductive path inside the side connector 12.
[0047] The solder ball array of the dynamic random access memory 1 and the contact array 13 of the side connector 12 are electrically connected through edge field coupling or microbumps. In edge field coupling mode, the signal can be transmitted through capacitive coupling between the solder ball and the contact; in microbump mode, the signal can be physically connected through micro metal bumps pre-placed on the surface of the solder ball or the surface of the contact.
[0048] In this embodiment, the signal transmission process can be as follows: the communication signal generated by the dynamic random access memory 1 is output from its bottom solder ball array; the signal is electrically connected to the contact array 13 on the inner wall of the side connector 12 through edge field coupling or micro bumps; the signal is transmitted to the input port of the signal acquisition chip 3 through the vertical conductive via and the top solder pad array inside the side connector 12; the signal acquisition chip 3 samples and processes the received signal; the processed communication signal is transmitted to the signal transmission interface 6 through the output terminal of the signal acquisition chip 3; the signal transmission interface 6 outputs the signal to the external data processing system 4. Since the side connector 12 is a frame structure surrounding the periphery of the dynamic random access memory 1, and its contact array 13 corresponds to the position of the outer area of the solder ball array, the signal is directly connected to the side of the DRAM package through edge field coupling or micro bumps, without needing to penetrate the package or pass through the interlayer printed circuit board, pad 18 and flexible cable. Therefore, the transmission path between the signal sending point (dynamic random access memory 1) and the signal receiving point (signal acquisition chip 3) remains short and direct, thereby realizing the effective acquisition of high-speed communication signals between the dynamic random access memory 1 and the system platform 23.
[0049] This structure constructs a signal access channel on the periphery of the dynamic random access memory 1 package body through the side connector 12, so that the signal acquisition point is close to the physical boundary of the DRAM package body. The acquired signal truly reflects the actual working state of the DRAM chip, rather than the distorted waveform after long-distance transmission, thus realizing in-situ signal measurement at the DRAM chip.
[0050] Furthermore, since the contact array 13 on the inner wall of the side connector 12 is arranged in a ring and covers the entire peripheral area of the solder ball array, it can perform parallel acquisition of address, command, clock, data and data strobe signals across all channels, thereby making up for the shortcomings of logic analyzers or oscilloscopes that cannot capture all signals synchronously due to the limited number of channels.
[0051] In addition, the signal acquisition chip 3 outputs the processed communication signal to the external data processing system 4 in real time via the signal transmission interface 6, so that the acquired data can be completely saved. Users can retrieve data from any time period for playback and in-depth analysis as needed, thereby quickly locating the root cause of system failure. In some implementations, such as Figure 6As shown, the signal switching structure 2 is a second interposer layer 14. This second interposer layer 14 can be an interposer printed circuit board, with a first JEDEC standard interface on its upper surface that matches the solder ball array of the dynamic random access memory 1, and a second JEDEC standard interface on its lower surface that matches the front redistribution layer substrate 15; the second interposer layer 14 is connected to the front redistribution layer substrate 15 through its lower surface; the dynamic random access memory 1 is disposed above the second interposer layer 14, and its bottom solder ball array is electrically connected to the first JEDEC standard interface on the upper surface of the second interposer layer 14. A signal acquisition chip 3 is disposed between the second interposer layer 14 and the system platform 23. A front redistribution layer substrate 15 is disposed on the front side of the signal acquisition chip 3, and a back redistribution layer substrate 16 is disposed on the back side of the signal acquisition chip 3. The upper surface of the front redistribution layer substrate 15 is electrically connected to the second interposer layer 14; the back redistribution layer substrate 16 is electrically connected to the system platform 23. A memory signal transmission interface 17 is disposed between the dynamic random access memory 1 and the second interposer layer 14. The memory signal transmission interface 17 is used to transmit the JEDEC standard communication signals output by the dynamic random access memory 1 to the second interposer layer 14. The second interposer layer 14 divides the received communication signals into two paths: one path is transmitted through its internal wiring network to the system platform 23 via the back redistribution layer substrate 16 to maintain normal data communication between the dynamic random access memory 1 and the system platform 23; the other path is transmitted through its internal wiring network to the input terminal of the signal acquisition chip 3 via the front redistribution layer substrate 15 to realize real-time acquisition of communication signals between the dynamic random access memory DRAM and the system platform. The signal transmission interface 6 is located on the second intermediary layer 14 and is used to transmit the data frames processed by the signal acquisition chip 3 to the external data processing system 4. In this embodiment, the signal transmission process can be as follows: the communication signal generated by the dynamic random access memory 1 is output from its bottom solder ball array and enters the second interposer layer 14; the second interposer layer 14 splits the received communication signal, one path is transmitted through its internal wiring network to the system platform 23 via the back redistribution layer substrate 16 to maintain normal data communication between the dynamic random access memory 1 and the system platform 23; the other path is transmitted through its internal wiring network to the input terminal of the signal acquisition chip 3 via the front redistribution layer substrate 15 to realize real-time acquisition of communication signals between the DRAM and the system platform; after sampling and processing the received signal, the signal acquisition chip 3 generates a data frame containing timestamp and verification information, and outputs it to the front redistribution layer substrate 15 via its output terminal; the data frame is further converged to the signal transmission interface 6 through the internal wiring network of the second interposer layer 14, and is unidirectionally output to the external data processing system 4 via the interface. It should be noted that all communication signals from the Dynamic Random Access Memory 1, regardless of whether they ultimately go to the system platform 23 or the signal acquisition chip 3, enter the second interposer layer 14 through the memory signal transmission interface 17. The signal transmission interface 6 only handles the output of the processing results from the signal acquisition chip 3 and does not participate in the input or distribution of any raw DRAM signals. Since the DRAM signals are accessed and split within the second interposer layer 14, the input terminal of the signal acquisition chip 3 is adjacent to the memory signal transmission interface 17, and all interconnection paths are integrated into the high-density wiring network inside the second interposer layer 14. This eliminates the need for external adapters such as interposer printed circuit boards, pads, or flexible cables. Therefore, the transmission path between the signal emission point (the solder ball array of the Dynamic Random Access Memory 1) and the signal reception point (the input terminal of the signal acquisition chip 3) is the shortest, impedance matching is good, and timing jitter is controllable. This achieves high-fidelity, low-latency, and full-channel parallel acquisition of high-speed communication signals between the Dynamic Random Access Memory 1 and the system platform 23. Furthermore, this structure places the signal acquisition chip 3 between the dynamic random access memory 1 and the system platform 23, and provides a direct access channel through the memory signal transmission interface 17 on the second intermediary layer 14, so that the signal acquisition point is located at the physical boundary between the dynamic random access memory 1 (DRAM) and the system interface. The acquired signal truly reflects the actual working state of the DRAM chip, rather than the distorted waveform after long-distance transmission, thereby realizing in-situ signal measurement at the DRAM chip.
[0052] In addition, since the second intermediary layer 14 is provided with an independent memory signal transmission interface 17, and this interface is connected to all communication signal channels, it can perform parallel acquisition of address, command, clock, data and data strobe signals across all channels, thereby making up for the shortcomings of logic analyzers or oscilloscopes that cannot capture all signals synchronously due to the limited number of channels.
[0053] Similarly, in this embodiment, the signal acquisition chip 3 outputs the processed communication signal to the external data processing system 4 in real time via the signal transmission interface 6, so that the acquired data can be completely saved. Users can retrieve data from any time period for playback and in-depth analysis as needed, thereby quickly locating the root cause of system failure.
[0054] In some implementations, such as Figure 7a , Figure 7b As shown ( Figure 7a This is a top view. Figure 7b (Side view) The signal transfer structure 2 is the third interposer layer 19. The third interposer layer 19 is a rigid printed circuit board with dimensions compatible with standard memory modules, adaptable to the installation space of the existing system platform 23. The signal acquisition chip 3 and the dynamic random access memory 1 are arranged side-by-side on the third interposer layer 19, located on the same plane and maintaining a physical isolation distance to avoid mutual electrical interference. The dynamic random access memory 1 is electrically connected to the pad array on the upper surface of the third interposer layer 19 through its bottom solder ball array; the signal acquisition chip 3 is electrically connected to another set of pad arrays on the upper surface of the third interposer layer 19 through its bottom pads.
[0055] The third interposer layer 19 has a signal transmission interface 6 located near the signal acquisition chip 3. This signal transmission interface 6 is a high-speed serial interface used for electrical connection with the external data processing system 4. The third interposer layer 19 contains a conductive path, which is a conductive line printed inside the substrate. The path originates at the contacts of the dynamic random access memory 1 pad array and ends at the contacts of the signal acquisition chip 3 pad array, used to transmit communication signals from the dynamic random access memory 1 to the input terminal of the signal acquisition chip 3.
[0056] The third interposer 19 can be directly electrically connected to the system platform 23, or indirectly connected to the system platform 23 through a circuit pass pad 18. The circuit pass pad 18 is a rigid support structure with a signal pass hole that penetrates its thickness. The signal pass hole is filled with conductive material and forms an electrical connection path that matches the pads of the third interposer 19 and the interface of the system platform 23. Its function is to raise the third interposer 19 to a height higher than the dynamic random access memory 1 package to accommodate limited installation space, and at the same time provide a low-impedance, high-fidelity signal pass path between the third interposer 19 and the system platform 23. All communication signals are transmitted through the conductive path inside the third interposer 19 or the signal pass hole in the circuit pass pad 18.
[0057] In this embodiment, the signal transmission process can be as follows: the communication signal generated by the dynamic random access memory 1 is output from its bottom solder ball array and enters the pad array on the upper surface of the third interposer 19; the signal is transmitted to the input terminal of the signal acquisition chip 3 via the conductive path inside the third interposer 19; the signal acquisition chip 3 samples and processes the received signal; the processed communication signal is transmitted to the signal transmission interface 6 on the third interposer 19 via the output terminal of the signal acquisition chip 3; the signal transmission interface 6 outputs the signal to the external data processing system 4. Since the dynamic random access memory 1 and the signal acquisition chip 3 are arranged side by side on the same rigid substrate, and the signal is transmitted directly through the conductive path inside the substrate without the need for external adapter components such as the interposer printed circuit board, pad 18, or flexible cable, the transmission path between the signal sending point (dynamic random access memory 1) and the signal receiving point (signal acquisition chip 3) remains short and direct, thereby realizing the effective acquisition of high-speed communication signals between the dynamic random access memory 1 and the system platform 23.
[0058] It can be understood that this structure sets the dynamic random access memory 1 and the signal acquisition chip 3 on the same substrate plane and achieves electrical interconnection through the conductive path inside the substrate, so that the signal acquisition point is physically adjacent to the dynamic random access memory 1. The acquired signal truly reflects the actual working state of the DRAM chip, rather than the distorted waveform after long-distance transmission, thereby realizing in-situ signal measurement at the DRAM chip. In addition, since the conductive path inside the third interposer layer 19 connects all communication signal channels, and the dynamic random access memory 1 and the signal acquisition chip 3 are both connected through the pad array, the address, command, clock, data and data strobe signals can be acquired in parallel across all channels, thereby making up for the shortcomings of logic analyzers or oscilloscopes that cannot capture all signals synchronously due to the limited number of channels.
[0059] Similarly, in this embodiment, the signal acquisition chip 3 outputs the processed communication signal to the external data processing system 4 in real time via the signal transmission interface 6 on the third intermediary layer 19, so that the acquired data can be completely saved. Users can retrieve data from any time period for playback and in-depth analysis as needed, thereby quickly locating the root cause of system failure.
[0060] In some implementations, such as Figure 8 and Figure 9 As shown ( Figure 8 For 3D views, Figure 9(This is a side view) The signal transfer structure 2 is the fourth intermediary layer 20. The fourth intermediary layer 20 can be an active sampling intermediary layer. The fourth intermediary layer 20 is disposed between the system platform 23 and the dynamic random access memory 1. Its upper surface is electrically connected to the dynamic random access memory 1, and its lower surface is electrically connected to the system platform 23.
[0061] The signal acquisition chip 3 is integrated in the fourth intermediary layer 20. The communication signals between the dynamic random access memory 1 and the system platform 23 are all transmitted through the JEDEC interface 22 and the wiring network within the fourth intermediary layer 20. The communication signals that need to be acquired are distributed to the input terminal of the signal acquisition chip 3 by the fourth intermediary layer 20. The communication signals that do not need to be acquired are directly transmitted within the fourth intermediary layer 20 and do not enter the signal acquisition chip 3. Therefore, the signal acquisition chip 3 only samples and processes the address, command, clock, data and data strobe signals that are actually interacting between the DRAM and the system platform in real time. All unselected signal paths maintain zero intervention and zero delay load, thereby achieving high-fidelity monitoring of critical communication links without affecting the normal operation of the system. In this embodiment, the signal transmission process can be as follows: the communication signal generated by the dynamic random access memory 1 enters the fourth intermediary layer 20 via the JEDEC interface 22 on the fourth intermediary layer 20; the fourth intermediary layer 20 divides the communication signal into two paths: one path is transmitted through its internal wiring network to the system platform 23; the other path is transmitted through its internal wiring network to the input terminal of the signal acquisition chip 3; the data frame processed by the signal acquisition chip 3 is output to the external data processing system 4 via the signal transmission interface 6 on the fourth intermediary layer 20. Since the fourth intermediary layer 20 is located between the system platform 23 and the dynamic random access memory 1, and the signal acquisition chip 3 is integrated inside the fourth intermediary layer 20, the signal does not need to pass through external adapter components such as the intermediary layer printed circuit board, pad 18, or flexible cable. Therefore, the transmission path between the signal sending point (dynamic random access memory 1) and the signal receiving point (signal acquisition chip 3) remains the shortest and most direct, thereby realizing the effective acquisition of high-speed communication signals between the dynamic random access memory 1 and the system platform 23.
[0062] In addition, the signal acquisition chip 3 outputs the processed communication signal to the external data processing system 4 in real time through the signal transmission interface 6 on the fourth intermediary layer 20, so that the acquired data can be completely saved. Users can retrieve data from any time period for playback and in-depth analysis as needed, thereby quickly locating the root cause of system failure.
[0063] In this embodiment, the signal acquisition chip integrates a control module 24, a signal sampling module 25, a digital signal acquisition module 26, and a signal transmission module 27. The control module 24 is used to set the working mode and operating status of the signal acquisition chip 3; the signal sampling module 25 is used to perform analog domain sampling of the communication signals transmitted between the dynamic random access memory 1 and the system platform 23; the digital signal acquisition module 26 is used to receive the analog sampling data output by the signal sampling module 25, perform data judgment, formatting and packaging, and generate data frames that conform to a preset protocol; the signal transmission module 27 is used to receive the data frames output by the digital signal acquisition module 26 and convert them into physical layer signals that are compatible with the signal transmission interface 6 for output.
[0064] Furthermore, such as Figure 11 As shown, the signal sampling module 25 includes: an address / command signal receiving unit 28, a clock signal receiving unit 29, a data strobe signal receiving unit 30, and a data signal receiving unit 31. Each unit is used to receive the address signal, command signal, clock signal, data strobe signal, and data signal defined by the JEDEC standard, respectively. The output of each receiving unit is connected to a multi-phase delay unit 33 and a sampler 34 and / or a frequency divider 21 through a receiver 32. The multi-phase delay unit 33 is configured to generate a delay signal with a preset number of phase offsets. The sampler 34 is configured to synchronously sample the corresponding communication signal based on the delay signal. The frequency divider 21 is configured to divide the clock signal to generate a low-frequency clock adapted to the sampler 34 and the serial-to-parallel converter 35. The output of the sampler 34 is connected to a serial-to-parallel converter 35. The serial-to-parallel converter 35 is configured to convert the sampled high-speed serial data into a parallel data stream.
[0065] The signal transmission and processing process is as follows: The communication signal generated by the dynamic random access memory 1 is input into the signal transfer structure 2 via the first interface of the signal transfer structure 2; the communication signal is allocated to the corresponding receiving unit in the signal sampling module 25; the address / command signal receiving unit 28 receives the address and command signals, the clock signal receiving unit 29 receives the differential clock signal, the data strobe signal receiving unit 30 receives the data strobe signal, and the data signal receiving unit 31 receives the data signal; the signals output by each receiving unit are respectively sent to the corresponding multi-phase delay unit 33, sampler 34, and frequency divider 21 for multi-phase synchronous sampling; the sampler 34 outputs high-speed serial sampling data, which is converted into a parallel data stream via the serial-to-parallel converter 35; the parallel data stream is sent to the digital signal acquisition module 26 for data validity judgment, formatting and packaging, and generating a standard data frame containing a timestamp, channel identifier, and checksum; the data frame is sent to the signal transmission module 27 and converted into a physical layer signal adapted to the signal transmission interface 6; the physical layer signal is output to the external data processing system 4 via the signal transmission interface 6. Since the signal sampling module 25, the digital signal acquisition module 26, and the signal transmission module 27 are all integrated inside the signal transfer structure 2, and the modules are directly connected through a dedicated internal wiring network, the signal does not need to pass through an external circuit board or long-distance interconnection between discrete chips. Therefore, the overall path of the signal from the solder ball array of the dynamic random access memory 1 to the final output terminal of the signal acquisition chip 3 remains compact and controllable, thereby realizing the effective acquisition and reliable transmission of high-speed communication signals between the dynamic random access memory 1 and the system platform 23.
[0066] It is understood that this embodiment integrates a multi-channel receiving unit and a multi-phase synchronous sampling circuit inside the signal acquisition chip, so that the signal acquisition point is close to the access position of the signal transfer structure 2. The acquired signal truly reflects the original timing and level characteristics of the output signal at the DRAM chip end, rather than the distorted waveform reconstructed by external circuits, thereby realizing in-situ signal measurement at the DRAM chip end.
[0067] Since the signal sampling module 25 includes four independent receiving units: address / command, clock, data strobe, and data, and each unit is equipped with a multi-phase delay unit 33, a sampler 34, and a frequency divider 21, it can perform full-channel parallel acquisition and synchronous processing of all communication signal types defined by the JEDEC standard, thereby making up for the shortcomings of logic analyzers or oscilloscopes that cannot synchronously capture all signals due to the limited number of channels.
[0068] Figure 12 A schematic flowchart of a signal acquisition method according to an embodiment of this application is shown. Exemplarily, this signal acquisition method is applied to the aforementioned signal acquisition device, and the method includes: Step S100: Receive the communication signal output from the dynamic random access memory 1 through the first interface of the signal transfer structure 2; Step S200: After processing the communication signal by the signal acquisition chip 3, a data frame is generated; In step S300, the data frame is output to the external data processing system 4 in real time via the signal transmission interface 6 of the signal acquisition chip 3.
[0069] It is understood that the options in the above embodiments also apply to this embodiment, so they will not be described again here.
[0070] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0071] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0072] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0073] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A signal acquisition device, characterized in that, include: Dynamic random access memory, signal switching structure, and signal acquisition chip; The signal transfer structure is provided with a first interface and a second interface. The first interface is used to be electrically connected to the dynamic random access memory, and the second interface is used to be electrically connected to the system platform. The signal switching structure is used to receive and transmit communication signals transmitted between the dynamic random access memory and the system platform; The signal acquisition chip is electrically connected to the signal transfer structure and is used to receive the communication signal transmitted from the signal transfer structure, sample and process the communication signal, and then transmit the processed communication signal to an external data processing system through the signal transmission interface. The signal switching structure includes a first intermediary layer and a side connector; The first intermediary layer is installed on the system platform; the dynamic random access memory is installed on the first intermediary layer. The side connector is a frame structure surrounding the periphery of the dynamic random access memory, and its inner wall is provided with a contact array. The signal acquisition chip is mounted on the top of the side connector, and the input port of the signal acquisition chip is electrically connected to the first interposer through the contact array of the side connector. The solder ball array of the dynamic random access memory and the contact array of the side connector are electrically connected through microbumps.
2. The signal acquisition device according to claim 1, characterized in that, The signal switching structure includes an in-mold through-hole structure with at least two in-mold through holes; Each of the in-mold vias vertically penetrates the package of the dynamic random access memory (DRAM). The upper end of each of the in-mold vias is electrically connected to the chip pads of the DRAM, and the lower end is electrically connected to the signal transfer structure. The signal conversion structure is also provided with a signal transmission interface, which is electrically connected to the input and output terminals of the signal acquisition chip.
3. The signal acquisition device according to claim 1, characterized in that, The signal transfer structure is a double-sided slot-type memory module; The dynamic random access memory is mounted on the first surface of the double-sided slot memory module, and the signal acquisition chip is mounted on the second surface of the double-sided slot memory module; The first surface and the second surface are opposite surfaces; The double-sided slotted memory module has an internal conductive path for transmitting the communication signal of the dynamic random access memory to the input terminal of the signal acquisition chip; The dual-sided slotted memory module has a memory direct-insertion interface at one end for electrical connection to the system platform; and a signal transmission interface at the other end for electrical connection to an external data processing system.
4. The signal acquisition device according to claim 1, characterized in that, The signal switching structure is a second intermediary layer; The signal acquisition chip is disposed between the second intermediary layer and the dynamic random access memory; A front redistribution layer substrate is disposed on the front side of the signal acquisition chip, and a back redistribution layer substrate is disposed on the back side of the signal acquisition chip. The upper surface of the front redistribution layer substrate is electrically connected to the second interposer layer; the back redistribution layer substrate is electrically connected to the system platform. The dynamic random access memory is disposed above the second intermediary layer, and a memory signal transmission interface is provided between the dynamic random access memory and the second intermediary layer; the second intermediary layer is provided with a signal transmission interface.
5. The signal acquisition device according to claim 1, characterized in that, The signal switching structure is a third intermediary layer; The signal acquisition chip and the dynamic random access memory are arranged side by side and spaced apart on the third interposer layer; The signal transmission interface is located near the signal acquisition chip in the third intermediary layer. The third intermediate layer has a conductive path inside, which is used to transmit the communication signal of the dynamic random access memory to the signal acquisition chip; The signal acquisition chip is connected to the external data processing system through the signal transmission interface; The third intermediary layer is connected to the system platform.
6. The signal acquisition device according to claim 1, characterized in that, The signal switching structure is a fourth intermediary layer; the fourth intermediary layer is disposed between the system platform and the dynamic random access memory. The signal acquisition chip is integrated in the fourth intermediary layer; The signal acquisition chip is electrically connected to the system platform and the dynamic random access memory through the transmission interface of the fourth intermediary layer.
7. The signal acquisition device according to claim 6, characterized in that, The signal acquisition chip integrates a control module, a signal sampling module, a digital signal acquisition module, and a signal transmission module. The control module is used to set the working mode and operating status of the signal acquisition chip; The signal sampling module is used to perform analog domain sampling on the communication signals transmitted between the dynamic random access memory and the system platform. The digital signal acquisition module is used to receive the analog sampling data output by the signal sampling module, perform data judgment, formatting and packaging, and generate data frames that conform to a preset protocol. The signal transmission module is used to receive the data frames output by the digital signal acquisition module and convert them into physical layer signals adapted to the signal transmission interface for output.
8. The signal acquisition device according to claim 7, characterized in that, The signal sampling module includes: an address / command signal receiving unit, a clock signal receiving unit, a data strobe signal receiving unit, and a data signal receiving unit, each unit being used to receive the corresponding communication signal; The output of each receiving unit is connected to a multi-phase delay unit and a sampler. The multi-phase delay unit is configured to generate a delay signal with a preset number of phase offsets, and the sampler is configured to synchronously sample the corresponding communication signal based on the delay signal. The output of the sampler is connected to a serial-to-parallel converter, which is configured to convert the sampled high-speed serial data into a parallel data stream.
9. A signal acquisition method, characterized in that, The method, applied to the signal acquisition device according to any one of claims 1 to 8, comprises: The communication signal output from the dynamic random access memory is received through the first interface of the signal transfer structure. The communication signal is processed by the signal acquisition chip to generate a data frame; The data frame is output to the external data processing system in real time via the signal transmission interface of the signal acquisition chip.