A data transmission method, an electronic device, and a storage medium

Abstract

The application provides a data transmission method, an electronic device and a storage medium, and relates to the technical field of communication control; the method comprises the following steps: a processor chip is connected with an external device interface through an adapter module; if the external device connected with the external device interface is a master device, the adapter module receives first interaction data sent by the processor chip, and the first interaction data is data sent to the external master device; the adapter module buffers the first interaction data, so that the external master device reads the first interaction data from the adapter module; conversely, when the external master device sends second interaction data to the processor chip, the adapter module buffers the second interaction data, so that the processor chip reads the second interaction data from the adapter module. The application enables the processor chip and the external master device to not directly perform data interaction through the adapter module, and solves the problem that two master devices cannot perform data interaction.

Description

Technical Field

[0001] This application relates to the field of communication control technology, and in particular to a data transmission method, electronic device and storage medium. Background Technology

[0002] The processor chip is the core of an electronic device, responsible for controlling the operation of various modules within it. As technology advances, electronic devices become increasingly powerful. To achieve different functions, the processor chip connects to different slave device modules, controlling these modules to perform various data processing operations and realize different functions. Furthermore, to interact with external devices, electronic devices are equipped with external device interfaces, through which external devices connect to the electronic device.

[0003] If the external device connected to the processor chip via the external device interface is a master device, then during data interaction, the processor chip needs to act as a slave chip to interact with the external device. However, when the processor chip interacts with the slave device module, it also acts as a master chip to interact with the slave device module. At this time, there is a conflict between the master and slave roles of the processor chip, which affects the interaction between the processor chip and the external device. Summary of the Invention

[0004] This application provides a data transmission method, electronic device, and storage medium, which can solve the problem that when a processor chip interacts with both a slave device module and an external master device simultaneously, the conflict between the master and slave roles of the processor chip causes the processor chip and the external device to be unable to interact.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, this application provides a data transmission method, comprising: applied to an electronic device, the electronic device including a processor chip, an external device interface and an adapter module, wherein a first communication interface of the processor chip is connected to a third port of the adapter module, a first port of the adapter module is connected to the external device interface, and the processor chip is a main chip;

[0007] The methods include:

[0008] When the first external device connected to the external device interface is the master device, the adapter module receives the first interactive data sent by the processor chip;

[0009] If the first interaction data is data sent to the first external device, the switching module caches the first interaction data so that the first external device can read the first interaction data from the switching module.

[0010] In this application, the control processor chip always remains the master chip to solve the problem of conflicting master and slave roles when the processor chip interacts with both the slave device module and the external master device simultaneously. In addition, this application sets up a switching module. When the external device interface is connected to the master device and the processor chip sends the first interaction data to the external master device, the switching module buffers the first interaction data sent by the processor chip. The external master device reads the first interaction data from the switching module, so that the processor chip, as the master chip, does not directly interact with the external master device, thus solving the problem that the two master devices cannot interact and enabling the processor chip, as the master chip, to transmit data with the external master device.

[0011] As another implementation of the first aspect, when the first external device connected to the external device interface is the master device, the method further includes:

[0012] The switching module receives the second interactive data sent by the first external device;

[0013] If the second interactive data is data sent to the processor chip, the switching module caches the second interactive data so that the processor chip can read the second interactive data from the switching module.

[0014] In this application, when the external host device sends the second interactive data to the processor chip, the switching module buffers the second interactive data sent by the external host device, and the processor chip reads the second interactive data from the switching module, so that the processor chip, which is the host chip, does not interact directly with the external host device, thus solving the problem that the two host devices cannot interact, and enabling the processor chip, which is the host chip, to transmit data with the external host device.

[0015] As another implementation of the first aspect, the electronic device further includes a first slave device module, and the second port of the adapter module is connected to the first slave device module;

[0016] When the first external device connected to the external device interface is the master device, the method further includes:

[0017] The switching module receives third interactive data sent by the processor chip;

[0018] If the third interactive data is data sent to the first slave device module, the switching module sends the third interactive data to the first slave device module.

[0019] In this application, when the external device is the master device, if the adapter module is connected to the first slave device module, the adapter module can directly send the third interactive data sent by the processor chip to the first slave device module to the first slave device module, so that the processor chip can interact with both the external master device and the first slave device module at the same time, thus solving the problem of the conflict between the master and slave roles of the processor chip when it interacts with both the slave device module and the external master device at the same time.

[0020] As another implementation of the first aspect, the electronic device further includes a port controller and a port manager;

[0021] When the first external device connected to the external device interface is the master device, before the adapter module receives the first interactive data sent by the processor chip, the method further includes:

[0022] The port controller detects that the external device interface is connected to the first external device, and detects that the first external device is the master device;

[0023] The port controller sends a first device access message to the port manager, wherein the first device access message indicates that the first external device connected to the external device interface is a master device;

[0024] After receiving the first device access message, the port manager generates a first management policy for the external device interface. The first management policy is used to instruct the external device interface to start a data transmission mode for data transmission.

[0025] In this application, an electronic device is equipped with a port controller to detect the device information of the external device connected to the external device interface, and then the port manager manages the external device interface so that the external device interface switches to different functions according to different external devices.

[0026] As another implementation of the first aspect, after the port manager receives the first device access message, the method further includes:

[0027] The port manager sends a data caching instruction to the switching module, wherein the data caching instruction is used to instruct the switching module to start a data caching mode, which is a mode for caching the interaction data between the processor chip and the first external device;

[0028] After receiving the data caching instruction, the switching module enters the data caching mode.

[0029] In this application, when the external device interface is connected to the master device, the port manager sends a data caching instruction to the adapter module to switch the adapter module to data caching mode. This allows the processor chip to cache data when interacting with the external master device, thus avoiding the problem of the processor chip and the external master device being unable to interact.

[0030] As another implementation of the first aspect, the switching module includes a buffer and an interface controller, the buffer and the interface controller being connected together, and the method further includes:

[0031] When the first external device connected to the external device interface is the master device, the interface controller receives the first interactive data sent by the processor chip;

[0032] If the first interactive data is data sent to the first external device, the interface controller sends the first interactive data to the buffer;

[0033] After receiving the first interactive data, the buffer caches the first interactive data so that the first external device can read the first interactive data from the buffer.

[0034] The interface controller receives the second interactive data sent by the first external device;

[0035] If the second interactive data is data sent to the processor chip, the interface controller sends the second interactive data to the buffer;

[0036] After receiving the second interactive data, the buffer caches the second interactive data so that the processor chip can read the second interactive data from the buffer.

[0037] In this application, a buffer is set in the switching module to cache data. In addition, an interface controller is set in the switching module so that the switching module can determine the transmission direction of the received interactive data and ensure the accuracy of data transmission.

[0038] As another implementation of the first aspect, the method further includes:

[0039] When the second external device connected to the external device interface is a slave device, the adapter module receives the fourth interactive data sent by the processor chip;

[0040] If the fourth interactive data is data sent to the second external device, the switching module sends the fourth interactive data to the second external device.

[0041] In this application, when a slave device is connected to an external device interface, since the processor chip is the main chip, the adapter module can directly send the interactive data received from the processor chip to the external device.

[0042] As another implementation of the first aspect, the electronic device further includes a first slave device module, and the second port of the adapter module is connected to the first slave device module;

[0043] When the second external device connected to the external device interface is a slave device, the method further includes:

[0044] The switching module receives the fifth interactive data sent by the processor chip;

[0045] If the fifth interactive data is data sent to the first slave device module, the switching module sends the fifth interactive data to the first slave device module.

[0046] In this application, since the processor chip is the main chip and the first slave device module is the slave module, the switching module can directly send the interactive data received from the processor chip to the first slave device module.

[0047] As another implementation of the first aspect, the electronic device further includes a first slave device module, the second port of the adapter module being connected to the first slave device module, and the method further includes:

[0048] When the third external device connected to the external device interface is a charger, the adapter module receives the sixth interactive data sent by the processor chip;

[0049] If the sixth interactive data is data sent to the first slave device module, the switching module sends the sixth interactive data to the first slave device module.

[0050] As another implementation of the first aspect, the electronic device further includes a port controller and a port manager;

[0051] When the third external device connected to the external device interface is a charger, before the adapter module receives the sixth interactive data sent by the processor chip, the method further includes:

[0052] The port controller detects that the external device interface is connected to a third external device, and detects that the third external device is a charger;

[0053] The port controller sends a second device access message to the port manager, wherein the second device access message indicates that the second external device connected to the external device interface is a charger;

[0054] After receiving the second device access message, the port manager generates a second management policy for the external device interface. The second management policy is used to instruct the external device interface to start a data transmission blocking mode to prohibit data transmission.

[0055] In this application, when a charger is connected to an external device interface, since the charger and the processor chip cannot interact with each other, the external device interface is set to a data transmission-prohibited mode to prevent data transmission and ensure the data transmission security of the external device interface.

[0056] In a second aspect, an electronic device is provided, including a processor chip, an external device interface, and an adapter module, wherein a first communication interface of the processor chip is connected to a third port of the adapter module, a first port of the adapter module is connected to the external device interface, and the processor chip is a main chip.

[0057] As another implementation of the second aspect, the electronic device further includes a first slave device module, and the second port of the adapter module is connected to the first slave device module.

[0058] In this application, an adapter module is used to connect one interface of the processor chip to different modules, thereby increasing the functionality of the processor chip interface.

[0059] As another implementation of the second aspect, the electronic device further includes a second slave device module, and the second communication interface of the processor chip is connected to the second slave device module.

[0060] As another implementation of the second aspect, the first slave device module is an AIGC data processing module, and both the AIGC data processing module and the adapter module are located on the AIGC chip.

[0061] As another implementation of the second aspect, the electronic device further includes a port controller and a port manager, the port controller and the port manager being connected, the port controller being used to detect the device type of the external device connected to the external device interface, the device type including master device and slave device, and the port manager being used to perform port management on the external device interface according to the device type detected by the port controller.

[0062] As another implementation of the second aspect, the port controller and the port manager are disposed on the AIGC chip.

[0063] As another implementation of the second aspect, the switching module includes a buffer and an interface controller, the interface controller being connected to the third port, the first port, the second port and the buffer of the switching module respectively.

[0064] Thirdly, a chip system is provided, including a processor coupled to a memory, wherein the processor executes a computer program stored in the memory to implement the method of any one of the first aspects of this application.

[0065] Fourthly, a computer-readable storage medium is provided, which stores a computer program that, when executed by an electronic device, implements the method of any one of the first aspects of this application.

[0066] Fifthly, this application provides a computer program product that, when run on a device, causes the device to perform the method of any one of the first aspects of this application.

[0067] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0068] Figure 1 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application;

[0069] Figure 2 A schematic diagram of the structure of the AIGC chip and the Type-C interface connecting to different interfaces of the processor chip in the prior art provided for the embodiments of this application;

[0070] Figure 3 A schematic diagram of the structure of a processor chip in the prior art provided for the embodiments of this application, where the interface is connected to a Type-C interface and cannot be connected to an AIGC chip;

[0071] Figure 4 The diagram shows a prior art structure where the processor chip's interface is connected to the AIGC chip and cannot be connected to the Type-C interface, as provided in the embodiments of this application.

[0072] Figure 5 This is a schematic diagram illustrating the structure of the AIGC chip and the external device interface connected to the processor chip via an adapter module, as provided in this embodiment of the application.

[0073] Figure 6 A schematic flowchart illustrating the data transmission method when the external device is a slave device, as provided in this embodiment of the application;

[0074] Figure 7 A schematic diagram showing the structure of a processor chip with different interfaces connected to an adapter module and a second slave device module, as provided in an embodiment of this application;

[0075] Figure 8A flowchart illustrating the data transmission method when the external device is the master device, as provided in the embodiments of this application;

[0076] Figure 9 This is a schematic diagram of the adapter module integrated into the AIGC chip according to an embodiment of this application;

[0077] Figure 10 A flowchart illustrating the data transmission method when the external device is a charger, as provided in this embodiment of the application;

[0078] Figure 11 A flowchart illustrating the data transmission method when the external device provided in this application is a USB flash drive;

[0079] Figure 12 A flowchart illustrating the data transmission method when the external device provided in this application is a computer; Detailed Implementation

[0080] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limiting purposes, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details.

[0081] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0082] It should also be understood that in the embodiments of this application, "one or more" refers to one, two, or more; "and / or" describes the relationship between the associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0083] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," "fourth," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0084] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0085] The data transmission method provided in this application can be applied to electronic devices such as tablet computers, mobile phones, laptops, ultra-mobile personal computers (UMPCs), netbooks, and personal digital assistants (PDAs). This application does not limit the specific type of electronic device.

[0086] Figure 1 A schematic diagram of an electronic device is shown. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, antenna 1, antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a touch sensor 180K, etc.

[0087] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0088] Processor 110 may include one or more processing units, such as: application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, memory, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0089] The controller can be the nerve center and command center of the electronic device 100. The controller can generate operation control signals according to the instruction opcode and timing signals to complete the control of fetching and executing instructions.

[0090] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0091] USB interface 130 is an interface that conforms to the USB standard specification, specifically it can be a Mini USB interface, Micro USB interface, USB Type-C interface, etc. USB interface 130 can be used to connect a charger to charge electronic device 100, and it can also be used for data transfer between electronic device 100 and peripheral devices.

[0092] The external storage interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0093] Internal memory 121 can be used to store executable program code, which includes instructions. Processor 110 executes various functional applications and data processing of electronic device 100 by running the instructions stored in internal memory 121. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function (such as sound playback, image playback, etc.).

[0094] In addition, the internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0095] The charging management module 140 is used to receive charging input from the charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger via the USB interface 130.

[0096] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140 to power the processor 110, internal memory 121, external memory, display 194, camera 193, and wireless communication module 160, etc.

[0097] In some other embodiments, the power management module 141 may also be located within the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may also be located in the same device.

[0098] The core of an electronic device is the processor chip, a very large-scale integrated circuit. It can be considered the "brain" of the device, responsible for executing computer program instructions, performing data processing and calculations, and controlling the operation of the entire system. The processor chip can also control and coordinate the work of various components within the electronic device, enabling them to transmit, store, and process data in an orderly manner; perform arithmetic and logical operations on various data types, such as addition, subtraction, multiplication, division, comparison, and judgment; and interact with external devices to achieve information input and output.

[0099] When electronic devices interact with external devices, the external devices need to be plugged into the external device interface (such as a Type-C interface) of the electronic device. Since the external device interface of the electronic device is connected to the communication interface of the processor chip, plugging the external device into the external device interface of the electronic device enables data interaction between the processor chip and the external device, which in turn enables data interaction between the electronic device and the external device.

[0100] For ease of description, this application will use a Type-C interface for external devices and a USB interface for the processor chip as an example.

[0101] With the development of electronic devices, various slave device modules can be added to further enhance their functionality. Different slave device modules are used to implement different functions. The processor chip is connected to each slave device module, controlling different slave device modules to perform different data processing to achieve different functions.

[0102] The following description uses the example of adding a slave device module to an electronic device to implement artificial intelligence processing functions. It should be noted that adding artificial intelligence processing functions to an electronic device is only one embodiment and does not constitute a limitation of this application. Other slave functional modules can also be added to the electronic device.

[0103] Artificial intelligence (AI) refers to the ability of computer systems to perform tasks that typically require human intelligence, such as learning, reasoning, problem-solving, language understanding, image recognition, and planning / decision-making. It is an interdisciplinary field that integrates computer science, cybernetics, information theory, neurophysiology, psychology, linguistics, philosophy, and other disciplines. In recent years, with the development of AI, its application in electronic devices has become a reality. Electronic devices can use AI technology to interact with users, recognize user intentions and perform corresponding operations, and perform image processing, among other things.

[0104] Because artificial intelligence (AI) demands significant computing resources for tasks such as text generation, image editing, and speech recognition and synthesis, specialized chips can efficiently process these tasks and reduce processing time. For example, AIGC (Artificial Intelligence Generated Content) chips are specifically designed and optimized for AI-generated content tasks. AIGC chips feature powerful computing capabilities, efficient parallel processing, high-bandwidth memory access, low power consumption, and support for mixed-precision computing. Therefore, integrating AIGC chips into electronic devices can endow them with powerful AI performance.

[0105] AIGC chips themselves do not have an operating system. When used in electronic devices, AIGC chips are slave devices and require the processor chip in the electronic device to transmit data to them so that AIGC chips can process the received data. Therefore, AIGC chips need to be connected to the processor chip in the electronic device, and AIGC chips are slave modules.

[0106] In one implementation, if the processor chip has an idle communication interface, the AIGC chip can connect to the idle communication interface to achieve communication between the processor chip and the AIGC chip. Figure 2 As shown. The processor chip can interact with the AIGC chip through one communication interface; the processor chip can also be connected to an external device interface through another communication interface, and the external device is connected to the external device interface to realize the interaction between the external device and the processor chip.

[0107] In another implementation, if the processor chip has only one communication interface that can meet the business requirements of the AIGC chip—for example, if the performance (e.g., bandwidth, data write speed, large model loading time) of only one USB interface in a Qualcomm platform meets the business requirements of the AIGC chip—this communication interface in the processor chip is often connected to an external device interface on an electronic device. Figure 3 As shown, the communication interface in the processor chip is already occupied by the external device interface (Type-C interface) on the electronic device, and the communication interface in the processor chip can no longer connect to the AIGC chip; or, as... Figure 4 As shown, if the AIGC chip is connected to the communication interface on the processor chip, the processor chip will be unable to connect to the external device interface (Type-C interface) on the electronic device, and the electronic device will be unable to interact with the external device.

[0108] To address the aforementioned issues, and in order for the processor chip to communicate with the AIGC chip and interact with external devices via the Type-C interface on the electronic device, this application adds an adapter module to the electronic device. The adapter module can serve as an interface expansion module, connecting to both the AIGC chip and the external device interface. For example, the adapter module can be a USB expansion module (also known as a USB HUB controller). Of course, the interface expansion module can also be other communication modules, which are not limited here.

[0109] Specifically, the processor chip's first communication interface is connected to the third port of the adapter module, the adapter module's first port is connected to the external device interface, and the processor chip's second port is connected to the AIGC chip (slave device module). By adding an adapter module to the electronic device, communication between the processor chip and the slave device module (AIGC chip) can be achieved without affecting the existing interaction between the external device interface and the processor chip.

[0110] Below, in conjunction with Figure 6 As shown, the data transmission methods for the processor chip, AIGC chip, and external device interfaces are explained in detail.

[0111] S11, the processor chip sends the data to be processed to the transfer module, wherein the data to be processed includes the data content and the destination address of the data content.

[0112] In this embodiment, both the external device and the AIGC chip correspond to a unique communication address. For example, the communication address of the external device can be address 1, and the communication address of the AIGC chip can be address 2. Address 1 and address 2 are different communication addresses. If the data content is data transmitted to the external device, then the destination address of the data content is the communication address of the external device; if the data content is data transmitted to the AIGC chip, then the destination address of the data content is the communication address of the AIGC chip.

[0113] The communication address of the external device can be the communication address assigned to the external device by the processor chip during the initialization process after the external device is inserted into the Type-C interface.

[0114] S12, the switching module receives the data to be processed sent by the processor chip, and the switching module parses the data to be processed to obtain the first data content, the second data content, the destination address of the first data content, and the destination address corresponding to the second data content.

[0115] In this embodiment, the second data content may include images, files, etc. The first data content may include image data to be processed or user requests, etc.

[0116] S13, if the destination address corresponding to the first data content is the communication address of the AIGC chip, the switching module sends the first data content to the AIGC chip.

[0117] S14, if the destination address corresponding to the second data content is the communication address of the external device, the switching module sends the second data content to the external device.

[0118] Of course, if the data to be processed contains only the first data content, then step S14 above does not exist; if the data to be processed contains only the second data content, then step S13 above does not exist.

[0119] The adapter module enables the processor chip to interact with both external devices and slave modules. However, during data exchange between the processor chip and the slave module, the slave module, lacking an operating system, needs to receive instructions from the processor chip to function; therefore, it cannot act as the master chip. The processor chip, on the other hand, possesses an operating system and control over other chips and components. It actively sends control signals to the slave chip according to predetermined program logic or user commands, instructing when to start working, what specific operations to perform, and when to stop. Therefore, the processor chip can act as the master chip.

[0120] The inventors discovered that if the external device connected to the external device interface is a slave device, using the methods described in steps S11 to S14 above, the processor chip can transmit data to the slave device module (AIGC chip) and the external device through the adapter module.

[0121] If the external device connected to the external device interface is the master device, for example, if the external device interface is connected to a computer and the computer is the master device, then the processor chip will become a slave chip when interacting with the external device.

[0122] If we follow the current method, using the original port controller in the processor chip to detect the device information of the external device connected to the external device interface, such as... Figure 3 As shown, when the native port controller in the processor chip detects that the external device is the master device, the processor chip will set its own role as a slave chip.

[0123] In this situation, the processor chip acts as the master chip when interacting with the slave device module, and as the slave chip when interacting with the connected external device. This creates a conflict between the master and slave roles of the processor chip, preventing the smooth transmission of data between the processor chip, the external device, and the slave device module.

[0124] To address the conflicting master-slave roles of the processor chip during interaction between the processor chip, slave module, and external device (master device), this application incorporates a port controller and a port manager within the electronic device, separate from the processor chip. Taking the Type-C interface as an example, this application sets up a port controller (Type-C PortController, TCPC) and a port manager (Type-C port manager, TCPM) within the electronic device, as follows: Figure 5 As shown.

[0125] The newly configured port controller takes over the tasks of the original port controller in the processor chip. This makes the processor chip unaware of whether the external device is a master or slave device, ensuring that the processor chip always maintains its role as the master chip.

[0126] Specifically, a port controller (such as TCPC) detects the device information of external devices. This information can include the device type and master / slave type. Device types include chargers, USB flash drives, computers, etc. Specifically, because each external device has a different Configuration Channel pin (CC pin) circuit, TCPC determines the device information by detecting the CC pin circuit of the external device.

[0127] After detecting device information, the port controller sends the detected device information to the port manager (e.g., TCPM). Upon receiving the device information from the port controller, the port manager manages the external device interface according to the device information, such as managing the data transmission type of the external device interface and whether data transmission is allowed.

[0128] In another implementation, after receiving device information from the port controller, the port manager sends a first instruction to the processor chip. This first instruction instructs the processor chip to maintain its master chip role. Upon receiving the first instruction, the processor chip does not change its master-slave role and continues to maintain that role.

[0129] Because the newly added port controller takes over the detection tasks of external devices, the processor chip is unaware of the master-slave role of the external devices. Therefore, the processor chip cannot change its own master-slave role based on the external devices, thus preventing it from always remaining the master chip. This application's method solves the problem of conflicting master-slave roles when the processor chip interacts with the AIGC chip and external devices.

[0130] Although the newly added port controller solved the problem of conflicting master and slave roles when the processor chip, slave device module, and external device (master device) interacted, the inventors discovered another problem: when the external device is the master device, since the processor chip always remains the master chip, both the processor chip and the external device are master devices. In this case, data transmission between the processor chip and the external device is also impossible.

[0131] To address the data transmission issues between the processor chip and the external device when both are master devices, this application incorporates a buffer in the switching module. During data interaction between the processor chip and the external device, the exchanged data is placed in the buffer. Both the processor chip and the external device then read the exchanged data from the buffer, thus preventing direct data exchange between them and resolving the problem of data transmission inability when both the processor chip and the external device are master devices.

[0132] In one embodiment, different communication interfaces of the processor chip are connected from the device module (second slave device module) and the external device interface, such as... Figure 7 As shown, the adapter module is connected to the first communication interface of the processor chip, and the slave device module is connected to the second communication interface of the processor chip. The specific method for the processor chip to interact with the external device is as follows.

[0133] When the slave device module is the AIGC chip, the data transmission method when the external device is the master device is described in detail.

[0134] The processor chip sends the data to be processed (first interaction data) to the adapter module.

[0135] After receiving the data to be processed from the processor chip, the transfer module stores the data.

[0136] External devices can read data to be processed from the transfer module through polling. Alternatively, the transfer module can send a read command to the external device, which then reads the data to be processed from the transfer module upon receiving the command.

[0137] Conversely, when an external device sends data to be processed (secondary interactive data) to the processor chip, the adapter module will also store the data to be processed first, so that the processor chip can read the data to be processed from the adapter module. This will not be explained in detail here.

[0138] In another embodiment, if the external device connected to the external device interface is a slave device, the adapter module sends the data to be processed to the external device after receiving the data to be processed sent by the processor chip to the external device.

[0139] Reference Figure 5 As shown, in another embodiment, the AIGC chip and the external device interface are connected to the same communication interface of the processor chip. The specific method for the processor chip to interact with the external device is as follows; please refer to [reference needed]. Figure 8 .

[0140] S21, the processor chip sends the data to be processed to the transfer module, wherein the data to be processed includes the third data content (third interactive data), the fourth data content (first interactive data), the destination address of the third data content, and the destination address of the fourth data content.

[0141] S22, the switching module receives the data to be processed sent by the processor chip, and the switching module parses the data to be processed to obtain each data content in the data to be processed and the destination address corresponding to each data content.

[0142] S23, if the destination address corresponding to the third data content is the communication address of the AIGC chip, the switching module sends the corresponding third data content to the AIGC chip.

[0143] S24, if the destination address corresponding to the fourth data content is the communication address of an external device, the switching module stores the fourth data content.

[0144] S25, the external device reads the fourth data content from the transfer module by polling.

[0145] S26, the external device sends the data to be transmitted to the transfer module. The data to be transmitted includes the fifth data content, the sixth data content (second interactive data), the destination address of the fifth data content, and the destination address of the sixth data content.

[0146] In this embodiment, the fifth data content can be an image or a user request, etc. The sixth data content can be an image or a file, etc.

[0147] S27, after receiving the data to be transmitted from the external device, the switching module parses the data to be transmitted to obtain the fifth data content, the sixth data content, the destination address of the fifth data content, and the destination address of the sixth data content.

[0148] S28, if the destination address of the fifth data content is the communication address of the AIGC chip, the switching module sends the corresponding fifth data content to the AIGC chip.

[0149] S29, if the destination address of the sixth data content is the communication address of the processor chip, the switching module stores the sixth data content.

[0150] S30, the processor chip reads the sixth data content from the adapter module through polling.

[0151] In another embodiment, after step S24, the method may further include: after the adapter module stores the fourth data content, the adapter module sends a data read instruction to the external device, the data read instruction instructing the external device to read the fourth data content from the adapter module. Upon receiving the data read instruction, the external device reads the fourth data content from the adapter module.

[0152] In another embodiment, after step S28, the process may further include: after the switching module stores the sixth data content, the switching module sends a data read instruction to the processor chip, the data read instruction instructing the processor chip to read the sixth data content from the switching module. Upon receiving the data read instruction, the processor chip reads the sixth data content from the switching module.

[0153] In another embodiment, the data to be processed may include either third or fourth data content. If the data to be processed only includes third data content, then steps S24 and S25 will not exist. If the data to be processed only includes fourth data content, then step S23 will not exist. Similarly, the data to be transmitted may include either fifth or sixth data content. If the data to be transmitted only includes fifth data content, then steps S29 and S30 will not exist; if the data to be transmitted only includes sixth data content, then step S28 will not exist.

[0154] The internal structure of the adapter module will be described below.

[0155] Reference Figure 9 As shown, the adapter module includes a second port, a first port, a third port, a buffer, and an interface controller. The second port is connected to the AIGC data processing module (slave device module), the first port is connected to the external device interface, and the third port is connected to the USB physical layer in the processor chip. The second port, first port, third port, and buffer are all connected to the interface controller. For example, when the adapter module is a USB expansion module, the interface controller can be a HUB controller, and the second port, first port, and third port can all be USB interfaces.

[0156] Reference Figure 9 As shown, in practical applications, to save space and make the various modules in the electronic device more compact, the adapter module, port manager (TCPM), and port controller (TCPC) can be integrated with the AIGC data processing module on the AIGC chip. The AIGC data processing module implements artificial intelligence functions. TCPM is set on the AIGC data processing module. In practical applications, TCPM and the AIGC data processing module can be two separate modules; there is no restriction here.

[0157] Below, in conjunction with Figure 9 Taking a Type-C interface as an example, this application describes the data transmission method when connecting different external devices. Specifically, it explains the data transmission methods when connecting a charger, a slave device, and a master device. The slave device can be a USB flash drive or a portable hard drive, while the master device can be a computer or a mobile terminal. For ease of explanation, this application uses a USB flash drive as the slave device and a computer as the master device for detailed description.

[0158] like Figure 10 As shown in the figure, as an embodiment of this application, when the external device (third external device) connected to the external device interface is a charger, the method of this application is specifically described as follows.

[0159] S31, TCPC detects that the external device connected to the Type-C interface is a charger.

[0160] S32, after TCPC detects that the Type-C interface is connected to the charger, TCPC sends a second device access message to TCPM. The second device access message is used to indicate that the Type-C interface is connected to the charger.

[0161] S33, after receiving the second device access message sent by TCPC, TCPM sends a second management policy to the Type-C interface. The second management policy is used to instruct the external device interface to start a data transmission ban mode to prohibit data transmission.

[0162] In this embodiment, after receiving the second management policy, the Type-C interface activates the data transmission ban mode, prohibiting the Type-C interface from transmitting data.

[0163] Specifically, since the Type-C interface connects to the charger, no data is transmitted between the processor chip and the charger. At this time, the processor chip only transmits data with the AIGC data processing module. Therefore, the processor chip still acts as the master device, and the AIGC data processing module still communicates as the slave device module.

[0164] In another embodiment, after receiving the second device access message sent by TCPC, TCPM can send a first message to the processor chip, which is used to instruct the processor chip to be set as the master device.

[0165] TCPM and the processor chip can communicate via a serial bus, for example, via an I2C bus.

[0166] In another embodiment, the processor chip and the AIGC data processing module remain connected, and when communicating with each other, the processor chip is the master device and the AIGC data processing module is the slave device. Even after connecting the charger via the Type-C interface, the processor chip remains the master device and the AIGC data processing module remains the slave device. Therefore, after receiving the second device access message from TCPC, TCPM may not send the first message to the processor chip, thus ensuring that the processor chip remains the master device and the AIGC data processing module remains the slave device.

[0167] S34, the processor chip generates first data according to the communication address of the AIGC data processing module, and sends the first data to the interface controller. The first data contains seventh data content (sixth interactive data) and the destination address of the seventh data content, etc. The destination address of the seventh data content is the communication address of the AIGC data processing module (first slave device module).

[0168] In this embodiment, after the charger is connected to the Type-C interface, TCPM manages the Type-C interface, preventing it from transmitting data. The processor chip recognizes that the Type-C interface cannot transmit data, therefore, the processor chip does not interact with the charger and can only interact with the AIGC data processing module.

[0169] The processor chip sends the first data to the third port in the adapter module. After receiving the first data, the third port sends the first data to the interface controller.

[0170] S35, after receiving the first data, the interface controller analyzes the first data to obtain the seventh data content and the destination address of the seventh data content, and determines that the destination address of the seventh data content is the communication address of the AIGC data processing module.

[0171] S36, the interface controller sends the seventh data content to the AIGC data processing module through the second port.

[0172] In actual use, when the adapter module is a USB expansion module, the third port in the USB expansion module includes the USB physical layer.

[0173] The USB physical layer in the third port communicates with the processor chip. After receiving the first data sent by the processor chip, the USB physical layer in the third port performs format conversion and other operations on the first data to obtain processed first data. The USB physical layer in the third port then sends the processed first data to the interface controller. After receiving the processed first data, the interface controller analyzes the first data to obtain the seventh data content and the destination address of the seventh data content included in the first data.

[0174] S37, the AIGC data processing module receives the seventh data content and processes it.

[0175] In this embodiment, if the AIGC data processing module needs to return data to the processor chip, it needs to send first return data to the second port. After receiving the first return data, the second port sends the first return data to the interface controller. After receiving the first return data, the interface controller determines whether to send the first return data to the processor chip based on the destination address of the first return data. The interface controller then sends the first return data to the processor chip through the third port.

[0176] In one embodiment, if the Type-C interface connects to an external device that does not have an operating system, and the external device is a slave device (e.g., a USB flash drive, portable hard drive, portable printer), the processor chip is the master chip. The processor chip can interact with both the AIGC data processing module and the external device. Specifically, the communication method between the processor chip, the AIGC data processing module, and the external slave device is described below.

[0177] like Figure 11 As shown, for ease of description, we will use a USB flash drive as an example for illustration.

[0178] S41, TCPC detected that the external device (second external device) connected to the Type-C interface is a USB flash drive.

[0179] S42, TCPC sends a third device access message to TCPM. The third device access message is used to indicate that the USB flash drive is connected to the Type-C interface and that the USB flash drive is a slave device.

[0180] S43, after receiving the third device access message, TCPM sends a third management policy to the Type-C interface. The third management policy is used to instruct the external device interface to start the data transmission mode for data transmission.

[0181] In this embodiment, after receiving the third management policy, the Type-C interface enters the data transmission mode, in which the Type-C interface can transmit data.

[0182] In another embodiment, after receiving the third device access message, TCPM can send a fourth message to the processor chip, which is used to instruct the processor chip to be set as the master device.

[0183] In another embodiment, when the processor chip and the AIGC data processing module are connected, the processor chip is the master chip and the AIGC data processing module is the slave device. Even after a USB flash drive is connected via the Type-C interface, the processor chip remains the master chip, and the AIGC data processing module remains the slave device. Therefore, after TCPM receives a third device access message, TCPM does not need to send a fourth message to the processor chip, thus maintaining the processor chip as the master chip and the AIGC data processing module as the slave device.

[0184] In one embodiment, since the USB flash drive can only act as a slave device and not a master device, the processor chip, acting as the master chip, can directly interact with the USB flash drive. After receiving a third device access message, the TCPM can send a direct data transmission command to the interface controller. This command instructs the interface controller to directly transmit data to the USB flash drive after receiving the data exchanged between the processor chip and the USB flash drive. Upon receiving the direct data transmission command, if the interface controller receives the data sent by the processor chip to the USB flash drive, it will directly send the corresponding data to the USB flash drive. The processor chip can both write and read data from the USB flash drive.

[0185] S44, the interface controller detects that an external device has been inserted into the Type-C interface, and sends a device insertion event to the processor chip.

[0186] Specifically, the first port of the adapter module includes a USB physical layer. When the USB physical layer in the first port detects an external device connected to the Type-C interface, it generates a device access notification. The USB physical layer in the first port sends the device access notification to the interface controller. After receiving the device access notification, the interface controller generates a device insertion event and sends the device insertion event to the processor chip through the third port.

[0187] S45, after receiving the device insertion event sent by the interface controller, the processor chip sends an initialization command to the interface controller.

[0188] Specifically, the processor chip sends initialization instructions to the interface controller through the third port.

[0189] In another embodiment, the USB physical layer in the first port detects an external device connected to the Type-C interface and generates a device access notification. The USB physical layer in the first port sends the device access notification to the interface controller. Upon receiving the device access notification, the external access flag in the interface controller changes. The processor chip determines the presence of an external device on the Type-C interface by reading the external access flag in the interface controller.

[0190] S46. After receiving the initialization command, the interface controller sends an initialization command to the USB flash drive to initialize the USB flash drive connected to the Type-C interface. The initialization command includes the communication address assigned to the USB flash drive.

[0191] In this embodiment, initializing the USB flash drive connected via the Type-C interface includes assigning a unique communication address to the USB flash drive and obtaining its configuration information. The configuration information includes the number of interfaces on the USB flash drive and the function of each interface.

[0192] S47. After receiving the initialization command, the USB flash drive initializes itself according to the command and obtains the communication address of the USB flash drive.

[0193] S48, when the processor chip needs to send data to the USB flash drive and the AIGC data processing module respectively, the processor chip generates second data based on the communication address of the USB flash drive and the communication address of the AIGC data processing module, and sends the second data to the interface controller. The second data includes the eighth data content, the destination address of the eighth data content, the ninth data content, and the destination address of the ninth data content.

[0194] S49, the processor chip sends the second data to the interface controller.

[0195] S50, after receiving the second data, the interface controller analyzes the second data and determines that the second data includes the eighth data content and the ninth data content, and that the destination address of the eighth data content is the communication address of the USB flash drive, and the destination address of the ninth data content is the communication address of the AIGC data processing module.

[0196] Specifically, the third port of the switching module receives the second data and then sends the second data to the interface controller. After receiving the second data, the interface controller analyzes it to obtain the data content and the corresponding communication address.

[0197] In one embodiment, after receiving the second data, the USB physical layer in the third port performs format conversion and other operations on the second data to obtain processed second data. The third port then sends the processed second data to the interface controller. The interface controller analyzes the processed second data to obtain the data content and communication address included in the second data.

[0198] S51, the interface controller sends the eighth data content to the USB flash drive.

[0199] In this embodiment, the interface controller sends the eighth data content (fourth interactive data) to the USB flash drive through the first port.

[0200] S52, the interface controller sends the ninth data content (fifth interactive data) to the AIGC data processing module (first slave device module).

[0201] In this embodiment, the interface controller sends the eighth data content to the AIGC data processing module through the second port.

[0202] In one embodiment, if the second data only includes the eighth data content, then the above step S52 does not need to be executed; if the second data only includes the ninth data content, then the above step S51 does not need to be executed.

[0203] In one embodiment, the data read by the processor chip from the USB flash drive needs to be transmitted to the processor chip through the interface controller, which will not be described in detail here.

[0204] In one embodiment, if the Type-C interface connects to an external device with an operating system (the first external device), such as a computer, the processor chip is the master chip, the external device is the master device, and the AIGC data processing module is the slave device. The processor chip and the AIGC data processing module can directly interact with each other. The processor chip and the external device do not interact directly to avoid master-slave conflicts. Specifically, the communication method between the processor chip, the AIGC data processing module, and the external slave device is described below.

[0205] like Figure 12 As shown, for ease of description, we will use a computer as an example for explanation.

[0206] S61, TCPC detects that the external device (first external device) connected to the Type-C interface is a computer.

[0207] S62, TCPC sends a first device access message to TCPM. The first device access message is used to indicate that the Type-C interface is connected to the computer and the computer is the master device.

[0208] S63, after receiving the first device access message, TCPM sends a first management policy to the Type-C interface. The first management policy is used to instruct the external device interface to start the data transmission mode for data transmission.

[0209] S64, TCPM sends a data caching instruction to the interface controller. The data caching instruction is used to instruct the interface controller to start the data caching mode, which is a mode that caches the interaction data between the processor chip and the computer.

[0210] S65, after receiving the data caching instruction, the interface controller enters the data caching mode.

[0211] S66, the interface controller detects that an external device has been inserted into the Type-C interface, and sends a device insertion event to the processor chip.

[0212] S67. After receiving the device insertion event sent by the interface controller, the processor chip sends an initialization command to the interface controller.

[0213] Specifically, the processor chip sends initialization instructions to the interface controller through the third port.

[0214] S68: After receiving the initialization command, the interface controller sends an initialization command to the computer to initialize the computer connected to the Type-C interface. The initialization command includes the communication address assigned to the computer.

[0215] In this embodiment, initializing the computer connected via the Type-C interface includes assigning a unique communication address to the computer and obtaining the computer's configuration information. The configuration information includes the number of interfaces on the computer and the function of each interface.

[0216] S69. After receiving the initialization command, the computer initializes itself according to the command and obtains the computer's communication address.

[0217] S70, when the processor chip needs to send data to the computer and the AIGC data processing module (first slave device module) respectively, the processor chip generates third data according to the communication address of the computer and the communication address of the AIGC data processing module, and sends the third data to the interface controller. The third data includes the tenth data content, the destination address of the tenth data content, the eleventh data content, and the destination address of the eleventh data content.

[0218] S71, the processor chip sends third data to the interface controller.

[0219] S72, after receiving the third data, the interface controller analyzes the third data and determines that the third data includes the tenth data content and the eleventh data content, and that the destination address of the tenth data content (first interactive data) is the communication address of the computer, and the destination address of the eleventh data content (third interactive data) is the communication address of the AIGC data processing module.

[0220] Specifically, the third port of the switching module receives the second data and then sends the third data to the interface controller. Upon receiving the third data, the interface controller analyzes it to obtain the data content and the corresponding communication address.

[0221] In one embodiment, after receiving the third data, the USB physical layer in the third port performs format conversion and other operations on the third data to obtain processed third data. The third port then sends the processed third data to the interface controller. The interface controller analyzes the processed third data to obtain the data content and communication address included in the third data.

[0222] S73, the interface controller sends the eleventh data content to the AIGC data processing module.

[0223] S74, the interface controller sends the tenth data content to the buffer.

[0224] S75, the computer reads the tenth data content from the buffer through the interface controller.

[0225] Specifically, the computer sends a read command to the interface controller, the interface controller sends a read command to the buffer, the buffer sends the corresponding read data to the interface controller according to the read command, and the interface controller sends the read data to the computer.

[0226] In this embodiment, if the computer (first external device) needs to send fourth data (second interactive data) to the processor chip, the computer first needs to send the fourth data to the interface controller. After receiving the fourth data sent by the computer, the interface controller sends the fourth data to the buffer. The buffer stores the fourth data. The processor chip reads the fourth data from the buffer through the interface controller.

[0227] Finally, it should be noted that the buffer can be set in the adapter module, such as... Figure 9 As shown. The buffer can also be set outside the adapter module; there are no restrictions here.

[0228] In this application, the naming convention of "first," "second," etc., is used to distinguish information of the same type in different embodiments, or information of the same type in the same embodiment. Although information of the same type has different numbers, it does not mean that the content (or value) of information of the same type must be different. In practical applications, information of the same type may have different numbers, but its content (or value) may be the same.

[0229] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0230] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the above-described method embodiments.

[0231] This application also provides a computer program product that, when run on a first device, enables the first device to implement the steps described in the various method embodiments above.

[0232] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to the first device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0233] This application also provides a chip system, which includes a processor coupled to a memory. The processor executes a computer program stored in the memory to implement the steps of any method embodiment of this application. The chip system can be a single chip or a chip module composed of multiple chips.

[0234] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0235] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0236] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A data transmission method, characterized in that, The invention is applied to an electronic device, which includes a processor chip, an external device interface, and an adapter module. The first communication interface of the processor chip is connected to the third port of the adapter module, and the first port of the adapter module is connected to the external device interface. The processor chip is the main chip. The method includes: When the first external device connected to the external device interface is the master device, the adapter module receives the first interactive data sent by the processor chip; If the first interaction data is data sent to the first external device, the switching module caches the first interaction data so that the first external device can read the first interaction data from the switching module.

2. The method as described in claim 1, characterized in that, When the first external device connected to the external device interface is the master device, the method further includes: The switching module receives the second interactive data sent by the first external device; If the second interactive data is data sent to the processor chip, the switching module caches the second interactive data so that the processor chip can read the second interactive data from the switching module.

3. The method as described in claim 1, characterized in that, The electronic device further includes a first slave device module, and the second port of the adapter module is connected to the first slave device module; When the first external device connected to the external device interface is the master device, the method further includes: The switching module receives third interactive data sent by the processor chip; If the third interactive data is data sent to the first slave device module, the switching module sends the third interactive data to the first slave device module.

4. The method according to any one of claims 1 to 3, characterized in that, The electronic device also includes a port controller and a port manager; When the first external device connected to the external device interface is the master device, before the adapter module receives the first interactive data sent by the processor chip, the method further includes: The port controller detects that the external device interface is connected to the first external device, and detects that the first external device is the master device; The port controller sends a first device access message to the port manager, wherein the first device access message indicates that the first external device connected to the external device interface is a master device; After receiving the first device access message, the port manager generates a first management policy for the external device interface. The first management policy is used to instruct the external device interface to start a data transmission mode for data transmission.

5. The method as described in claim 4, characterized in that, After the port manager receives the first device access message, the method further includes: The port manager sends a data caching instruction to the switching module, wherein the data caching instruction is used to instruct the switching module to start a data caching mode, which is a mode for caching the interaction data between the processor chip and the first external device; After receiving the data caching instruction, the switching module enters the data caching mode.

6. The method as described in claim 1, characterized in that, The switching module includes a buffer and an interface controller, the buffer and the interface controller are connected, and the method further includes: When the first external device connected to the external device interface is the master device, the interface controller receives the first interactive data sent by the processor chip; If the first interactive data is data sent to the first external device, the interface controller sends the first interactive data to the buffer; After receiving the first interactive data, the buffer caches the first interactive data so that the first external device can read the first interactive data from the buffer. The interface controller receives the second interactive data sent by the first external device; If the second interactive data is data sent to the processor chip, the interface controller sends the second interactive data to the buffer; After receiving the second interactive data, the buffer caches the second interactive data so that the processor chip can read the second interactive data from the buffer.

7. The method as described in claim 1, characterized in that, The method further includes: When the second external device connected to the external device interface is a slave device, the adapter module receives the fourth interactive data sent by the processor chip; If the fourth interactive data is data sent to the second external device, the switching module sends the fourth interactive data to the second external device.

8. The method as described in claim 7, characterized in that, The electronic device further includes a first slave device module, and the second port of the adapter module is connected to the first slave device module; When the second external device connected to the external device interface is a slave device, the method further includes: The switching module receives the fifth interactive data sent by the processor chip; If the fifth interactive data is data sent to the first slave device module, the switching module sends the fifth interactive data to the first slave device module.

9. The method as described in claim 1, characterized in that, The electronic device further includes a first slave device module, and the second port of the adapter module is connected to the first slave device module. The method further includes: When the third external device connected to the external device interface is a charger, the adapter module receives the sixth interactive data sent by the processor chip; If the sixth interactive data is data sent to the first slave device module, the switching module sends the sixth interactive data to the first slave device module.

10. The method as described in claim 9, characterized in that, The electronic device also includes a port controller and a port manager; When the third external device connected to the external device interface is a charger, before the adapter module receives the sixth interactive data sent by the processor chip, the method further includes: The port controller detects that the external device interface is connected to a third external device, and detects that the third external device is a charger; The port controller sends a second device access message to the port manager, wherein the second device access message indicates that the second external device connected to the external device interface is a charger; After receiving the second device access message, the port manager generates a second management policy for the external device interface. The second management policy is used to instruct the external device interface to start a data transmission blocking mode to prohibit data transmission.

11. An electronic device, characterized in that, It includes a processor chip, an external device interface, and an adapter module. The first communication interface of the processor chip is connected to the third port of the adapter module, and the first port of the adapter module is connected to the external device interface. The processor chip is the main chip.

12. The electronic device as claimed in claim 11, characterized in that, The electronic device further includes a first slave device module, and the second port of the adapter module is connected to the first slave device module.

13. The electronic device as claimed in claim 11 or 12, characterized in that, The electronic device further includes a second slave device module, and the second communication interface of the processor chip is connected to the second slave device module.

14. The electronic device as claimed in claim 12, characterized in that, The first slave device module is an AIGC data processing module, and both the AIGC data processing module and the adapter module are mounted on the AIGC chip.

15. The electronic device as claimed in claim 14, characterized in that, The electronic device further includes a port controller and a port manager. The port controller and the port manager are connected. The port controller is used to detect the device type of the external device connected to the external device interface. The device type includes master devices and slave devices. The port manager is used to manage the port of the external device interface according to the device type detected by the port controller.

16. The electronic device as claimed in claim 15, characterized in that, The port controller and the port manager are located on the AIGC chip.

17. The electronic device as claimed in claim 12, characterized in that, The adapter module includes a buffer and an interface controller, and the interface controller is connected to the third port, the first port, the second port and the buffer of the adapter module respectively.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by an electronic device, implements the method as described in any one of claims 1 to 10.

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