FPGA-based ultra-high-speed peak gate feature extraction method and system
By utilizing the parallel pipeline architecture of FPGA and hysteresis comparison technology, the problem of real-time extraction of multi-dimensional peak features and waveform phase in ultrasonic testing is solved, improving the defect identification capability and imaging accuracy of ultrasonic microscopes, and making it suitable for high-end ultrasonic testing equipment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENGDU MAISHUO ELECTRIC CO LTD
- Filing Date
- 2026-05-14
- Publication Date
- 2026-08-04
AI Technical Summary
Existing ultrasonic testing technologies struggle to extract multi-dimensional peak features and waveform phase in real time under ultra-high-speed sampling, and are susceptible to noise interference, leading to reduced accuracy in defect identification.
A parallel pipeline architecture based on FPGA is adopted. By using hysteresis comparison, delay alignment and parallel extreme value tracking, the first peak, second peak, maximum peak, last peak and waveform phase features in the ultrasonic echo data stream are extracted in real time. Synchronous discrimination is achieved by combining binary tree comparison.
Real-time extraction of multi-dimensional peak features and synchronous discrimination of waveform phase were achieved under ultra-high-speed data streams, improving defect identification accuracy, suppressing noise interference, and meeting the real-time imaging requirements of high-end ultrasonic microscopes.
Smart Images
Figure CN122196510B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of ultrasonic testing technology, specifically to an FPGA-based method and system for extracting ultra-high-speed peak gate features. Background Technology
[0002] As an important non-destructive testing device, ultrasonic microscopy is widely used in the detection of internal defects in semiconductor packaging, composite materials, aerospace components, and other fields. Its core working principle is to emit ultrasonic waves into the sample under test through an ultrasonic transducer, receive the reflected echoes (A-scan signal), and form a C-scan image after data acquisition and processing, thereby visually displaying the internal structure of the sample.
[0003] In ultrasonic testing, peak gate imaging is the most commonly used imaging mode. The operator sets one or more gates (time windows) on the time axis of the A-scan signal. The system extracts feature values (such as peak amplitude) within the gates and converts them into pixel grayscale values to construct an image. Existing FPGA implementation technologies related to ultrasonic testing generally have significant limitations. Most existing solutions use a maximum / minimum comparator architecture, which can only extract the maximum peak value of the signal within the gate. This results in a single feature extraction dimension, losing crucial waveform information that reflects defects, deep details, and acoustic impedance changes, such as the first peak, second peak, maximum peak, last peak, and waveform phase. This reduces the accuracy of defect identification. Furthermore, the sampling rate of ultrasonic microscopes has increased to the 1GS / s to 6GS / s range. This ultra-high-speed sampling brings massive data processing pressure, which traditional software post-processing and low-speed hardware cannot meet real-time processing requirements. Moreover, severe signal noise interference during acquisition easily leads to false positives and false negatives in peak detection. Existing FPGA solutions cannot extract multi-dimensional peak features and determine waveform phase in real time under ultra-high-speed sub-data streams, failing to meet the high-precision, real-time imaging requirements of high-end ultrasonic microscopes. Therefore, there is an urgent need for an FPGA implementation method and device that can extract multi-dimensional features such as the first peak, second peak, highest peak, and last peak within the gate in real time under ultra-high-speed sub-data streams and simultaneously determine the waveform phase. Summary of the Invention
[0004] The purpose of this invention is to provide an ultra-high-speed peak gate feature extraction method and system based on FPGA. It can extract complete waveform features such as the first peak, second peak, highest peak, and last peak within the data gate in real time at sampling rates of 1GS / s, 2GS / s, 4GS / s and higher, relying on a parallel pipelined processing architecture, and simultaneously determine whether the waveform phase is reversed, thereby providing richer signal details for ultrasonic imaging and effectively improving defect identification capabilities.
[0005] To solve the above-mentioned technical problems, the present invention adopts the following solution: An FPGA-based method for extracting features from ultra-high-speed peak gates includes: presetting positive and negative thresholds and hysteresis width, comprising the following steps: S1: The original high-speed ultrasonic echo data stream is parallelized to obtain parallel data groups by sampling K data points per clock cycle. The parallel data groups are compared with positive and negative thresholds respectively, and the hysteresis comparison results are output. S2: Align the original high-speed ultrasonic echo data stream with the hysteresis comparison result by delay, and filter out the positive and negative peak sub-data streams based on the hysteresis comparison result; S3: Perform parallel pipelined extreme value tracing on the positive and negative peak sub-data streams respectively to obtain the local extreme values of each sub-data stream segment. Compare the local extreme values to obtain the global extreme value and its position information within the current sub-data stream. S4: Repeat S3 to obtain the global extrema of multiple sub-data streams, and extract the positive first peak, positive second peak, positive maximum peak, positive last peak, as well as the negative first peak, negative second peak, negative maximum peak, negative last peak and their position information accordingly. S5: Based on the positive first peak, positive second peak, positive maximum peak, positive last peak, and negative first peak, negative second peak, negative maximum peak, negative last peak and their position information extracted in S4, determine the waveform phase state and output the extracted peak features and phase state.
[0006] Existing ultrasonic peak extraction schemes can only acquire a single peak, losing information about the first, second, and last peaks, as well as waveform phase information. Furthermore, they are insufficient to meet the demands of ultra-high-speed real-time processing above 1 GS / s and are susceptible to noise interference. This invention, based on FPGA, employs parallel hysteresis comparison to suppress noise, delay alignment to ensure timing synchronization, parallel extremum tracking and binary tree comparison to quickly locate global extrema, multi-window multi-peak extraction to preserve complete waveform details, and phase discrimination to synchronously output phase status. This achieves synchronous extraction of the first, second, third, and last peaks, as well as waveform phase, in both positive and negative directions under ultra-high-speed data streams. It boasts strong real-time processing capabilities, rich feature dimensions, strong resistance to noise jitter, and low latency with high stability.
[0007] Preferably, in S1, K is equal to the ratio of the sampling rate to the FPGA processing clock frequency. Each clock cycle, the K sampled data input in parallel is accompanied by a frame end flag, which is used to indicate whether the parallel data group of the current clock cycle is the end of a complete sub-data stream.
[0008] Preferably, in S1, the hysteresis comparison result is a vector of positive and negative threshold comparison results and its peak segment end marker. The hysteresis comparison between the parallel data group and the positive threshold is specifically as follows: When the sampled data in the parallel data group jumps from below the positive threshold to above "positive threshold + hysteresis width", the vector position is 1; When the sampled data in the parallel data group jumps from above the positive threshold to below "positive threshold - hysteresis width", the vector position is 0 and a peak end marker is generated; The hysteresis comparison between parallel data sets and negative thresholds is specifically as follows: When the sampled data in the parallel data group jumps from above the negative threshold to below "negative threshold - hysteresis width", the vector position is 1; When the sampled data in the parallel data group jumps from below the negative threshold to above "negative threshold + hysteresis width", the vector position is 0 and a peak end marker is generated.
[0009] Preferably, in S2, the filtering of positive and negative peak sub-data streams is specifically as follows: Based on the position of 1 in the positive threshold comparison result vector, the sampling data at the corresponding position is extracted from the original high-speed ultrasonic echo data stream after delay alignment to form a positive peak sub-data stream; Based on the positions where 1 is found in the negative threshold comparison result vector, the sampled data at the corresponding positions are extracted to form a negative peak sub-data stream.
[0010] Preferably, in S3, extreme value tracking uses K parallel comparators, each of which independently tracks the local extreme values of a sub-data stream.
[0011] Preferably, in S4: The first and second positive peaks are the global maximum values of the first and second sub-data streams, respectively; the highest positive peak is the global maximum value among all sub-data streams; and the last positive peak is the global maximum value of the last sub-data stream. The negative first peak and negative second peak are the global minimum values of the first and second sub-data streams, respectively; the negative maximum peak is the global minimum value among all sub-data streams; and the negative final peak is the global minimum value of the last sub-data stream.
[0012] Preferably, in S5: When the positive first peak, positive second peak, and negative first peak are all valid, and the position of the negative first peak is between the positive first peak and the positive second peak, the phase is considered normal. When the negative first peak, negative second peak, and positive first peak are all valid and the position of the positive first peak is between the negative first peak and the negative second peak, a phase reversal is determined. Otherwise, the phase is determined to be abnormal.
[0013] Preferably, the hysteresis width is preset according to the system noise level; the higher the noise, the greater the hysteresis width.
[0014] Preferably, it also includes a marker delay step: delaying the frame end flag accompanying the original high-speed ultrasonic echo data stream by M clock cycles, where M is equal to the number of clock cycles consumed by the extreme value tracking and binary tree comparison processing in S3, and the delayed frame end flag is used to control the synchronous output of peak features and phase state in S5.
[0015] An FPGA-based ultra-high-speed peak gate feature extraction system includes: The parallel hysteresis comparison module is used to parallelize the original high-speed ultrasonic echo data stream by taking K samples per clock cycle to obtain parallel data groups. The parallel data groups are compared with the positive threshold and hysteresis width, and the negative threshold and hysteresis width respectively. The positive and negative threshold comparison result vectors and their peak segment end markers are output. The data filtering module is used to align the raw high-speed ultrasonic echo data stream with the hysteresis comparison, and filter out the positive and negative peak sub-data streams based on the hysteresis comparison results. The extreme value tracking and binary tree comparison module is used to perform parallel pipelined extreme value tracking on the positive and negative peak sub-data streams respectively, obtain the local extreme values of each sub-data stream segment, compare each local extreme value, and obtain the global extreme value and its position information in the current sub-data stream; The multi-peak extraction module is used to repeatedly call the extreme value tracking and binary tree comparison module to obtain the global extreme values of multiple sub-data streams, and extract the positive first peak, positive second peak, positive maximum peak, positive last peak, as well as the negative first peak, negative second peak, negative maximum peak, negative last peak and their position information. The phase discrimination and output module is used to determine the waveform phase state based on the positive first peak, positive second peak, positive maximum peak, positive last peak, negative first peak, negative second peak, negative maximum peak, negative last peak and their position information extracted by the multi-peak extraction module, and output the extracted peak features and phase state.
[0016] The beneficial effects of this invention are: 1. This invention fully utilizes the parallel pipeline architecture of FPGA, perfectly adapts to sampling rates of 1GS / s and above, has no data blocking, and meets the requirements for real-time imaging in ultrasonic microscopy.
[0017] 2. It adopts a hardware architecture that combines parallel extreme value tracking and binary tree comparison to simultaneously extract nine types of peak features, including the first positive peak, the second positive peak, the highest positive peak, the last positive peak, the first negative peak, the second negative peak, the highest negative peak, the last negative peak, and the waveform phase. It preserves complete waveform details, breaks through the traditional single peak limitation, provides additional dimensions of defect features, improves the ability to detect complex defects, and significantly improves the accuracy of defect identification.
[0018] 3. A hysteresis comparison mechanism is adopted (positive and negative thresholds are set with upper and lower limits composed of hysteresis widths respectively) to suppress noise jitter of the signal near the threshold and avoid false peak detection and missed detection problems.
[0019] 4. It adopts a fully hardware parallel processing architecture, requiring no software intervention, achieving low latency and high stability, and is suitable for high-end industrial ultrasonic testing equipment. Attached Figure Description
[0020] Figure 1This is a flowchart of the FPGA-based ultra-high-speed peak gate feature extraction method and system processing of the present invention.
[0021] Figure 2 This is a schematic diagram of the sub-data flow of the present invention.
[0022] Figure 3 This is a timing diagram for parallel extreme value tracking in this invention.
[0023] Figure 4 This is a block diagram of the parallel binary tree comparison in this invention.
[0024] Figure 5 This is a block diagram of the FPGA-based ultra-high-speed peak gate feature extraction method and system processing of the present invention. Detailed Implementation
[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0026] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps described in these embodiments do not limit the scope of the invention.
[0027] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.
[0028] Furthermore, for clarity and brevity, descriptions of well-known structures, functions, and configurations may have been omitted. Those skilled in the art will recognize that various changes and modifications can be made to the examples described herein without departing from the spirit and scope of this disclosure.
[0029] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0030] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.
[0031] The present invention will now be described in detail with reference to the accompanying drawings and embodiments: Example 1 like Figures 1-5 As shown, the FPGA-based ultra-high-speed peak gate feature extraction method includes: preset positive and negative thresholds, and hysteresis width, and includes the following steps: S1: The original high-speed ultrasonic echo data stream is parallelized to obtain parallel data groups by sampling K data points per clock cycle. The parallel data groups are compared with positive and negative thresholds respectively, and the hysteresis comparison results are output. S2: Align the original high-speed ultrasonic echo data stream with the hysteresis comparison result by delay, and filter out the positive and negative peak sub-data streams based on the hysteresis comparison result; S3: Perform parallel pipelined extreme value tracing on the positive and negative peak sub-data streams respectively to obtain the local extreme values of each sub-data stream segment. Compare the local extreme values to obtain the global extreme value and its position information within the current sub-data stream. S4: Repeat S3 to obtain the global extrema of multiple sub-data streams, and extract the positive first peak, positive second peak, positive maximum peak, positive last peak, as well as the negative first peak, negative second peak, negative maximum peak, negative last peak and their position information accordingly. S5: Based on the positive first peak, positive second peak, positive maximum peak, positive last peak, and negative first peak, negative second peak, negative maximum peak, negative last peak and their position information extracted in S4, determine the waveform phase state and output the extracted peak features and phase state.
[0032] Specifically, the threshold processing generates a positive threshold THP and a negative threshold THN based on a preset threshold TH.
[0033] In S1, the original high-speed ultrasonic echo data stream is output to the parallel hysteresis comparison and delay unit according to K Data data and frame end flag L per clock cycle to obtain parallel data group Data(K), where K is the number of Data data in a single clock cycle, K = sampling rate / processing clock frequency. For example, if the sampling rate is 1GHz and the processing clock frequency is 125MHz, K = 8.
[0034] Parallel hysteresis comparison is specifically divided into parallel hysteresis comparison 1 and parallel hysteresis comparison 2. Parallel Hysteresis Comparison 1: The original high-speed ultrasonic echo data stream Data(K) is compared with a positive threshold and a hysteresis width. A hysteresis comparison mechanism is used to output a K-bit positive threshold comparison result level vector CP, which can suppress jitter of the input signal near the threshold. The level vector position is 1 when the input data vector jumps from below the positive threshold to above the positive threshold + hysteresis width; and 0 when it jumps from above the positive threshold to below the positive threshold - hysteresis width. The high-level peak segment of the level vector ends with the marker CP. L Set to 1.
[0035] Parallel Hysteresis Comparison 2: The original high-speed ultrasonic echo data stream is compared with a negative threshold and a hysteresis width. A hysteresis comparison mechanism is used to output a K-bit negative threshold comparison result vector CN, which can suppress jitter of the input signal near the threshold. The input data vector is set to 1 when it jumps from above the negative threshold to below the negative threshold minus the hysteresis width, and to 0 when it jumps from below the negative threshold to above the negative threshold plus the hysteresis width. The high-level peak segment of the level vector ends with a marker CP. L Set to 1.
[0036] In S2, the original high-speed ultrasonic echo data stream and the frame end flag L are first delayed by N clock cycles to obtain the sub-data stream Data0(K) and the frame end flag L0. N is equal to the delay consumed by the parallel delay comparison processing and is aligned with the parallel hysteresis comparison output.
[0037] The specific filtering of positive and negative peak sub-data streams involves selecting CP. L The flags DP6 and CP flag DP6 are obtained from the delayed sub-data stream Data0(K) when the flags and CP flags are set to 1. L Select CP L The flag and CN flag being set to 1 correspond to the delayed sub-data stream Data0(K) obtaining DN6 and the sub-data stream end flag DN6. L .
[0038] In S3, parallel pipelined extremum tracing is performed on the positive and negative peak sub-data streams respectively to obtain the local extrema of each sub-data stream segment. The specific steps are as follows: Parallel maximum / minimum tracking is performed on the DP6 sub-data stream. K parallel maximum value comparators are set up, and the sub-data stream is as follows: DP6(11) DP6(12) DP6(13)… DP6(21) DP6(22) DP6(23)… ………………………………… DP6(K1) DP6(K2) DP6(K3)… The first maximum value parallel comparator performs pipelined maximum value comparisons according to the sub-data flow directions of DP6(11) DP6(12) DP6(13)...; The second maximum value parallel comparator performs pipelined maximum value comparisons according to the sub-data flow directions of DP6(21) DP6(22) DP6(23)...; ………………………………… The Kth maximum value parallel comparator performs pipelined maximum value comparisons according to the sub-data flow directions of DP6(K1) DP6(K2) DP6(K3)...; End of sub-data stream marker DP6L When the value is high, the comparison result of each vector of the current peak segment, DPM(K), is obtained.
[0039] Parallel extreme value tracking is performed on the DN6 sub-data stream. K parallel minimum value comparators are set up, and the sub-data stream is as follows: DN6(11) DN6(12) DN6(13)… DN6(21) DN6(22) DN6(23)… ………………………………… DN6(K1) DN6(K2) DN6(K3)… The first minimum value parallel comparator performs pipelined minimum value comparisons according to the sub-data flow directions of DN6(11) DN6(12) DPN(13)...; The second minimum value parallel comparator performs pipelined minimum value comparisons according to the sub-data flow directions of DN6(21) DN6(22) DN6(23)...; ………………………………… The Kth minimum parallel comparator performs pipelined minimum comparisons according to the sub-data flow directions of DN6(K1) DN6(K2) DN6(K3)...; End of sub-data stream marker DN6 L When the value is high, the comparison result of each vector in the current peak segment, DNM(K), is obtained as the local extremum.
[0040] Next, a parallel binary tree comparison is performed on the local extrema to obtain the global extrema and their location information within the current sub-data stream: the DPM(K) vector is grouped pairwise and compared step by step to obtain the K maximum values DPM. D and the corresponding location index DPM A The DNM(K) vectors are grouped pairwise and compared step by step to obtain the minimum value DNM among these K data points. D and the corresponding position index DNM A .
[0041] Repeat step S3 to obtain the DPM for each peak segment. D DPM A DNM D DNM A Based on this, the positive first peak, positive second peak, positive highest peak, positive last peak, as well as the negative first peak, negative second peak, negative highest peak, negative last peak and their location information are extracted.
[0042] The frame end flag L0 is delayed by M clock cycles to obtain the delay flag L1, where M is equal to the delay consumed by the parallel extreme value tracking and parallel binary tree comparison processing.
[0043] In S5, peak information is extracted as follows: Positive first peak: The positive first peak value FPPA is equal to the first maximum value DPM of S4. D The first peak address FTPP is equal to the first maximum value DPM of S4. D Corresponding location index DPM A ; Secondary peak: The secondary peak value SPPA is equal to the second maximum value DPM of S4. D The positive peak address STPP is equal to the second maximum value DPM of S4. D Corresponding location index DPM A If S4 has no second maximum value, it indicates that there is no positive second peak; Positive peak: The maximum value DPM of the current segment in S4. D Compare with the maximum value in the previous section, select the larger value to update the positive peak value PPA, and at the same time update the position index corresponding to the larger value to the positive peak address TPP; Positive peak: The maximum value of S4, DPM D The value of the positive peak value LPPA is updated in real time, and the corresponding position index DPM is also added. A Update to the positive peak address LTPP.
[0044] Negative first peak: The negative first peak value FNPA is equal to the first minimum value DNM of S4. D The negative first peak address FTNP is equal to the first minimum value DNM of S4. D Corresponding position index DNM A ; Negative secondary peak: The negative secondary peak value SNPA is equal to the second minimum value DNM of S4. D The negative second peak address STNP is equal to the second minimum value DNM of S4. D Corresponding position index DNM A If S4 has no second minimum value, there is no negative secondary peak; Negative peak: The minimum value DNM of the current segment in S4 D Compare with the minimum value in the previous section, select the smaller value to update the negative peak value NPA, and at the same time update the position index corresponding to the smaller value to the negative peak address TNP; Negative final peak: Minimum value DNM of S4 D The negative peak value LNPA is updated in real time, and the corresponding position index DNM is also updated. A Update to the negative peak address LTNP.
[0045] When L1 is set to 1, it indicates that the current sub-data stream analysis is complete, and the information of the positive first peak, positive second peak, positive maximum peak, positive last peak, negative first peak, negative second peak, negative maximum peak, and negative last peak will be output.
[0046] The waveform phase PHA is output to determine the positive and negative peak values. When the positive first peak, positive second peak, and negative first peak are all valid and the position of the negative first peak is between the positions of the positive first peak and the positive second peak, PHA=1 indicates that the waveform phase is normal. When the negative first peak, negative second peak, and positive first peak are all valid and the position of the positive first peak is between the positions of the negative first peak and the negative second peak, PHA=2 indicates that the waveform phase is reversed. In other cases, PHA=0 indicates that the gate waveform is abnormal. The PHA information of the positive first peak, positive second peak, positive maximum peak, positive last peak, negative first peak, negative second peak, negative maximum peak, negative last peak, and waveform phase is output for use by the subsequent imaging system or defect discrimination module.
[0047] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Based on the technical essence of the present invention, any simple modifications, equivalent substitutions, and improvements made to the above embodiments within the spirit and principles of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A feature extraction method for ultra-high-speed peak gates based on FPGA, including: The method presets positive and negative thresholds, as well as hysteresis width, and is characterized by including the following steps: S1: The original high-speed ultrasonic echo data stream is parallelized to obtain parallel data groups by sampling K data points per clock cycle. The parallel data groups are compared with positive and negative thresholds respectively, and the hysteresis comparison results are output. S2: Align the original high-speed ultrasonic echo data stream with the hysteresis comparison result by delay, and filter out the positive and negative peak sub-data streams based on the hysteresis comparison result; S3: Perform parallel pipelined extreme value tracing on the positive and negative peak sub-data streams respectively to obtain the local extreme values of each sub-data stream segment. Compare the local extreme values to obtain the global extreme value and its position information within the current sub-data stream. S4: Repeat S3 to obtain the global extrema of multiple sub-data streams, and extract the positive first peak, positive second peak, positive maximum peak, positive last peak, as well as the negative first peak, negative second peak, negative maximum peak, negative last peak and their position information accordingly. S5: Based on the positive first peak, positive second peak, positive maximum peak, positive last peak, negative first peak, negative second peak, negative maximum peak, negative last peak and their position information extracted in S4, determine the waveform phase state and output the extracted peak features and phase state.
2. The FPGA-based ultra-high-speed peak gate feature extraction method according to claim 1, characterized in that, In S1, K is equal to the ratio of the sampling rate to the FPGA processing clock frequency. Each clock cycle, K sampled data are input in parallel, accompanied by a frame end flag. The frame end flag is used to indicate whether the parallel data group of the current clock cycle is the end of a complete sub-data stream.
3. The FPGA-based ultra-high-speed peak gate feature extraction method according to claim 1, characterized in that, In S1, the hysteresis comparison result is a vector of positive and negative threshold comparison results and its peak segment end marker. The hysteresis comparison between the parallel data group and the positive threshold is specifically as follows: When the sampled data in the parallel data group jumps from below the positive threshold to above "positive threshold + hysteresis width", the vector position is 1; When the sampled data in the parallel data group jumps from above the positive threshold to below "positive threshold - hysteresis width", the vector position is 0 and a peak end marker is generated; The hysteresis comparison between parallel data sets and negative thresholds is specifically as follows: When the sampled data in the parallel data group jumps from above the negative threshold to below "negative threshold - hysteresis width", the vector position is 1; When the sampled data in the parallel data group jumps from below the negative threshold to above "negative threshold + hysteresis width", the vector position is 0 and a peak end marker is generated.
4. The FPGA-based ultra-high-speed peak gate feature extraction method according to claim 1, characterized in that, In S2, the filtering of positive and negative peak sub-data streams is specifically as follows: Based on the position of 1 in the positive threshold comparison result vector, the sampled data at the corresponding position is extracted from the original high-speed data stream after delay alignment to form a positive peak sub-data stream; Based on the positions where 1 is found in the negative threshold comparison result vector, the sampled data at the corresponding positions are extracted to form a negative peak sub-data stream.
5. The FPGA-based ultra-high-speed peak gate feature extraction method according to claim 1, characterized in that, In S3, extreme value tracking uses K parallel comparators, each of which independently tracks the local extreme values of a sub-data stream.
6. The FPGA-based ultra-high-speed peak gate feature extraction method according to claim 1, characterized in that, In S4: The first and second positive peaks are the global maximum values of the first and second sub-data streams, respectively; the highest positive peak is the global maximum value across all windows; and the last positive peak is the global maximum value of the last window. The negative first peak and negative second peak are the global minimum values of the first and second sub-data streams, respectively; the negative maximum peak is the global minimum value of all windows; and the negative final peak is the global minimum value of the last window.
7. The FPGA-based ultra-high-speed peak gate feature extraction method according to claim 1, characterized in that, In S5: When the positive first peak, positive second peak, and negative first peak are all valid, and the position of the negative first peak is between the positive first peak and the positive second peak, the phase is considered normal. When the negative first peak, negative second peak, and positive first peak are all valid and the position of the positive first peak is between the negative first peak and the negative second peak, a phase reversal is determined. Otherwise, the phase is determined to be abnormal.
8. The FPGA-based ultra-high-speed peak gate feature extraction method according to claim 1, characterized in that, The hysteresis width is preset based on the system noise level; the higher the noise, the greater the hysteresis width.
9. The FPGA-based ultra-high-speed peak gate feature extraction method according to claim 1, characterized in that, It also includes a delay step: delaying the frame end flag that accompanies the original high-speed data stream by M clock cycles, where M is equal to the number of clock cycles consumed by the extreme value tracking and binary tree comparison processing in S3. The delayed frame end flag is used to control the synchronous output of peak features and phase states in S5.
10. An FPGA-based ultra-high-speed peak gate feature extraction system, characterized in that, include: The parallel hysteresis comparison module is used to parallelize the original high-speed ultrasonic echo data stream by taking K samples per clock cycle to obtain parallel data groups. The parallel data groups are compared with the positive threshold and hysteresis width, and the negative threshold and hysteresis width respectively, and the positive and negative threshold comparison result vectors and their peak segment end markers are output. The data filtering module is used to align the raw high-speed ultrasonic echo data stream with the hysteresis comparison, and filter out the positive and negative peak sub-data streams based on the hysteresis comparison results. The extreme value tracking and binary tree comparison module is used to perform parallel pipelined extreme value tracking on the positive and negative peak sub-data streams respectively, obtain the local extreme values of each sub-data stream segment, compare each local extreme value, and obtain the global extreme value and its position information in the current sub-data stream; The multi-peak extraction module is used to repeatedly call the extreme value tracking and binary tree comparison module to obtain the global extreme values of multiple sub-data streams, and extract the positive first peak, positive second peak, positive maximum peak, positive last peak, as well as the negative first peak, negative second peak, negative maximum peak, negative last peak and their position information. The phase discrimination and output module is used to determine the waveform phase state based on the positive first peak, positive second peak, positive maximum peak, positive last peak, negative first peak, negative second peak, negative maximum peak, negative last peak and their position information extracted by the multi-peak extraction module, and output the extracted peak features and phase state.