Gate-level netlist traceability method and system based on multi-level abstraction and intelligent learning

Abstract

The application discloses a gate-level netlist tracing method and system based on multi-level abstraction and intelligent learning, and relates to the technical field of integrated circuit design.The method comprises the following steps: dividing a gate-level netlist into multiple subgraphs; identifying basic logic units, function blocks and macro structures in the subgraphs; taking the basic logic units, function blocks and macro structures as nodes, determining edges between the nodes according to global connection relationships of the nodes in the gate-level netlist, and constructing a logic representation layer graph; extracting a feature vector of the logic representation layer graph, and performing similarity calculation on the feature vector and a feature vector of a reference graph to select several most similar reference graphs as candidate reference graphs; dividing the logic representation layer graph into multiple function subgraphs, and dividing the candidate reference graphs into multiple candidate function subgraphs; and using a graph attention network model to calculate similarity scores between the function subgraphs and the candidate function subgraphs matched with the function subgraphs, and determining a tracing result.The application can realize efficient, robust and verifiable tracing of the gate-level netlist.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a gate-level netlist tracing method and system based on multi-level abstraction and intelligent learning. Background Technology

[0002] The integrated circuit industry has entered an era of globalized division of labor and IP reuse. In the chip design process, Register Transfer Level (RTL) code needs to undergo automated steps such as logic synthesis, optimization, and placement and routing to ultimately generate a gate-level netlist. This process introduces numerous operations such as structural reorganization, logic optimization, and timing adjustments, resulting in significant changes in the structure, hierarchy, naming, and timing relationships between the gate-level netlist and the original RTL code. The direct mapping between the two is extremely ambiguous. This phenomenon poses a severe challenge to the protection of intellectual property (IP) in integrated circuits, hardware malware detection, design traceability, and compliance verification.

[0003] The core task of gate-level netlist tracing technology is to identify the IP address or functional module from which a value originates from a gate-level netlist in the absence of RTL code or design documentation. Currently, gate-level netlist tracing technology mainly includes the following two categories: The first category is the traditional method based on structural feature comparison and functional test response matching. Structural feature comparison includes critical path analysis and functional unit topology matching, while functional test response matching indirectly determines functional consistency by applying test vectors and comparing responses. This type of method is effective when the overall optimization level is low and the structural changes are small. However, when there are aggressive optimizations (such as logic reorganization, resource sharing, clock gating, etc.), the correspondence between the netlist structure and the original design is severely disrupted, and the robustness of this type of method decreases significantly, making it difficult to achieve accurate tracing.

[0004] The second category is intelligent methods based on circuit representation learning. In recent years, with the application of deep learning technologies such as Graph Neural Networks (GNNs) in circuit analysis, existing research has begun to model gate-level netlists as graph structures and learn their deep functional semantic representations through GNNs, thereby overcoming the interference caused by structural changes to some extent. These methods can determine the correlation between the netlist and RTL code at the functional level, possessing strong semantic understanding capabilities and enabling higher-level semantic tracing. However, these methods still have the following shortcomings in practical applications: Poor interpretability: Most existing deep learning models are end-to-end black box structures, making it difficult to explain the key circuit structures on which their origin conclusions depend, and failing to provide designers with verifiable location information.

[0005] Insufficient generalization ability: The performance of deep learning models is highly dependent on the composition of the training dataset. When faced with unfamiliar netlists generated by different architectures, processes, or synthesis strategies, the recognition accuracy often drops significantly.

[0006] Low processing efficiency: Large-scale gate-level netlists contain millions or even tens of millions of logic gates. The computational overhead of constructing the entire graph and performing graph neural network calculations is extremely high, making it difficult to deploy and apply in practical engineering. Summary of the Invention

[0007] To address some or all of the technical problems existing in the prior art, this invention provides a gate-level netlist tracing method and system based on multi-level abstraction and intelligent learning.

[0008] The technical solution of the present invention is as follows: Firstly, a gate-level netlist tracing method based on multi-level abstraction and intelligent learning is provided, including: Divide the gate-level netlist to be traced into multiple subgraphs; Identify the basic logic unit in each subgraph, identify the functional block based on the basic logic unit, and identify the macro structure by analyzing the data flow and control signals between all functional blocks based on the functional block. The identified basic logical units, functional blocks, and macroscopic structures are used as nodes to construct a node set. The edges between nodes are determined based on the global connection relationship of all nodes in the gate-level netlist. The logical representation layer graph is constructed based on the node set and the edges between nodes. Extract the feature vector of the logical representation layer graph and calculate the similarity with the feature vector of the reference graph in the preset reference intellectual property library, and select the most similar reference graphs as candidate reference graphs. Based on the macroscopic structural boundary corresponding to the logical representation layer diagram, the logical representation layer diagram is divided into multiple functional sub-diagrams. Based on the macroscopic structural boundary corresponding to each candidate reference diagram, each candidate reference diagram is divided into multiple candidate functional sub-diagrams. A pre-trained graph attention network model is used to compute similarity scores between a feature subgraph and its paired candidate feature subgraphs. The source tracing result is determined based on the calculated similarity score.

[0009] Furthermore, in some implementations, the gate-level netlist to be traced is divided into multiple subgraphs using the Metis graph partitioning algorithm or a connectivity analysis-based partitioning algorithm.

[0010] Furthermore, in some embodiments, the basic logic unit includes AND gate, OR gate, NOT gate, NAND gate, and flip-flop; the functional block includes combinational logic block and arithmetic unit; and the macroscopic structure includes control path, data path, and finite state machine.

[0011] Furthermore, in some implementations, a predefined rule-based first aggregator or a pre-trained first graph neural network model is used to identify the basic logical units in each subgraph; and a predefined rule-based second aggregator or a pre-trained second graph neural network model is used to identify the functional blocks.

[0012] Furthermore, in some embodiments, the feature vector integrates at least two of the following types of features: structural features, functional features, and serialization features; The structural features include at least one of the following: node degree distribution histogram, graph clustering coefficient, graph diameter, graph average path length, and distribution of the number and size of connected components. The functional characteristics include at least one of the following: node type distribution, ratio of registers to combinational logic, and node type sequence on the critical path. The serialization features include at least one of the node color label distribution features generated based on Weisfeiler-Lehman graph kernel iteration and the graph vector representation generated based on random walk.

[0013] Furthermore, in some embodiments, the similarity calculation employs cosine similarity or Euclidean distance.

[0014] Furthermore, in some embodiments, the functional subgraph includes an arithmetic logic unit subgraph, a control finite state machine subgraph, and a memory interface subgraph.

[0015] Furthermore, in some implementations, the calculation of a similarity score between a feature subgraph and its paired candidate feature subgraph using a pre-trained graph attention network model includes: Pair a functional subgraph with a candidate functional subgraph of the same functional type to form a subgraph pair; The subgraph is input to the graph attention network model to obtain the similarity score output by the graph attention network model. Among them, the graph attention network model adopts a graph matching network structure based on graph attention mechanism. It aggregates the features of neighboring nodes by calculating the attention coefficients between nodes and outputs a scalar between 0 and 1 as a similarity score.

[0016] Furthermore, in some implementations, determining the source tracing result based on the calculated similarity score includes: Based on the similarity scores corresponding to each candidate functional subgraph, a comprehensive similarity score for the candidate reference graph is obtained by weighted aggregation of the similarity scores. Based on the comprehensive similarity score of each candidate reference graph, the tracing result is determined. The tracing result includes: the candidate reference graph with the highest comprehensive similarity score and its corresponding gate-level netlist and RTL code, and several candidate functional subgraphs with the highest similarity scores corresponding to the candidate reference graph with the highest comprehensive similarity score.

[0017] Secondly, a gate-level netlist tracing system based on multi-level abstraction and intelligent learning is also provided, including: The netlist partitioning module is used to divide the gate-level netlist to be traced into multiple subgraphs; The hierarchical function identification module is used to identify the basic logical units in each sub-graph, identify the function blocks based on the basic logical units, and identify the macro structure by analyzing the data flow and control signals between all function blocks. The logic representation layer graph construction module is used to construct a node set using the identified basic logic units, functional blocks and macro structure as nodes, determine the edges between nodes based on the global connection relationship of all nodes in the gate-level netlist, and construct the logic representation layer graph based on the node set and the edges between nodes. The feature extraction and coarse screening module is used to extract the feature vector of the logical representation layer graph and perform similarity calculation with the feature vector of the reference graph in the preset reference intellectual property library, and select the most similar reference graphs as candidate reference graphs. The subgraph partitioning module is used to divide the logical representation layer graph into multiple functional subgraphs based on the macroscopic structural boundary corresponding to the logical representation layer graph, and to divide each candidate reference graph into multiple candidate functional subgraphs based on the macroscopic structural boundary corresponding to each candidate reference graph. The graph neural network matching module is used to compute similarity scores between a feature subgraph and its paired candidate feature subgraphs using a pre-trained graph attention network model. The source tracing result determination module is used to determine the source tracing result based on the calculated similarity score; The storage module is used to store the reference intellectual property library and the graph attention network model.

[0018] The main advantages of the technical solution of this invention are as follows: The gate-level netlist tracing method and system based on multi-level abstraction and intelligent learning of this invention transforms the gate-level netlist layer by layer into a semantically clear and compact logical representation layer graph through multi-level abstraction, effectively removing the structural differences introduced by comprehensive optimization and achieving tracing improvement from physical details to functional semantics. At the same time, it adopts a hierarchical matching strategy of "feature coarse screening - subgraph partitioning - graph attention network model fine matching", combined with a pre-built reference intellectual property library, which can ensure matching accuracy and interpretability while significantly reducing computational overhead, and achieve efficient, robust and verifiable tracing of gate-level netlists. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and constitute a part of this invention, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings: Figure 1 A flowchart illustrating a gate-level netlist tracing method based on multi-level abstraction and intelligent learning, provided for an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a gate-level netlist tracing system based on multi-level abstraction and intelligent learning, provided as an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0021] The technical solutions provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] refer to Figure 1 This invention provides a gate-level netlist tracing method based on multi-level abstraction and intelligent learning, which includes the following steps: Step 1: Divide the gate-level netlist to be traced into multiple subgraphs; Step 2: Identify the basic logic units in each subgraph, identify the functional blocks based on the basic logic units, and identify the macro structure by analyzing the data flow and control signals between all functional blocks. Step 3: Construct a node set using the identified basic logical units, functional blocks, and macroscopic structures as nodes; determine the edges between nodes based on the global connection relationships of all nodes in the gate-level netlist; and construct a logical representation layer graph based on the node set and the edges between nodes. Step 4: Extract the feature vector of the logical representation layer graph and calculate the similarity with the feature vector of the reference graph in the preset reference intellectual property library, and select the most similar reference graphs as candidate reference graphs. Step 5: Based on the macroscopic structural boundary corresponding to the logical representation layer diagram, divide the logical representation layer diagram into multiple functional sub-diagrams. Based on the macroscopic structural boundary corresponding to each candidate reference diagram, divide each candidate reference diagram into multiple candidate functional sub-diagrams respectively. Step 6: Calculate the similarity score between the functional subgraph and its paired candidate functional subgraph using a pre-trained graph attention network model; Step 7: Determine the source tracing result based on the calculated similarity score.

[0023] In this embodiment of the invention, the gate-level netlist to be traced is obtained according to actual needs.

[0024] In this embodiment of the invention, the reference intellectual property library is pre-constructed using existing known data. The reference intellectual property library includes: multiple known RTL codes and their corresponding gate-level netlists, a reference graph corresponding to each gate-level netlist, and a feature vector for each reference graph. Specifically, the reference graphs corresponding to the gate-level netlists are pre-constructed, and the construction method is the same as the construction method for the logical representation layer graph corresponding to the gate-level netlist to be traced; the feature vectors of the reference graphs are pre-extracted, and the extraction method is the same as the extraction method for the feature vectors of the logical representation layer graph.

[0025] The gate-level netlist tracing method provided in this invention, based on multi-level abstraction and intelligent learning, transforms the gate-level netlist layer by layer into a semantically clear and compact logical representation layer graph through multi-level abstraction. This effectively removes the structural differences introduced by comprehensive optimization, achieving improved tracing from physical details to functional semantics. Simultaneously, by employing a hierarchical matching strategy of "feature coarse screening—subgraph partitioning—graph attention network model fine matching," combined with a pre-built reference intellectual property library, it can ensure matching accuracy and interpretability while significantly reducing computational overhead, achieving efficient, robust, and verifiable tracing of gate-level netlists.

[0026] Furthermore, in this embodiment of the invention, in order to reduce invalid processing and computational workload, before dividing the gate-level netlist to be traced into multiple subgraphs, the method further includes: performing syntax parsing and cleaning on the gate-level netlist to be traced to remove comments, redundant spaces and invalid statements.

[0027] Furthermore, in this embodiment of the invention, the gate-level netlist to be traced is divided into multiple subgraphs with tightly connected internal connections and sparsely connected external connections using the Metis graph partitioning algorithm or a partitioning algorithm based on connectivity analysis, thereby providing good locality for subsequent function identification.

[0028] The number of subgraphs can be set according to the specific needs. For example, for a netlist with a scale of millions of gates, the number of subgraphs can be set to 100-500.

[0029] Furthermore, in this embodiment of the invention, the basic logic unit includes AND gate, OR gate, NOT gate, NAND gate, and flip-flop; the functional block includes combinational logic block and arithmetic unit; the macroscopic structure includes control path, data path, and finite state machine.

[0030] In this embodiment of the invention, a predefined rule-based first aggregator or a pre-trained first graph neural network model is used to identify the basic logical units in each subgraph.

[0031] In this embodiment of the invention, the first aggregator takes the subgraph as input and outputs the basic logic unit category to which each gate-level node in the subgraph belongs.

[0032] The first aggregator is an expert system-based function identification method that identifies basic logic units through predefined pattern matching rules. These pattern matching rules can be predefined based on the circuit structure characteristics of common basic logic units.

[0033] In this embodiment of the invention, the first graph neural network model takes a subgraph as input and outputs the basic logic unit category to which each gate-level node in the subgraph belongs.

[0034] The first graph neural network model is pre-trained using a first training dataset, which is constructed using existing known data. The first training dataset includes the original graph of the gate-level netlist and the basic logical unit category label to which each gate-level node in the original graph belongs.

[0035] Specifically, using the first training dataset, a first graph neural network model is trained through backpropagation and gradient descent. The loss function used during training can be the cross-entropy loss function.

[0036] In this embodiment of the invention, a predefined rule-based second aggregator or a pre-trained second graph neural network model is used to identify functional blocks.

[0037] In this embodiment of the invention, the second aggregator takes the subgraph of the basic logical unit category to which the labeled nodes belong as input and outputs the functional block category to which different regions in the subgraph belong.

[0038] The second aggregator is an expert system-based function identification method that identifies functional blocks using predefined pattern matching rules. These pattern matching rules can be predefined based on the circuit structure characteristics of common functional units.

[0039] In this embodiment of the invention, the second graph neural network model takes the subgraph of the basic logical unit category to which the labeled nodes belong as input and outputs the functional block category to which different regions in the subgraph belong.

[0040] The second neural network model is pre-trained using a second training dataset, which is constructed using existing known data. The second training dataset includes the original graph to which the labeled nodes belong as basic logical unit categories and the functional block category labels to which different regions in the original graph belong.

[0041] Specifically, using the second training dataset, a second graph neural network model is trained via backpropagation and gradient descent. The cross-entropy loss function can be used during training.

[0042] In this embodiment of the invention, based on identifying all functional blocks in a subgraph, the macroscopic structure is identified by analyzing the data flow and control signals between all functional blocks in the subgraph. These control signals include, for example, enable signals and selection signals.

[0043] In this embodiment of the invention, by using an aggregator or graph neural network model to identify functional units, it is possible to quickly identify different functional units and ensure identification accuracy.

[0044] Furthermore, in this embodiment of the invention, a node set is constructed using all identified basic logic units, all functional blocks, and all macroscopic structures as nodes. The edges between nodes are determined based on the global connection relationships of all nodes in the gate-level netlist. A logical representation layer graph is constructed based on the node set and the edges between nodes.

[0045] In this embodiment of the invention, the logical representation layer graph is a hierarchical graph structure containing nodes of multiple abstract levels; the edges between nodes include connecting edges and constitutive edges. Connecting edges are used to represent the data flow or control flow relationship between different nodes, and constitutive edges are used to represent the inclusion relationship between macroscopic structure nodes and their contained functional block nodes, and between functional block nodes and their contained basic logical unit nodes.

[0046] In this embodiment of the invention, a hierarchical graph structure containing nodes of multiple abstract levels and distinguishing between connecting edges and constitutive edges is constructed as a logical representation layer graph. This not only fully preserves the data flow and control flow relationships between functional units, but also clearly expresses the inclusion hierarchy between macro structure, functional blocks and basic logical units. Thus, while avoiding node conflicts, a high degree of integration of functional semantics and structural hierarchy is achieved, providing a graph representation with clear structure and rich semantics for subsequent multi-granularity tracing.

[0047] Furthermore, in this embodiment of the invention, the feature vector integrates at least two of the following types of features: structural features, functional features, and serialization features; Structural features include at least one of the following: node degree distribution histogram, graph clustering coefficient, graph diameter, graph average path length, and distribution of the number and size of connected components; Functional characteristics include at least one of the following: node type distribution, the ratio of registers to combinational logic, and the node type sequence on the critical path; The serialization features include at least one of the node color label distribution features generated based on the Weisfeiler-Lehman graph kernel iteration and the graph vector representation generated based on random walk.

[0048] In this embodiment of the invention, the graph diameter and the average path length can be determined by approximate calculation.

[0049] In this embodiment of the invention, the node type distribution represents the number or proportion of various types of nodes in the logical representation layer diagram. The node type indicates the basic logical unit category, functional block category, or macroscopic structure category to which the node belongs.

[0050] In this embodiment of the invention, the critical path is determined specifically based on the actual situation. For example, the longest combined path is selected as the critical path.

[0051] In this embodiment of the invention, the node color label distribution features generated based on the Weisfeiler-Lehman graph kernel iteration are obtained in the following way: the nodes in the graph are refined through multiple rounds of iteration, and the color labels are updated according to the current colors of the nodes and their neighboring nodes in each round. The color distribution of all nodes after iteration is statistically analyzed to form a high-dimensional feature vector as the node color label distribution features.

[0052] In this embodiment of the invention, the graph vector representation generated based on random walks is obtained in the following way: a large number of random walks are performed in the graph, and the sequence of node types visited in each walk is regarded as sentences in natural language. The bag-of-words model or Doc2Vec method is used to convert these sequences into a vector representation of the entire graph to obtain the graph vector representation.

[0053] In this embodiment of the invention, the feature vector of the logic representation layer graph is extracted in the following way: at least two of the following types of features are extracted from the logic representation layer graph: structural features, functional features, and serialization features; the extracted features are concatenated into a complete feature vector to obtain the feature vector of the logic representation layer graph.

[0054] In this embodiment of the invention, feature vectors are constructed by fusing structural features, functional features and serialization features. This enables a comprehensive characterization of the essential attributes of the logical representation layer graph from multiple dimensions, including topological morphology, functional composition and structural pattern, forming a highly complementary graph representation. This allows for more accurate and robust reference graph screening in the feature coarse screening stage, significantly reducing the computational overhead of subsequent fine matching.

[0055] Furthermore, in this embodiment of the invention, in step 4, the similarity calculation uses cosine similarity or Euclidean distance.

[0056] Specifically, when cosine similarity is used for similarity calculation, the cosine similarity between the feature vector of the logical representation layer graph and the feature vector of each reference graph is calculated, and the reference graphs with the highest cosine similarity are selected as candidate reference graphs. When Euclidean distance is used for similarity calculation, the Euclidean distance between the feature vector of the logical representation layer graph and the feature vector of each reference graph is calculated, and the reference graphs with the smallest Euclidean distance are selected as candidate reference graphs.

[0057] In this embodiment of the invention, cosine similarity or Euclidean distance is used for similarity calculation, which can accurately select the most similar reference image from a massive number of reference images with extremely low computational overhead, greatly reducing the size of candidate reference images for subsequent fine matching, thereby significantly improving the overall source tracing efficiency while ensuring matching accuracy.

[0058] Furthermore, considering that when facing large-scale designs, even if candidate reference diagrams have been selected from the reference intellectual property library, the overhead of performing full-map matching on the candidate reference diagrams is still huge, in this embodiment of the invention, based on the macroscopic structural boundary corresponding to the logical representation layer diagram, the logical representation layer diagram is divided into multiple functional sub-diagrams, and based on the macroscopic structural boundary corresponding to each candidate reference diagram, each candidate reference diagram is divided into multiple candidate functional sub-diagrams respectively.

[0059] In this embodiment of the invention, the type of functional sub-graph is specifically set according to actual needs, such as including arithmetic logic unit sub-graph, control finite state machine sub-graph, and memory interface sub-graph.

[0060] Further, in this embodiment of the invention, calculating the similarity score between a functional subgraph and its paired candidate functional subgraph using a pre-trained graph attention network model includes: Pair a functional subgraph with a candidate functional subgraph of the same functional type to form a subgraph pair; The subgraph is input to the graph attention network model to obtain the similarity score output by the graph attention network model.

[0061] In this embodiment of the invention, a functional subgraph can be paired with candidate functional subgraphs of multiple candidate reference graphs to form multiple subgraph pairs.

[0062] In this embodiment of the invention, the graph attention network model adopts a graph matching network structure based on the graph attention mechanism. It aggregates the features of neighboring nodes by calculating the attention coefficients between nodes and outputs a scalar between 0 and 1 as a similarity score.

[0063] Specifically, the graph attention network model calculates the weights of its neighboring nodes for each node in the input functional subgraph through an attention mechanism, aggregates them to generate a node embedding vector, and then obtains and outputs a similarity score between 0 and 1 through node-level alignment and graph-level pooling.

[0064] In this embodiment of the invention, the graph attention network model is pre-trained using a third training dataset, which is constructed using existing known data. The third training dataset includes functional subgraph pairs and their corresponding similarity score labels.

[0065] Specifically, a graph attention network model is trained using a third training dataset via backpropagation and gradient descent. The loss function during training can be the mean squared error between the model output and the label.

[0066] In this embodiment of the invention, by pairing subgraphs of the same functional type and inputting them into a graph attention network model for fine matching, the attention mechanism is used to automatically focus on key structural features and output similarity scores, which can achieve high-precision, fine-grained subgraph-level similarity evaluation. This not only improves the accuracy of matching, but also provides an interpretable basis for tracing conclusions.

[0067] Further, in this embodiment of the invention, in step 7, determining the source tracing result based on the calculated similarity score includes: Based on the similarity scores corresponding to each candidate functional subgraph, a comprehensive similarity score for the candidate reference graph is obtained by weighted aggregation of the similarity scores. Based on the comprehensive similarity score of each candidate reference graph, the source tracing results are determined. The source tracing results include: the candidate reference graph with the highest comprehensive similarity score and its corresponding gate-level netlist and RTL code, and several candidate functional subgraphs with the highest similarity scores corresponding to the candidate reference graph with the highest comprehensive similarity score.

[0068] In this embodiment of the invention, the comprehensive similarity score of the candidate reference map is obtained by weighted aggregation of the similarity scores of each functional sub-graph, and the reference map with the highest score and its key functional sub-graph information are output. This can significantly enhance the interpretability of the tracing results while ensuring the accuracy of the tracing.

[0069] Furthermore, in another embodiment of the present invention, when the tracing task is only for a specific functional module, in step 6, only a pre-trained graph attention network model is used to calculate the similarity score between the functional subgraph corresponding to the specific functional module and its paired candidate functional subgraph. In step 7, the tracing result is determined based on the calculated similarity scores corresponding to each candidate functional subgraph. The tracing result includes the candidate functional subgraph with the highest similarity score and its corresponding candidate reference graph, gate-level netlist, and RTL code.

[0070] refer to Figure 2 This invention also provides a gate-level netlist tracing system based on multi-level abstraction and intelligent learning, the system comprising: Netlist partitioning module 100 is used to partition the gate-level netlist to be traced into multiple subgraphs; The hierarchical function identification module 200 is used to identify the basic logic unit in each sub-graph, identify the function block based on the basic logic unit, and identify the macro structure by analyzing the data flow and control signals between all function blocks. The logic representation layer graph construction module 300 is used to construct a node set using the identified basic logic units, functional blocks and macro structures as nodes, determine the edges between nodes based on the global connection relationship of all nodes in the gate-level netlist, and construct a logic representation layer graph based on the node set and the edges between nodes. The feature extraction and coarse screening module 400 is used to extract the feature vector of the logical representation layer graph and perform similarity calculation with the feature vector of the reference graph in the preset reference intellectual property library, and select the most similar reference graphs as candidate reference graphs. The subgraph partitioning module 500 is used to divide the logical representation layer graph into multiple functional subgraphs based on the macroscopic structural boundary corresponding to the logical representation layer graph, and to divide each candidate reference graph into multiple candidate functional subgraphs based on the macroscopic structural boundary corresponding to each candidate reference graph. Graph neural network matching module 600 is used to compute similarity scores between a feature subgraph and its paired candidate feature subgraph using a pre-trained graph attention network model; The source tracing result determination module 700 is used to determine the source tracing result based on the calculated similarity score; Storage module 800 is used to store a reference intellectual property library and a graph attention network model.

[0071] The above modules are hardware structures corresponding to the above method steps. The specific working principles and beneficial effects of each module can be found in the above method, and will not be repeated here.

[0072] The gate-level netlist tracing system provided in this invention, based on multi-level abstraction and intelligent learning, transforms the gate-level netlist layer by layer into a semantically clear and compact logical representation layer graph through multi-level abstraction. This effectively removes the structural differences introduced by comprehensive optimization, achieving improved tracing from physical details to functional semantics. Simultaneously, by employing a hierarchical matching strategy of "feature coarse screening—subgraph partitioning—graph attention network model fine matching," combined with a pre-built reference intellectual property library, it can ensure matching accuracy and interpretability while significantly reducing computational overhead, achieving efficient, robust, and verifiable tracing of gate-level netlists.

[0073] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Additionally, the terms "front," "back," "left," "right," "upper," and "lower" in this document refer to the placement shown in the accompanying drawings.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate-level netlist tracing method based on multi-level abstraction and intelligent learning, characterized in that, include: Divide the gate-level netlist to be traced into multiple subgraphs; The basic logic units in each subgraph are identified, and functional blocks are identified based on the basic logic units. Based on the functional blocks, the macro structure is identified by analyzing the data flow and control signals between all functional blocks. The basic logic units include AND gates, OR gates, NOT gates, NAND gates, and flip-flops. The functional blocks include combinational logic blocks and arithmetic units. The macro structure includes control paths, data paths, and finite state machines. The identified basic logical units, functional blocks, and macroscopic structures are used as nodes to construct a node set. The edges between nodes are determined based on the global connection relationship of all nodes in the gate-level netlist. The logical representation layer graph is constructed based on the node set and the edges between nodes. Extract the feature vector of the logical representation layer graph and calculate the similarity with the feature vector of the reference graph in the preset reference intellectual property library, and select the most similar reference graphs as candidate reference graphs. Based on the macroscopic structural boundary corresponding to the logical representation layer diagram, the logical representation layer diagram is divided into multiple functional sub-diagrams. Based on the macroscopic structural boundary corresponding to each candidate reference diagram, each candidate reference diagram is divided into multiple candidate functional sub-diagrams. A pre-trained graph attention network model is used to compute similarity scores between a feature subgraph and its paired candidate feature subgraphs. The source tracing result is determined based on the calculated similarity score.

2. The gate-level netlist tracing method based on multi-level abstraction and intelligent learning according to claim 1, characterized in that, The gate-level netlist to be traced is divided into multiple subgraphs using the Metis graph partitioning algorithm or a partitioning algorithm based on connectivity analysis.

3. The gate-level netlist tracing method based on multi-level abstraction and intelligent learning according to claim 1, characterized in that, The basic logical units in each subgraph are identified using a predefined rule-based first aggregator or a pre-trained first graph neural network model; the functional blocks are identified using a predefined rule-based second aggregator or a pre-trained second graph neural network model.

4. The gate-level netlist tracing method based on multi-level abstraction and intelligent learning according to claim 1, characterized in that, The feature vector integrates at least two of the following types of features: structural features, functional features, and serialization features; The structural features include at least one of the following: node degree distribution histogram, graph clustering coefficient, graph diameter, graph average path length, and distribution of the number and size of connected components. The functional characteristics include at least one of the following: node type distribution, ratio of registers to combinational logic, and node type sequence on the critical path. The serialization features include at least one of the node color label distribution features generated based on Weisfeiler-Lehman graph kernel iteration and the graph vector representation generated based on random walk.

5. The gate-level netlist tracing method based on multi-level abstraction and intelligent learning according to claim 1, characterized in that, The similarity calculation uses cosine similarity or Euclidean distance.

6. The gate-level netlist tracing method based on multi-level abstraction and intelligent learning according to claim 1, characterized in that, The functional sub-graphs include an arithmetic logic unit sub-graph, a control finite state machine sub-graph, and a memory interface sub-graph.

7. The gate-level netlist tracing method based on multi-level abstraction and intelligent learning according to claim 1, characterized in that, The calculation of similarity scores between a feature subgraph and its paired candidate feature subgraphs using a pre-trained graph attention network model includes: Pair a functional subgraph with a candidate functional subgraph of the same functional type to form a subgraph pair; The subgraph is input to the graph attention network model to obtain the similarity score output by the graph attention network model. Among them, the graph attention network model adopts a graph matching network structure based on graph attention mechanism. It aggregates the features of neighboring nodes by calculating the attention coefficients between nodes and outputs a scalar between 0 and 1 as a similarity score.

8. The gate-level netlist tracing method based on multi-level abstraction and intelligent learning according to claim 1, characterized in that, The process of determining the source tracing result based on the calculated similarity score includes: Based on the similarity scores corresponding to each candidate functional subgraph, a comprehensive similarity score for the candidate reference graph is obtained by weighted aggregation of the similarity scores. Based on the comprehensive similarity score of each candidate reference graph, the tracing result is determined. The tracing result includes: the candidate reference graph with the highest comprehensive similarity score and its corresponding gate-level netlist and RTL code, and several candidate functional subgraphs with the highest similarity scores corresponding to the candidate reference graph with the highest comprehensive similarity score.

9. A gate-level netlist tracing system based on multi-level abstraction and intelligent learning, characterized in that, include: The netlist partitioning module is used to divide the gate-level netlist to be traced into multiple subgraphs; The hierarchical function identification module is used to identify the basic logic units in each subgraph, identify function blocks based on the basic logic units, and identify the macro structure by analyzing the data flow and control signals between all function blocks. The basic logic units include AND gates, OR gates, NOT gates, NAND gates, and flip-flops. The function blocks include combinational logic blocks and arithmetic units. The macro structure includes control paths, data paths, and finite state machines. The logic representation layer graph construction module is used to construct a node set using the identified basic logic units, functional blocks and macro structure as nodes, determine the edges between nodes based on the global connection relationship of all nodes in the gate-level netlist, and construct the logic representation layer graph based on the node set and the edges between nodes. The feature extraction and coarse screening module is used to extract the feature vector of the logical representation layer graph and perform similarity calculation with the feature vector of the reference graph in the preset reference intellectual property library, and select the most similar reference graphs as candidate reference graphs. The subgraph partitioning module is used to divide the logical representation layer graph into multiple functional subgraphs based on the macroscopic structural boundary corresponding to the logical representation layer graph, and to divide each candidate reference graph into multiple candidate functional subgraphs based on the macroscopic structural boundary corresponding to each candidate reference graph. The graph neural network matching module is used to compute similarity scores between a feature subgraph and its paired candidate feature subgraphs using a pre-trained graph attention network model. The source tracing result determination module is used to determine the source tracing result based on the calculated similarity score; The storage module is used to store the reference intellectual property library and the graph attention network model.

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