A method for waveguide chip layout, fabrication and testing

Abstract

This application provides a method for waveguide chip layout, fabrication, and testing, relating to the field of optical chip technology. In the layout stage, several chip design areas exist on the wafer, and waveguide design areas exist within these chip design areas. The design polarization period corresponding to the waveguide design area is derived from the deviation range of the quasi-phase-matched polarization period. The quasi-phase-matched polarization period deviates from the wafer fabrication process due to certain process errors. By scanning parameters within this deviation range, a design polarization period with a greater number than the chip design areas is determined and configured in a one-to-one correspondence with each waveguide design area. This results in a greater number of waveguide design areas than chip design areas, enabling more precise coverage of the process error range and increasing the number of waveguides meeting the quasi-phase-matching conditions. This effectively solves the problems of reduced waveguide nonlinear efficiency, decreased output power, and lower yield caused by deviations in the quasi-phase-matched polarization period from the design value.

Description

Technical Field

[0001] This application relates to the field of optical chip technology, and more specifically, to a method for waveguide chip layout, fabrication, and testing. Background Technology

[0002] Periodically polarized lithium niobate (PPLN) achieves quasi-phase-matching (QPM) through periodic inversion of ferroelectric domains. It is a key device for high-efficiency laser wavelength conversion and is widely used in quantum information, optical communication and other fields.

[0003] In nonlinear applications based on PPLN waveguides, the domain period must satisfy the QPM condition, which is affected by various factors such as film thickness, ridge etching depth, and sidewall tilt angle. This means that during actual fabrication, due to process errors, the polarization period required to satisfy the QPM often deviates from the design value, resulting in the final waveguide failing to meet the QPM condition. This leads to problems such as reduced nonlinear efficiency, decreased output power, and lower yield. Summary of the Invention

[0004] The purpose of this application is to provide a method for waveguide chip layout, fabrication, and testing to overcome the aforementioned technical problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: One aspect of this application provides a waveguide chip layout method, the method comprising: Obtain the deviation range of the quasi-phase-matched (QPM) polarization period, which corresponds to the process error range of the wafer fabrication chip; Parameter scanning is performed within the deviation range to obtain multiple design polarization periods, wherein the number of multiple design polarization periods is greater than the number of chip design areas on the wafer and equal to the number of waveguide design areas on the wafer, and the waveguide design areas are distributed in each chip design area; and the multiple design polarization periods are configured one-to-one in each waveguide design area.

[0006] Optionally, parameter scanning within the deviation range can be performed to obtain multiple design polarization periods, including: Obtain the number of chip design areas; The scan step size is determined as P / (M×N-1) based on the number of chip design areas and the deviation interval, where N is the number of chip design areas, P is the width of the deviation interval, and M is a positive integer greater than 1. Based on the scanning step size, the parameters are scanned from one end of the deviation interval to the other end to obtain M×N design polarization periods.

[0007] Optionally, the number of waveguide design areas configured within each chip design area is M.

[0008] Optionally, the waveguide design areas on the chip are arranged linearly, and the value of the design polarization period corresponding to the waveguide design area is divided into multiple monotonic intervals along the direction of the linear arrangement. The monotonic transformation trend of each monotonic interval is the same, and there is no monotonic transformation between two adjacent monotonic intervals.

[0009] Optionally, the values ​​of the design polarization periods corresponding to the waveguide design areas follow a monotonic trend and form a numerical sequence. Within the same chip design area, the numerical sequences of the design polarization periods corresponding to adjacent waveguide design areas are spaced apart by N-1 design polarization periods, where N is the number of chip design areas.

[0010] Optionally, within different chip design regions, the numerical value of the design polarization period corresponding to the waveguide design region exhibits a consistent monotonic variation trend along the direction of linear arrangement.

[0011] Optionally, the waveguide design regions on the wafer are linearly arranged, and the value of the design polarization period corresponding to the waveguide design regions changes monotonically along the direction of the linear arrangement.

[0012] Optionally, obtaining the deviation range of the quasi-phase-matched polarization period includes: The refractive index range is determined based on the range of process errors in wafer fabrication; and the deviation range of the quasi-phase-matched polarization period is determined based on the refractive index range.

[0013] Another aspect of this application provides a method for fabricating a waveguide chip, the method comprising: The waveguide chip layout information is obtained. The waveguide chip layout information includes N chip design areas on the wafer and M waveguide design areas configured in each chip design area. The M×N waveguide design areas are arranged linearly. The design polarization periods corresponding to the M×N waveguide design areas are different from each other, and the corresponding design polarization period values ​​are arranged in a numerical sequence according to a monotonic changing trend. Among them, within the same chip design area, the design polarization period values ​​of adjacent waveguide design areas are separated by N-1 design polarization periods in the numerical sequence. Waveguides are fabricated in each waveguide design area of ​​the wafer based on the waveguide chip layout information to obtain the waveguide chip.

[0014] In another aspect of the embodiments of this application, a waveguide chip testing method is provided, the method comprising: A waveguide chip is obtained. The waveguide chip has N chip design areas, and each chip design area has M waveguides. The M×N waveguides are linearly arranged, and the design polarization periods corresponding to the M×N waveguides are different from each other. The corresponding design polarization period values ​​are arranged in a numerical sequence according to a monotonic change trend. Within the same chip design area, the design polarization period values ​​of adjacent waveguides are separated by N-1 design polarization periods in the numerical sequence. Within different chip design areas, the monotonic change trend of the design polarization period values ​​of the waveguides is consistent along the direction of the linear arrangement. Select the target chip design area from N chip design areas. The value of the design polarization period corresponding to the waveguide in the target chip design area includes the median or lower median of the numerical sequence. The target waveguide in the target chip design area is determined based on nonlinear efficiency testing. The target waveguide is the waveguide with the highest nonlinear efficiency in the target chip design area. Based on the ranking of the target waveguide in the target chip design area, nonlinear efficiency tests are performed on the candidate waveguides in the remaining chip design area.

[0015] The beneficial effects of this application include: This application provides a method for waveguide chip layout, fabrication, and testing. In this application, a wafer is used to fabricate the waveguide chip. Therefore, during the layout stage, several chip design regions exist on the wafer, and each chip design region contains a waveguide design region. The design polarization period corresponding to the waveguide design region comes from the deviation range of the QPM polarization period. The QPM polarization period has a certain deviation range due to the process error in wafer fabrication. By performing parameter scanning on the deviation range, a design polarization period with a greater number than the chip design regions is determined, and these are configured in a one-to-one correspondence in each waveguide design region. This results in a greater number of waveguide design regions than chip design regions, increasing the number of waveguide design regions configured within at least some chip design regions. The denser waveguide design region layout allows for smaller step sizes during parameter scanning, enabling more precise coverage of the process error range and increasing the number of waveguides meeting the QPM conditions. This, in turn, helps increase the number of QPM-compliant sub-chips produced from the wafer, effectively solving the problems of reduced waveguide nonlinear efficiency, decreased output power, and lower yield caused by the QPM polarization period deviating from the design value. Attached Figure Description To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1A schematic flowchart illustrating a waveguide chip layout method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a waveguide chip layout method provided in an embodiment of this application; Figure 3 for Figure 2 A schematic diagram showing the monotonic variation of the design polarization period along the linear arrangement direction in the middle waveguide design area; Figure 4 A schematic diagram of another waveguide chip layout method provided in this application embodiment; Figure 5 for Figure 4 A schematic diagram showing the monotonic variation of the design polarization period along the linear arrangement direction in the middle waveguide design area; Figure 6 This is a schematic diagram of the structure of a waveguide chip provided in an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] Waveguide chips are fabricated from wafers. During the layout stage, several chip design regions typically exist on the wafer, and waveguide design regions exist within these chip design regions. For PPLN waveguide chips, when performing nonlinear optical applications based on PPLN waveguides, their domain periods must be designed to satisfy the quasi-phase-matched QPM condition, which can be mathematically expressed as: In the formula, Λ represents the polarization period. , and These represent the wave vectors of the pump light, signal light, and idler light, respectively. The wave vector of each light wave is related to the effective refractive index of its respective waveguide mode, and the magnitude of the effective refractive index is affected by various factors such as film thickness, ridge etching depth, and sidewall tilt angle. This leads to a situation where, due to process errors, the polarization period required to satisfy QPM often deviates from the design value during actual fabrication. Consequently, the final waveguide does not meet the QPM condition, resulting in reduced nonlinear efficiency and decreased output power.

[0019] To address the aforementioned issues, a parameter scan of the wafer is typically performed. This involves first assessing the range of process errors, then calculating the corresponding QPM period deviation range based on the error range, and finally performing a parameter scan on the polarization period within this range. In this way, even if the final waveguide QPM period deviates from the design value due to process errors, there will always be a few waveguides that meet the QPM conditions within the scan range.

[0020] However, the above methods have limitations: after the PPLN waveguide chip is fabricated, the waveguides that meet the QPM conditions usually need to be diced into small pieces and packaged into components. During the packaging process, chips that are too small will have a series of problems such as poor reliability and difficulty in clamping. Therefore, there is a minimum size requirement for packaged chips. This requires that the spacing between adjacent waveguides in the chip layout usually need to be set very large to meet the packaging size requirements. As a result, the number of waveguides that can be placed on the same chip is very limited. In addition, since parameter scanning is required, often only one or two PPLN waveguides that meet the QPM conditions can be produced from a single chip, which seriously limits the industrial yield of PPLN waveguide components.

[0021] Based on this, the inventors of this application propose to determine a design polarization period that is more numerous than the chip design area by performing parameter scanning on the deviation range, and to configure them in a one-to-one correspondence in each waveguide design area. This results in a greater number of waveguide design areas than chip design areas, increasing the number of waveguide design areas configured within at least a portion of the chip design areas. The denser waveguide design area layout allows for smaller step sizes during parameter scanning, enabling more precise coverage of the process error range and increasing the number of waveguides that meet the QPM condition. This, in turn, helps to increase the number of QPM-compliant sub-chips produced from the wafer, effectively solving the problems of reduced waveguide nonlinear efficiency, decreased output power, and lower yield caused by the deviation of the QPM polarization period from the design value.

[0022] Based on the above concept, this application proposes a waveguide chip layout method, fabrication method, and testing method. It should be understood that the layout, fabrication, and testing stages constitute the entire process of a waveguide chip from design to product. In the layout stage, the structure and function of each region in the wafer are rationally arranged through layout design. In the fabrication stage, based on the determined layout design, a waveguide chip with an actual structure is manufactured on the wafer using various processes such as photolithography, etching, and polarization (this process inevitably introduces process errors caused by uncontrollable factors such as thin film thickness, ridge etching depth, and sidewall tilt angle). In the testing stage, by testing the relevant indicators of the waveguide chip, waveguides that meet the conditions, such as those meeting the quasi-phase matching (QPM) condition, are selected from numerous waveguides. Then, the chip design area containing the qualified waveguide is used as the smallest cutting unit to cut and obtain qualified sub-chips.

[0023] The following section will describe the layout, fabrication, and testing methods of waveguide chips with reference to the accompanying drawings.

[0024] Figure 1 This is a flowchart illustrating a waveguide chip layout method provided in an embodiment of this application. Figure 2 This is a schematic diagram of a waveguide chip layout method provided in an embodiment of this application. Figure 2 This diagram shows the wafer at the layout stage and the chip design area 110 on the wafer. Different chip design areas 110 can be connected via... Figure 2 The dashed lines in the diagram separate the waveguide design area 111 within the chip design area 110. The wafer can be made of materials such as lithium niobate thin film, lithium tantalate thin film, or barium titanate thin film. For ease of understanding, lithium niobate thin film will be used as an example in the following description.

[0025] See Figure 1 , Figure 1 The waveguide chip layout method shown in the figure includes: S11: Obtain the deviation range of the QPM polarization period, which corresponds to the process error range of the wafer fabrication chip.

[0026] S12: Perform parameter scanning within the deviation range to obtain multiple design polarization periods. The number of design polarization periods is greater than the number of chip design areas on the wafer and equal to the number of waveguide design areas on the wafer. The waveguide design areas are distributed among the various chip design areas. S13: Arrange the multiple design polarization periods one-to-one with each waveguide design area.

[0027] During the layout stage, the layout design needs to be based on the wafer used to fabricate the waveguide chip. Therefore, it is necessary to know the relevant parameters of the wafer (which can be obtained by receiving information sent by other entities or by calling from a pre-entered database). The parameters include, but are not limited to, material, thickness, and size.

[0028] Once the wafer parameters are determined, chip design regions 110 and waveguide design regions 111 can be designed on the wafer according to relevant requirements. Chip design region 110 is the smallest unit cut in the final fabrication stage, and waveguide design region 111 is the area on the wafer containing the actual waveguide structure after the fabrication stage. Typically, waveguide design regions 111 are located within chip design regions 110; for example, at least one waveguide design region 111 is planned and configured within a single chip design region 110. The number of chip design regions 110 and waveguide design regions 111 can be reasonably selected according to requirements and process limitations. In the embodiments of this application, the number of waveguide design regions 111 is greater than the number of chip design regions 110. This ensures that at least some chip design regions 110 contain two or more waveguide design regions 111, resulting in a denser concentration of waveguide design regions 111 within each chip design region 110, which helps increase the probability of meeting QPM conditions.

[0029] Each waveguide design region needs to be configured with its corresponding design polarization period. The process of configuring the design polarization period within a waveguide design region is described below.

[0030] The quasi-phase-matched QPM polarization period is the design value. Due to uncontrollable errors introduced by the chip fabrication process (process errors are random, so they can be ranged), the actual value after chip fabrication deviates from this design value. To address this deviation, the QPM polarization period is ranged during the layout stage, i.e., designed as a deviation range, to encompass as many polarization periods as possible that still meet the QPM conditions despite the influence of process errors. The deviation range corresponds to the range of process errors in chip fabrication; for example, the deviation range is set to exactly cover the range of design value deviations caused by process errors. This avoids the deviation range being too large or too small, ensuring the accuracy and rationality of the deviation range design, so as to plan more waveguide design areas that meet the QPM conditions within the limited area of ​​the wafer. In other optional embodiments, when the impact of process errors on the deviation of the design value is relatively small, the deviation range can be further widened beyond just covering the range of design value deviations caused by process errors to ensure compatibility with process errors.

[0031] Once the deviation range is determined, multiple design polarization periods are selected within the deviation range using the polarization period as a parameter through parameter scanning. Each design polarization period is represented numerically. The number of design polarization periods selected from the deviation range should be the same as the number of waveguide design regions, i.e., greater than the number of chip design regions. Then, a corresponding design polarization period is configured for each waveguide design region. The design polarization periods configured for different waveguide design regions are different, in order to maximize the occurrence of diverse design polarization periods.

[0032] In some alternative implementations, obtaining the deviation range of the QPM polarization period includes: S111: Determine the corresponding refractive index range based on the value of the process error range for wafer fabrication of chips.

[0033] S112: Determine the deviation range of the QPM polarization period based on the refractive index range.

[0034] Random errors exist during wafer fabrication, making it difficult to directly determine the specific value of these errors; a range is required. This range can be set empirically, for example, by monitoring the fluctuation range of process errors in wafer fabrication. The error fluctuation is then substituted into simulation calculations to obtain the refractive index error range corresponding to the process error range, and then... (where Λ is the polarization period,) , and The QPM polarization period deviation range is calculated using the wave vectors representing the pump light, signal light, and idler light, respectively. This process error range can also be based on statistical values ​​or historical values.

[0035] In some alternative implementations, performing a parameter scan within the deviation range to obtain multiple design polarization periods may include the following steps: S121: Obtain the number of chip design areas on the wafer.

[0036] S122: Determine the scan step size as P / (M×N-1) based on the number of chip design areas and the deviation interval, where N is the number of chip design areas, P is the width of the deviation interval, and M is a positive integer greater than 1. S123: Based on the scanning step size, perform parameter scanning from one end of the deviation interval to the other end to obtain M×N design polarization periods.

[0037] The chip design area that can be set on a wafer is limited. Besides the finite size of the wafer itself, process limitations in fabrication and subsequent packaging must also be considered. For example, after fabricating the actual structure of waveguide 112 on the wafer to obtain the waveguide chip, the waveguide chip needs to be cut into several sub-chips along the dotted lines between adjacent chip design areas 110, using the chip design area 110 as the smallest unit. These sub-chips are then packaged to form a packaged chip. Sub-chips that are too small during packaging are prone to problems such as poor reliability and difficulty in clamping. Therefore, there is a minimum size requirement for the sub-chips, which also means that the chip design area has a minimum size requirement.

[0038] Taking into account the above limitations, the number of on-chip design areas can be preset according to requirements. This allows the number of on-chip design areas to be obtained by retrieving a preset value. Of course, in other alternative implementations, the number of on-chip design areas can also be an input value, such as a user-inputted number.

[0039] Once the number of chip design regions on the wafer is obtained, the scan step size for parameter scanning can be determined by the number of chip design regions and the offset interval. For example, if the width of the offset interval is represented by P, and the number of chip design regions 110 on the wafer is represented by N, then the scan step size satisfies: P / (M×N-1). M×N can be represented by the number of waveguide design regions 111 on the wafer, or by the number of design polarization periods obtained from the offset interval. M is a positive integer greater than 1.

[0040] The deviation interval is a numerical interval in a mathematical sense. Therefore, starting from one end of the deviation interval (such as the endpoint value of the interval), a value is selected as the design polarization period every time the scan step is repeated, until the other end of the deviation interval is reached, thus obtaining M×N design polarization periods.

[0041] For example Figure 2 This shows N chip design areas, numbered from top to bottom as chip design area 1101, chip design area 1102, up to chip design area 110N. Figure 2 In the diagram, different chip design areas are separated by dashed lines, and only one chip design area with the reference numeral "110" is shown. If the deviation interval is [pt, p+t], then the width of the deviation interval P=2t, from which the scan step size can be obtained as 2t / (M×N-1). Based on this, the parameters of the deviation interval are scanned. Starting with pt, pt is a value of one design polarization period. Every 2t / (M×N-1) is the value of the next design polarization period. M×N design polarization periods can be obtained from the deviation interval in sequence, where M=3. If the scanned design polarization periods are numbered, they are design polarization period 1, design polarization period 2, up to design polarization period M×N from top to bottom. This also means that there will be M×N waveguide design areas to be configured one-to-one with the M×N design polarization periods.

[0042] Based on the above description, it can be seen that the waveguide design area is located within the chip design area. Therefore, the distribution relationship between the waveguide design area and the chip design area can be described in the following two ways: Method 1 Waveguide design areas on a chip are not uniformly distributed across various chip design areas. For example, the number of waveguide design areas configured in some chip design areas may differ from the number configured in others.

[0043] Method 2 The waveguide design regions on the chip are evenly distributed within each chip design region. For example, if the total number of waveguide design regions 111 is M×N, and the total number of chip design regions is N, then the number of waveguide design regions configured within each chip design region is M. This maximizes the utilization of the chip design region area, increases the number of waveguide design regions, and is beneficial for increasing the number of waveguide design regions that meet the QPM (Quality, Performance, and Maintenance) criteria.

[0044] In some alternative implementations, such as Figure 2 or Figure 4 As shown, the chip design area 110 on the wafer is linearly arranged, and the waveguide design area 111 on the wafer is linearly arranged.

[0045] When the waveguide design regions 111 are arranged linearly, the numerical sorting of the design polarization periods corresponding to the waveguide design regions 111 can be done in two ways: Method 1 Please refer to Figure 2The N chip design areas 110 are ordered by number: chip design area 1101 to chip design area 110N. The M×N design polarization periods obtained from the deviation interval are ordered by number: design polarization period 1 to design polarization period M×N, where M=3. The numerical order of the design polarization periods is consistent with the numerical order, that is, the numerical value of design polarization period 1 is the smallest, and the numerical value of design polarization period M×N is the largest.

[0046] Each chip design area is configured with the same number of waveguide design areas. Therefore, each chip design area is configured with waveguide design areas with 3 design polarization periods. The design polarization periods corresponding to different waveguide design areas are numbered differently. The linear arrangement of waveguide design areas is set sequentially according to the number of their configured design polarization periods.

[0047] The values ​​of the design polarization periods 1 to M×N vary monotonically along the direction of the linear arrangement of the waveguide design region. Figure 3 Taking the design polarization periods 1 to 5 shown in the diagram as examples, the vertical axis represents the numerical value of the design polarization period. Figure 3 As can be seen, the values ​​of the design polarization periods 1 to 5 increase monotonically.

[0048] In this way, the number of waveguide design areas configured in each chip design area is 3. The denser waveguide design area layout allows for a smaller step size during parameter scanning, which can more precisely cover the process error range, thereby increasing the absolute number of waveguides that meet the QPM condition. Therefore, it can also increase the number of sub-chips that meet the QPM condition, effectively solving the problems of reduced nonlinear efficiency, decreased output power, and low yield of the produced waveguide chips caused by the deviation of the QPM polarization period from the design value.

[0049] However, the limitation of this layout is that in micro- and nano-fabrication, the process errors of the same chip design area are relatively similar. This results in the design polarization period corresponding to the waveguide design area that meets the QPM condition generally being a continuous sub-interval of the deviation interval. Therefore, the distribution of waveguide design areas that meet the QPM condition on the layout is usually a group of adjacent waveguide design areas. For example Figure 2As shown, waveguide design regions with polarization periods of 3 to 8, after fabrication and testing, all met the QPM (Quality, Performance, and Maintenance) requirements, while the rest did not. Based on the layout, these waveguide design regions are distributed across chip design regions 1101 to 1103, with chip design regions 1102 and 1103 containing more than one waveguide design region that ultimately meets the QPM requirements. This means that multiple waveguide design regions meeting the QPM requirements may exist within the same chip design region. However, after final fabrication and packaging, although the number of qualified waveguides increases significantly, the number of sub-chips with qualified waveguides only increases slightly, because a sub-chip contains more than one qualified waveguide. Therefore, the number of sub-chips with qualified waveguides can be optimized and increased through the following method two.

[0050] Method 2 Please refer to Figure 4 The N chip design areas 110 are ordered by number: chip design area 1101 to chip design area 110N. The M×N design polarization periods obtained from the deviation interval are ordered by number: design polarization period 1 to design polarization period M×N, where M=3. The numerical order of the design polarization periods is consistent with the numerical order, that is, the numerical value of design polarization period 1 is the smallest, and the numerical value of design polarization period M×N is the largest.

[0051] The numbering order of chip design areas 1101 to 110N can remain unchanged. The linear arrangement of waveguide design areas is no longer set sequentially according to the numbering order of their configured design polarization periods, but rather in a staggered arrangement. For example, the numbering order of the design polarization periods configured in two adjacent waveguide design areas is not continuous; that is, there are several design polarization period numbers between the numbers of the design polarization periods configured in two adjacent waveguide design areas. In this way, the values ​​of the design polarization periods corresponding to the waveguide design areas are divided into multiple monotonic intervals along the direction of the linear arrangement. The monotonic transformation trend of each monotonic interval is the same, and there is no monotonic transformation between two adjacent monotonic intervals. This ensures that the waveguides of the waveguide design areas that ultimately meet the QPM conditions are distributed as much as possible in different chip design areas, thereby increasing the number of sub-chips with qualified waveguides.

[0052] Specifically, for example Figure 4 As shown, if the design polarization period values ​​form a numerical sequence with a monotonically increasing trend (or monotonically decreasing in other examples), the numerical sequence is: the value of design polarization period 1, the value of design polarization period 2, and so on up to the value of design polarization period M×N.

[0053] Each chip design area is configured with 3 waveguide design areas, for example Figure 4In the chip design area 1101, three waveguide design areas with design polarization periods of 1, N+1, and 2N+1 are configured. In the chip design area 1102, three waveguide design areas with design polarization periods of 2, N+2, and 2N+2 are configured, and so on, until the chip design area 110N is configured with three waveguide design areas with design polarization periods of N, 2N, and 3N. Therefore, within the same chip design area, the design polarization period values ​​of adjacent waveguide design areas will be separated by N-1 design polarization period values ​​in the numerical sequence. For example, in chip design area 1101: two adjacent waveguide design areas with design polarization period 1 and design polarization period N+1, when their design polarization periods 1 and N+1 are returned to the numerical sequence, are separated by a gap from design polarization period 2 to design polarization period N, totaling N-1 values. Similarly, two adjacent waveguide design areas with design polarization periods N+1 and 2N+1, when their design polarization periods N+1 and 2N+1 are returned to the numerical sequence, are also separated by a gap of N-1 design polarization period values.

[0054] Therefore, the numerical value of the design polarization period corresponding to the waveguide design region has multiple monotonic intervals along the linear arrangement direction of the waveguide design region, and the monotonic transformation trend of each monotonic interval is the same, and there is no monotonic transformation between two adjacent monotonic intervals. Figure 5 Taking the design polarization periods 1, N+1, 2N+1, 2, N+2, and 2N+2 as examples, the vertical axis represents the numerical value of the design polarization period. Figure 5 As can be seen, the values ​​of design polarization periods 1, N+1 to 2N+1 form an increasing monotonic interval, and the values ​​of design polarization periods 2, N+2 to 2N+2 form the next increasing monotonic interval. Therefore, Figure 5 The diagram shows two monotonic intervals that are adjacent to each other. The values ​​of the design polarization period 2N+1 at the end of the previous monotonic interval and the design polarization period 2 at the beginning of the next monotonic interval do not continue the original monotonically increasing trend, but instead reverse and show a decreasing trend. Therefore, these two adjacent monotonic intervals do not exhibit a monotonic transformation.

[0055] This staggered distribution allows for a larger numerical interval between the design polarization periods of adjacent waveguide design areas, avoiding similar process errors and thus ensuring that waveguide design areas that ultimately meet QPM conditions are distributed across more chip design areas. For example... Figure 4As shown, waveguide design regions with polarization periods of 3 to 8 were finally fabricated into waveguides and tested to meet the QPM condition, while the others did not. According to the layout, the waveguide design regions with polarization periods of 3 to 8 were dispersed in chip design regions 1103 to 1108. After final fabrication and packaging, although the number of qualified waveguides remained the same, the number of sub-chips with qualified waveguides doubled from 3 to 6, with each sub-chip containing only one qualified waveguide.

[0056] Another aspect of this application provides a method for fabricating a waveguide chip, the method comprising: S14: Obtain waveguide chip layout information. The waveguide chip layout information includes N chip design areas on the wafer and M waveguide design areas configured within each chip design area. The M×N waveguide design areas are arranged linearly. The design polarization periods corresponding to the M×N waveguide design areas are all different, and the values ​​of the corresponding design polarization periods are arranged in a monotonic trend to form a numerical sequence. Among them, within the same chip design area, the values ​​of the design polarization periods corresponding to adjacent waveguide design areas are separated by N-1 design polarization periods in the numerical sequence.

[0057] S15: Based on the waveguide chip layout information, waveguides are fabricated in each waveguide design area of ​​the wafer to obtain the waveguide chip.

[0058] Waveguide chip layout information can be obtained using the aforementioned waveguide chip layout methods. Therefore, the waveguide chip layout information can be derived from a layout obtained using any of the aforementioned waveguide chip layout methods, for example, at least... Figure 2 or Figure 4 .by Figure 4 The layout information shown is an example: The waveguide chip layout information includes N chip design areas 110 on the wafer and M waveguide design areas 111 configured within each chip design area 110. The M×N waveguide design areas 111 are arranged linearly, and the design polarization periods corresponding to the M×N waveguide design areas 111 are all different. Furthermore, the values ​​of the design polarization periods corresponding to the M×N waveguide design areas 111 are arranged in a numerical sequence according to a monotonic variation trend. Within the same chip design area 110, the values ​​of the design polarization periods corresponding to adjacent waveguide design areas 111 are spaced apart by N-1 design polarization periods in the numerical sequence.

[0059] Then, based on the waveguide chip layout information, waveguides with actual structures are mass-produced on the wafer using various micro- and nano-processes such as photolithography, etching, and polarization within each waveguide design area, thus obtaining waveguide chips. For example... Figure 6As shown, waveguide 112 in the waveguide chip now has a practical structure. Three waveguides 112 are still distributed in each chip design area 110. The design polarization periods corresponding to the three waveguides 112 distributed in the chip design area 110 are design polarization periods 1, N+1, and 2N+1, respectively. Further details are omitted. It should be understood that the design polarization period corresponding to the waveguide at this point is not its actual polarization period, but only a theoretical value from the layout stage. The actual polarization period of the waveguide will deviate somewhat from its corresponding design polarization period after process errors during the fabrication stage.

[0060] In another aspect of this application, considering the high testing time cost when the number of waveguides is large, a waveguide chip testing method is provided to reduce testing time cost. The method includes: S16: Obtain the waveguide chip. The waveguide chip has N chip design areas, and each chip design area has M waveguides. The M×N waveguides are linearly arranged, and the design polarization periods corresponding to the M×N waveguides are different from each other. The values ​​of the corresponding design polarization periods are arranged in a monotonically changing trend to form a numerical sequence. Within the same chip design area, the values ​​of the design polarization periods corresponding to adjacent waveguides are separated by N-1 design polarization periods in the numerical sequence. Within different chip design areas, the values ​​of the design polarization periods corresponding to the waveguides have the same monotonically changing trend along the direction of the linear arrangement.

[0061] S17: Select the target chip design area from N chip design areas. The value of the design polarization period corresponding to waveguide 112 in the target chip design area includes the median or lower median of the numerical sequence.

[0062] S18: Determine the target waveguide in the target chip design area based on nonlinear efficiency testing. The target waveguide is the waveguide with the highest nonlinear efficiency in the target chip design area.

[0063] S19: Based on the ranking of the target waveguide in the target chip design area, perform nonlinear efficiency tests on the candidate waveguides in the remaining chip design area.

[0064] Figure 6 This is a schematic diagram of the structure of a waveguide chip provided in an embodiment of this application.

[0065] Reference Figure 6 , Figure 6 The waveguide chip shown has N chip design areas 110, linearly arranged from top to bottom and numbered as chip design area 1101, chip design area 1102, up to chip design area 110N. The waveguide chip also has M×N waveguides 112, linearly arranged from top to bottom, where M=3, and each chip design area contains 3 waveguides. For example... Figure 6In this embodiment, three waveguides 112 with design polarization periods of 1, N+1, and 2N+1 are configured in the chip design area 1101; three waveguides 112 with design polarization periods of 2, N+2, and 2N+2 are configured in the chip design area 1102; and so on, until three waveguides 112 with design polarization periods of N, 2N, and 3N are configured in the chip design area 110N. Figure 6 The diagram shows a waveguide, not a waveguide design region. A waveguide corresponds to a waveguide designed within the waveguide design region; the difference lies in... Figure 6 The waveguide in this context can be considered as a waveguide that has already been processed or fabricated, rather than a design parameter.

[0066] Within different chip design areas, the values ​​of the design polarization periods corresponding to waveguides exhibit a consistent monotonic variation trend along the linear arrangement direction. For example, the values ​​of the design polarization periods corresponding to waveguide 112 in chip design area 1101 increase sequentially from top to bottom, and the values ​​of the design polarization periods corresponding to waveguide 112 in chip design areas 1102 to 110N also increase sequentially from top to bottom.

[0067] During testing, the chip design area with the number closest to N / 2 can be selected from chip design areas 1101 to chip design area 110N as the target chip design area. For example, when N is even, chip design area 110N / 2 is selected as the target chip design area. The design polarization period corresponding to the waveguide 112 configured in the target chip design area should be numbered as N / 2, 3N / 2 and 5N / 2. When N is odd, chip design area 110N / 2-1 or chip design area 110N / 2+1 is selected as the target chip design area.

[0068] The waveguide 112 configured in the target chip design area should satisfy the following: the value of the design polarization period corresponding to the waveguide 112 should belong to the median or lower median of the numerical sequence. When the numerical sequence has an even number of elements, the lower median is the smaller of the two middle values ​​in the numerical sequence. When the numerical sequence has an odd number of elements, the median is the middle value in the numerical sequence.

[0069] After determining the target chip design area, perform nonlinear efficiency tests on all waveguides within that area, and define the waveguide with the highest nonlinear efficiency, i.e. the best test result, as the target waveguide.

[0070] If the target waveguide ranks first in the target chip design area, then waveguide 112, which also ranks first in the remaining chip design areas 110, is selected as a candidate waveguide for nonlinear efficiency testing. The nonlinear efficiency test result of the candidate waveguide is used as the final result to determine whether its chip design area 110 meets the QPM condition. This reduces the testing time by two-thirds, thereby improving testing efficiency.

[0071] In rare cases, the waveguide 112 with the highest nonlinear efficiency is located in the chip design area 110 at the head or tail. In such cases, additional testing is required on several other waveguides with a period closer to that of the waveguide with the highest nonlinear efficiency.

[0072] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0073] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0074] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0075] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0076] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A waveguide chip layout method, characterized in that, The method includes: Obtain the deviation range of the quasi-phase-matched polarization period, the deviation range corresponding to the process error range of the wafer fabrication chip; Parameter scanning is performed within the deviation range to obtain multiple design polarization periods. The number of these multiple design polarization periods is greater than the number of chip design regions on the wafer and equal to the number of waveguide design regions on the wafer. The waveguide design regions are distributed among the various chip design regions. The plurality of design polarization periods are configured one-to-one in each of the waveguide design regions; The waveguide design areas on the wafer are arranged linearly, and the value of the design polarization period corresponding to the waveguide design area is divided into multiple monotonic intervals along the direction of the linear arrangement. The monotonic transformation trend of each monotonic interval is the same, and there is no monotonic transformation between two adjacent monotonic intervals. The values ​​of the design polarization periods corresponding to the waveguide design areas follow a monotonic trend and form a numerical sequence. Within the same chip design area, the values ​​of the design polarization periods corresponding to adjacent waveguide design areas are spaced N-1 design polarization periods apart in the numerical sequence, where N is the number of chip design areas and N is an integer greater than or equal to 2.

2. The waveguide chip layout method as described in claim 1, characterized in that, The step of performing a parameter scan within the deviation range to obtain multiple design polarization periods includes: Obtain the number of the chip design areas; The scan step size is determined as P / (M × N-1) based on the number of chip design areas and the deviation interval, where P is the width of the deviation interval and M is a positive integer greater than 1. Based on the scan step size, parameter scanning is performed from one end of the deviation interval to the other end to obtain M×N design polarization periods.

3. The waveguide chip layout method as described in claim 2, characterized in that, The number of waveguide design areas configured within each of the chip design areas is M.

4. The waveguide chip layout method according to any one of claims 1 to 3, characterized in that, Within different chip design regions, the numerical value of the design polarization period corresponding to the waveguide design region exhibits a consistent monotonic variation trend along the direction of the linear arrangement.

5. The waveguide chip layout method according to any one of claims 1 to 3, characterized in that, The deviation range for obtaining the quasi-phase-matched polarization period includes: The corresponding refractive index range is determined based on the value of the process error range in the wafer fabrication process; and The deviation range of the quasi-phase-matched polarization period is determined based on the refractive index range.

6. A method for fabricating a waveguide chip, characterized in that, The method includes: The waveguide chip layout information is obtained, which includes N chip design areas on the wafer and M waveguide design areas configured in each chip design area. The M×N waveguide design areas are linearly arranged, and the design polarization periods corresponding to the M×N waveguide design areas are all different. The values ​​of the corresponding design polarization periods are arranged in a monotonic trend to form a numerical sequence. In the same chip design area, the values ​​of the design polarization periods corresponding to adjacent waveguide design areas are separated by N-1 design polarization periods in the numerical sequence. N is the number of chip design areas and N is an integer greater than or equal to 2. Waveguides are fabricated in each waveguide design region of the wafer according to the waveguide chip layout information to obtain a waveguide chip; The design polarization period corresponding to the waveguide design area is divided into multiple monotonic intervals along the direction of the linear arrangement. Each monotonic interval has the same monotonic transformation trend, and there is no monotonic transformation between two adjacent monotonic intervals.

7. A waveguide chip testing method, characterized in that, The method includes: A waveguide chip is obtained, wherein the waveguide chip has N chip design areas, each chip design area has M waveguides, the M×N waveguides are linearly arranged, the design polarization periods corresponding to the M×N waveguides are all different, and the values ​​of the corresponding design polarization periods are arranged in a monotonic trend to form a numerical sequence. In the same chip design area, the values ​​of the design polarization periods corresponding to adjacent waveguides are spaced apart by N-1 design polarization periods in the numerical sequence. In different chip design areas, the values ​​of the design polarization periods corresponding to the waveguides have the same monotonic trend along the direction of the linear arrangement. N is the number of chip design areas, and N is an integer greater than or equal to 2. Select a target chip design area from N chip design areas, wherein the value of the design polarization period corresponding to the waveguide in the target chip design area includes the median or lower median of the numerical sequence; The target waveguide in the target chip design area is determined based on nonlinear efficiency testing, and the target waveguide is the waveguide with the highest nonlinear efficiency in the target chip design area. Based on the arrangement of the target waveguide in the target chip design area, nonlinear efficiency tests are performed on the remaining candidate waveguides in the chip design area. The design polarization period corresponding to the waveguide design area is divided into multiple monotonic intervals along the direction of the linear arrangement. Each monotonic interval has the same monotonic transformation trend, and there is no monotonic transformation between two adjacent monotonic intervals.

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