Chip automated integration method, device, computer equipment, readable storage medium and program product

Abstract

The present disclosure provides a chip automation integration method, device, computer equipment, readable storage medium and program product, relates to the technical field of integrated circuit design, and the implementation scheme is: a parent circuit module is constructed, a parent circuit module interface of the parent circuit module includes a first port and has a first parameter; a sub-circuit module is constructed, a sub-circuit module interface of the sub-circuit module includes a second port and has a second parameter; based on a preset connection legality verification rule, the first parameter and the second parameter, the connection legality verification of the sub-circuit module interface and the parent circuit module interface is performed; in response to the fact that the connection legality verification is passed, the connection relationship between the sub-circuit module interface and the parent circuit module interface is established; based on the first parameter, the second parameter and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, integrated code is generated; and based on the integrated code, the chip is automatically integrated, which can improve the efficiency and accuracy of chip integration and reduce the integration and maintenance cost.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, particularly to chip design, system-on-a-chip integration, and especially to an automated chip integration method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] With the rapid development of electronic information technology, the integration level and functional density of integrated circuits are increasing day by day. Complex systems often require the collaborative integration of multiple modules and components to achieve complete applications. In the design flow of large-scale integrated circuits, the interconnection and integration of various functional modules is a critical link, directly affecting the design cycle and system reliability. Traditional module integration methods are mainly manual, relying on designers to manually complete signal matching, logic interconnection, and code writing according to interface rules. When the number of modules increases and the interface types become more diversified, the overall process becomes lengthy and prone to problems such as signal mismatch and logic association errors, increasing debugging and repair costs. At the same time, although some existing auxiliary design tools have simplified the operation to a certain extent, they generally have limitations such as limited adaptability, high learning costs, and insufficient integration with the existing design environment. It is difficult to ensure integration efficiency, design accuracy, and ease of maintenance in complex scenarios. The industry generally expects integration methods that are more suitable for actual engineering needs. Summary of the Invention

[0003] This disclosure provides a method, apparatus, computer device, computer-readable storage medium, and computer program product for automated chip integration.

[0004] According to one aspect of this disclosure, a method for automated chip integration is provided, comprising: constructing a parent circuit module, the parent circuit module being used to accommodate an instantiated circuit module, the parent circuit module having a parent circuit module interface, the parent circuit module interface including at least one first port, the parent circuit module interface having a corresponding first parameter, the first parameter being used to characterize the attributes of the parent circuit module interface and the at least one first port; constructing a child circuit module, the child circuit module being used to characterize the circuit module instantiated in the parent circuit module, the child circuit module having a child circuit module interface for interacting with the parent circuit module via circuit signals, the child circuit module interface including at least one second port, the child circuit module interface having a corresponding second parameter, the second parameter being used to characterize the attributes of the parent circuit module interface and the at least one first port; and constructing a child circuit module, the child circuit module being used to characterize the instantiated circuit module in the parent circuit module, the child circuit module having a child circuit module interface for interacting with the parent circuit module via circuit signals, the child circuit module interface including at least one second port, the child circuit module interface having a corresponding second parameter, the second parameter being used to characterize the attributes of the parent circuit module interface and the at least one first port. The system identifies the attributes of the sub-circuit module interface and at least one second port; performs connection validity verification on the sub-circuit module interface and the parent circuit module interface based on preset connection validity verification rules, a first parameter, and a second parameter. The connection validity verification is used to determine whether a connection can be successfully established between the sub-circuit module interface and the parent circuit module interface; in response to the successful connection validity verification, establishes the connection relationship between the sub-circuit module interface and the parent circuit module interface; generates integration code based on the first parameter, the second parameter, and the established connection relationship between the sub-circuit module interface and the parent circuit module interface. The integration code is used to characterize the signal interaction and parameter configuration between the circuit modules of the chip to be integrated; and automatically integrates the chip based on the integration code.

[0005] In some embodiments, the parent circuit module interface includes an external interface and internal wiring. The external interface is used to connect the parent circuit module to the child circuit module instantiated in the parent circuit module, and the internal wiring is used to connect the child circuit module instantiated in the parent circuit module.

[0006] In some embodiments, the first parameter includes the name of the parent circuit module interface and a first port list, the first port list including the name, bit width, signal transmission type, signal source, and signal destination of at least one first port; the second parameter includes the name of the child circuit module interface and a second port list, the second port list including the name, bit width, signal transmission type, signal source, and signal destination of at least one second port, the signal transmission type including input type, output type, and connection line type.

[0007] In some embodiments, based on preset connection validity verification rules, a first parameter, and a second parameter, connection validity verification is performed on the sub-circuit module interface and the parent circuit module interface, including: determining the parent circuit module interface and the sub-circuit module interface to be connected as a first interface to be connected and a second interface to be connected, respectively; performing connection validity verification one by one on each group of ports to be connected in the first interface to be connected and the second interface to be connected, wherein each group of ports to be connected includes a third port and a fourth port, wherein the third port is located in either the first interface to be connected or the second interface to be connected, and the fourth port is located in the other; and determining that the connection validity verification of the first interface to be connected and the second interface to be connected has passed in response to each group of ports to be connected passing the connection validity verification.

[0008] In some embodiments, for each group of ports to be connected in the first and second interfaces to be connected, connection validity checks are performed one by one, including: in response to the signal transmission type of the third port being an output type, determining whether the signal transmission type of the fourth port is an input type; in response to the signal transmission type of the fourth port not being an input type, determining whether the signal source of the third port is empty; in response to the signal source of the third port being empty, determining that the connection validity check has passed.

[0009] In some embodiments, for each group of ports to be connected in the first interface to be connected and the second interface to be connected, the connection validity check is performed one by one, and the method further includes: in response to the signal transmission type of the third port being an input type and the signal source of the third port being not empty, the connection validity check is determined to be passed.

[0010] In some embodiments, for each group of ports to be connected in the first and second interfaces to be connected, a connection validity check is performed one by one, which further includes: in response to the signal transmission type of the third port being a connection line type and the signal source of either the third port or the fourth port being empty, while the signal source of the other port is not empty, or in response to the signal transmission type of the third port being a connection line type, the signal transmission type of the fourth port being an input type, and the signal source of the fourth port being empty, the connection validity check is determined to be passed.

[0011] In some embodiments, based on the first parameter, the second parameter, and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, the integration code is generated, including: based on the first parameter, generating interface definition code and parameter definition code to describe the parent circuit module interface, wherein the interface definition code is used to declare the hardware description of the parent circuit module interface, and the parameter definition code is used to declare the first parameter; traversing the sub-circuit modules, based on the second parameter and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, generating module instantiation code and parameter mapping code for the sub-circuit module within the parent circuit module, wherein the module instantiation code is used to declare the hardware description of the sub-circuit module interface, and the parameter mapping code is used to declare the mapping relationship between the sub-circuit module interface with the established connection relationship and the corresponding first and second parameters of the parent circuit module interface, and the integration code includes interface definition code, parameter definition code, module instantiation code, and parameter mapping code.

[0012] According to another aspect of this disclosure, a chip automated integration apparatus is provided, comprising: a parent circuit module construction unit configured to construct a parent circuit module, the parent circuit module being used to accommodate an instantiated circuit module, the parent circuit module having a parent circuit module interface, the parent circuit module interface including at least one first port, the parent circuit module interface having a corresponding first parameter, the first parameter being used to characterize the attributes of the parent circuit module interface and the at least one first port; and a child circuit module construction unit configured to construct a child circuit module, the child circuit module being used to characterize a circuit module instantiated in the parent circuit module, the child circuit module having a child circuit module interface for interacting with the parent circuit module via circuit signals, the child circuit module interface including at least one second port, the child circuit module interface having a corresponding second parameter, the second parameter being used to characterize the attributes of the child circuit module interface and the at least one first port. The system includes: an attribute of at least one second port; a validity verification unit configured to perform connection validity verification on the sub-circuit module interface and the parent circuit module interface based on preset connection validity verification rules, a first parameter, and a second parameter, the connection validity verification being used to determine whether a connection can be successfully established between the sub-circuit module interface and the parent circuit module interface; a connection relationship establishment unit configured to establish a connection relationship between the sub-circuit module interface and the parent circuit module interface in response to the successful connection validity verification; an integration code generation unit configured to generate integration code based on the first parameter, the second parameter, and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, the integration code being used to characterize the signal interaction and parameter configuration between the circuit modules of the chip to be integrated; and an integration unit configured to automatically integrate the chip based on the integration code.

[0013] According to another aspect of this disclosure, a computer device is provided, comprising: a processor; and a memory having a computer program stored thereon, wherein when executed by the processor, the computer program causes the processor to perform the methods provided above in this disclosure.

[0014] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0015] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0016] According to one or more embodiments of this disclosure, the efficiency and accuracy of chip integration can be significantly improved, integration and maintenance costs can be reduced, and the readability and maintainability of the generated code can be ensured.

[0017] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0018] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0019] Figure 1 This is a flowchart illustrating a chip automated integration method according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram illustrating the internal structure of the parent circuit module according to an embodiment of the present disclosure; Figure 3 This is a schematic diagram illustrating chip integration code according to an embodiment of the present disclosure; Figure 4 This is a block diagram illustrating a chip automated integration apparatus according to an embodiment of the present disclosure; Figure 5 An example computer device is shown in which any of the embodiments described herein may be implemented. Detailed Implementation

[0020] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0021] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0022] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0023] In the semiconductor chip design field, System-on-Chip (SoC) integration has become the mainstream approach for implementing complex circuits. Such systems typically require the integration of numerous register-transfer-level (RTL) circuit modules (IP cores) from different design units to achieve complete functionality. As chip size and system complexity continue to increase, the number of IP cores and interface types are constantly growing. Traditional chip integration mainly relies on manual signal matching, logic connections, and code writing. Designers must meticulously verify the interface protocols, signal widths, clock and reset rules of each module, and manually write interconnect logic and top-level code. This process is cumbersome and prone to human error, leading to interface mismatches, timing anomalies, and other issues, resulting in lengthy verification and repair cycles. Furthermore, when IP cores are upgraded or the system architecture is adjusted, a large amount of interconnect code needs to be modified, resulting in high maintenance costs and low iteration efficiency. While some existing High-Level Synthesis (HLS) tools or domain-specific languages ​​(such as Chisel) attempt to improve the integration abstraction level, they suffer from high learning costs, poor readability and compatibility of generated code, and difficulty in meeting the demands of large-scale chip integration for efficiency, reliability, and ease of use.

[0024] Therefore, embodiments of this disclosure provide an automated chip integration method that can significantly improve the efficiency and accuracy of chip integration, reduce integration and maintenance costs, and at the same time ensure the readability and maintainability of the generated code.

[0025] Figure 1 This is a flowchart illustrating a chip automated integration method according to an embodiment of the present disclosure.

[0026] like Figure 1 As shown, the automated chip integration method includes steps S101, S102, S103, S104, S105, and S106.

[0027] In step S101, a parent circuit module is constructed. The parent circuit module is used to accommodate the instantiated circuit module. The parent circuit module has a parent circuit module interface. The parent circuit module interface includes at least one first port and has a corresponding first parameter. The first parameter is used to characterize the attributes of the parent circuit module interface and at least one first port.

[0028] In the example, the parent circuit module can serve as a unified integration unit for instantiating and managing multiple sub-circuit modules. The parent circuit module interface acts as the channel for external interaction, enabling signal transmission between the parent circuit module and external / internal circuit modules. The first port can be the smallest unit within the parent circuit module interface responsible for signal transmission and reception; each first port handles signal transmission to ensure clear and independent signal interaction. The first parameter corresponding to the parent circuit module can be a standardized definition of the characteristics related to the parent circuit module interface and the first port. This clarifies attributes and prevents connection errors caused by unclear attributes. For example, in system-on-a-chip integration, the parent circuit module can serve as a top-level module. Its interface and first port, with their attributes clearly defined through the first parameter, can stably connect external input / output units and various internal IP cores, ensuring an orderly integration process.

[0029] In step S102, a sub-circuit module is constructed. The sub-circuit module is used to characterize the circuit module instantiated in the parent circuit module. The sub-circuit module has a sub-circuit module interface for interacting with the parent circuit module via circuit signals. The sub-circuit module interface includes at least one second port and has a corresponding second parameter. The second parameter is used to characterize the attributes of the sub-circuit module interface and the at least one second port.

[0030] In the example, a sub-circuit module can be a functional unit that relies on a parent circuit module for instantiation and assembly. Essentially, it is a circuit component in the chip integration architecture with independent functions that can be repeatedly called, specifically designed to implement specific circuit functions under the unified support of the parent circuit module. The sub-circuit module interface can be a dedicated channel for signal transmission and interaction between the sub-circuit module and the parent circuit module, used to establish an effective connection between the sub-module and the top-level module. The second port, as a component of the sub-circuit module interface, can be the smallest carrier for signal transmission, used to complete the transmission of specified signals such as input and output, ensuring the independence and accuracy of the interactive signals. The second parameter defines the attributes of the sub-circuit module interface and the second port, ensuring that the attributes are consistent when the sub-circuit module is connected to the parent circuit module. For example, in large-scale chip integration, various IP cores can be used as sub-circuit modules, and through the standardized settings of the interface, second port, and parameters, they can be instantiated and assembled in the top-level parent module.

[0031] In step S103, based on the preset connection validity verification rules, the first parameter, and the second parameter, a connection validity verification is performed on the sub-circuit module interface and the parent circuit module interface. The connection validity verification is used to determine whether a connection can be successfully established between the sub-circuit module interface and the parent circuit module interface.

[0032] In the example, connection validity verification is a crucial step in ensuring accurate interface connections and avoiding circuit logic errors during chip integration. It can be accomplished using pre-defined connection validity verification rules, the first parameter of the parent circuit module interface, and the second parameter of the child circuit module interface. The core of connection validity verification is to determine whether two types of interfaces can stably and compliantly establish a signal connection from an attribute matching perspective. The pre-defined connection validity verification rules can be judgment criteria formed by combining integrated circuit design specifications and signal transmission logic, used to clarify the allowed connection methods, signal flow constraints, and other requirements for interfaces or ports. The first and second parameters record the inherent attributes of the parent and child circuit module interfaces and their corresponding ports, providing an objective basis for verification and avoiding biases and omissions caused by manual judgment. During verification, the attribute information in the first and second parameters can be extracted and compared item by item according to the pre-defined rules. Based on parameterized information and fixed rules, automated and standardized compliance judgment is achieved. It is worth noting that the pre-defined connection validity verification is not a hard-coded binding for a specific port or protocol, but rather a general verification rule automatically executed based on standardized parameterized interface / port attributes.

[0033] In step S104, in response to the successful connection validity check, a connection relationship is established between the sub-circuit module interface and the parent circuit module interface.

[0034] In the example, when the connection validity check shows that the sub-circuit module interface and the parent circuit module interface meet the preset connection validity check rules, the two can be connected based on the parameter and interface correspondence to ensure normal signal transmission and reception.

[0035] Therefore, by constructing circuit modules with corresponding interfaces or ports and corresponding parameters, performing connection validity checks based on preset connection validity rules and interface parameters, and establishing connection relationships after the checks are passed, invalid connections and circuit errors can be avoided, thereby improving the accuracy and reliability of chip integration, based on clearly defining the signal interaction rules and attribute matching between sub-modules and parent modules.

[0036] In step S105, based on the first parameter, the second parameter, and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, integration code is generated. The integration code is used to characterize the signal interaction and parameter configuration between the circuit modules of the chip to be integrated.

[0037] In step S106, the chip is automatically integrated based on the integration code.

[0038] In the example, by reading the first parameter of the parent circuit module interface, the second parameter of the child circuit module interface, and the established legal connection relationship between them, information such as interface or port attributes, signal flow, and module associations can be converted into standard circuit description code according to a unified code standard. This fully reflects the signal interaction methods and parameter configurations between the various circuit modules inside the chip. The generated integrated code structure can be directly used in the chip design flow without manual writing or extensive modifications. After the integrated code is generated, chip integration is automatically performed based on this code, assembling all child circuit modules into the parent circuit module according to the code definition, forming a complete top-level chip architecture, realizing a complete process from modular design to actual chip integration. For example, in SoC chip design, this method can quickly generate top-level RTL code and automatically integrate multiple IP cores based on the code, significantly shortening the design cycle.

[0039] Therefore, by parametrically modeling the circuit module interfaces and constructing a unified connection validity verification mechanism based on these parameters, while simultaneously using parameters and connection relationships to drive the automatic generation of integration code, the chip integration process can be automated and its consistency controlled. Specifically, by constructing parent and child circuit modules, clarifying interface and port attributes with the help of parameters, and performing connection validity verification based on preset rules and interface parameters, the legality and stability of signal paths can be ensured, and illegal connections can be eliminated. Furthermore, by automatically generating standardized integration code based on parameters and legal connection relationships, and completing the automatic chip integration based on the code, the entire process can be replaced by manual writing and verification, significantly improving chip integration efficiency and accuracy, reducing the probability of errors, while ensuring the readability and maintainability of the integration code, and significantly optimizing the front-end design and integration process of large chips.

[0040] The following describes in further detail various aspects of the automated chip integration method according to embodiments of the present disclosure.

[0041] In some embodiments, the parent circuit module interface includes an external interface and internal wiring. The external interface is used to connect the parent circuit module to the child circuit module instantiated in the parent circuit module, and the internal wiring is used to connect the child circuit module instantiated in the parent circuit module.

[0042] In the example, the external interface handles the signal interaction between the parent circuit module (as the top-level carrier) and the instantiated child circuit modules. It serves as the external communication channel between the parent and child circuit modules, enabling the parent circuit module to control the child circuit modules, transmit data, and provide status feedback, ensuring effective communication between the top-level architecture and each functional unit. Internal connections, on the other hand, act as internal interconnection channels between child circuit modules, allowing for more standardized internal signal flow.

[0043] In the example, the internal interconnects, besides enabling direct interconnection between sub-circuit modules, can also serve as intermediate interconnect interfaces, using an interface structure consistent with the sub-circuit module interface or parent circuit module interface, and through standardized signal mapping and forwarding logic, establishing decoupled signal transmission channels between different modules. This intermediate interconnection mechanism based on internal interconnects supports flexible connections between multiple modules without needing to define new signals for each group of sub-module interconnections, thereby improving the scalability and module reusability of system integration.

[0044] Therefore, this interface design that separates the internal and external interfaces can clearly distinguish between two different scenarios: external interaction of the top-level carrier and internal module interconnection. This makes signal flow and connection relationships easier to manage and maintain, and adapts to the integration needs of complex chip multi-module interconnection.

[0045] In some embodiments, the first parameter includes the name of the parent circuit module interface and a first port list, the first port list including the name, bit width, signal transmission type, signal source, and signal destination of at least one first port; the second parameter includes the name of the child circuit module interface and a second port list, the second port list including the name, bit width, signal transmission type, signal source, and signal destination of at least one second port, the signal transmission type including input type, output type, and connection line type.

[0046] In the example, the parent circuit module interface name can be used to uniquely identify the interface, facilitating calling and differentiation. The first port list records in detail the name, bit width, signal transmission type, signal source, and signal destination of each first port, thus fully depicting the basic characteristics and signal flow relationships of the first port. The second parameter also includes the sub-circuit module interface name and the second port list, serving the same purpose as the first parameter, and can be used to accurately define the key attributes of the sub-module interface and its ports. The signal transmission type is divided into input type, output type, and connection type, corresponding to signal reception, signal transmission, and intermediate transfer functions, respectively, providing a clear type judgment basis for connection validity verification.

[0047] Therefore, by clearly defining the specific composition of the first and second parameters and the signal transmission type, the interface and port attributes can be completely and standardizedly characterized. This enables the interface to adapt to the port attribute requirements of various standard protocols such as AXI, APB, and ADB, providing a foundation for the automatic integration of heterogeneous interfaces and a precise basis for connection validity verification, effectively improving the accuracy and reliability of verification. At the same time, it can make port matching, connection establishment, and integration code generation more standardized, significantly reducing manual configuration errors and improving the stability and efficiency of chip integration.

[0048] In some embodiments, based on preset connection validity verification rules, a first parameter, and a second parameter, connection validity verification is performed on the sub-circuit module interface and the parent circuit module interface, including: determining the parent circuit module interface and the sub-circuit module interface to be connected as a first interface to be connected and a second interface to be connected, respectively; performing connection validity verification one by one on each group of ports to be connected in the first interface to be connected and the second interface to be connected, wherein each group of ports to be connected includes a third port and a fourth port, wherein the third port is located in either the first interface to be connected or the second interface to be connected, and the fourth port is located in the other; and determining that the connection validity verification of the first interface to be connected and the second interface to be connected has passed in response to each group of ports to be connected passing the connection validity verification.

[0049] In the example, when performing connection validity verification, the parent circuit module interface and child circuit module interface to be connected can be marked as the first interface to be connected and the second interface to be connected, respectively, to clarify the objects of this connection validity verification. Then, using ports as the smallest unit, each pair of ports that need to be connected between the two interfaces is checked for compliance. The third and fourth ports come from the two interfaces to be connected, and they are paired; the verification order is not important, only whether the pairing itself conforms to the rules. During the connection validity verification process, key information such as port width, signal transmission type, signal source and destination can be checked item by item according to preset verification rules to ensure that each pair of ports meets the basic specifications of circuit connection. Only when all the port pairs to be connected in the two interfaces pass the connection validity verification is the connection validity verification of the two interfaces considered successful. The connection validity verification can be based on the standardized interface and / or port attributes defined in the first and second parameters, and can be automatically executed by preset rules, thereby decoupling the verification logic from the specific port configuration and improving the universality and automation of the verification process.

[0050] Therefore, by refining interface-level verification to verify each port pair individually, accurate and comprehensive connection validity verification can be achieved, avoiding the omission of connection errors. Using the passing of connection validity verification for all port pairs as the condition for passing interface connection validity verification can significantly improve the reliability of connection determination, make error location more intuitive, and further enhance the credibility of chip integration results.

[0051] In some embodiments, for each group of ports to be connected in the first and second interfaces to be connected, connection validity checks are performed one by one, including: in response to the signal transmission type of the third port being an output type, determining whether the signal transmission type of the fourth port is an input type; in response to the signal transmission type of the fourth port not being an input type, determining whether the signal source of the third port is empty; in response to the signal source of the third port being empty, determining that the connection validity check has passed.

[0052] In the example, when verifying the connection validity of ports in two interfaces to be connected, if the signal transmission type of the third port is output, it can be checked whether the paired fourth port is input. If the fourth port is not input, it can be further determined whether the signal source of the third port is empty. When the signal source of the third port is empty, it means that the port is not driven by other signals, which meets the valid connection conditions for an output port, and the connection verification of this set of ports can be determined to be successful. This verification logic strictly follows the underlying rules that output ports cannot be directly connected to input ports and that output ports must not have other drivers.

[0053] Therefore, by performing step-by-step verification of the connection of output type ports, it is possible to strictly follow the circuit signal transmission specifications, avoid illegal connection situations such as repeated driving of output ports, and improve the accuracy and rationality of verification. At the same time, it makes the verification rules easier to execute and troubleshoot, reduces the connection error rate, and ensures the stability and legality of chip integration connections.

[0054] In some embodiments, for each group of ports to be connected in the first interface to be connected and the second interface to be connected, the connection validity check is performed one by one, and the method further includes: in response to the signal transmission type of the third port being an input type and the signal source of the third port being not empty, the connection validity check is determined to be passed.

[0055] In the example, if the signal transmission type of the third port is input, the signal source of that port can be directly checked for valid configuration according to the preset connection validity verification rules. Since the function of an input port is to receive external drive signals, a clear signal source is required for it to function properly. Therefore, when the third port is determined to be input and its signal source is not empty, it indicates that the port has valid signal drive conditions, conforms to the basic design specifications of circuit connections, and thus the connection validity verification of this group of ports can be confirmed as passed. This verification rule, based on the requirement that the input port must have a drive source, avoids problems such as input ports having no signal drive or being unusable due to being floating, thereby ensuring that the ports can normally complete signal reception and transmission after connection.

[0056] Therefore, by clearly defining the verification rules for input type ports, it can be ensured that the input ports must have a valid signal source, eliminating illegal connections such as floating or undriven connections, making the verification logic coverage more comprehensive, and further improving the reliability of chip integration.

[0057] In some embodiments, for each group of ports to be connected in the first and second interfaces to be connected, a connection validity check is performed one by one, which further includes: in response to the signal transmission type of the third port being a connection line type and the signal source of either the third port or the fourth port being empty, while the signal source of the other port is not empty, or in response to the signal transmission type of the third port being a connection line type, the signal transmission type of the fourth port being an input type, and the signal source of the fourth port being empty, the connection validity check is determined to be passed.

[0058] In the example, if the third port is a connector type, it only needs to meet one of two valid conditions to pass the verification. The first condition is that the signal source of the connector type port and the other port is either empty or not empty, ensuring that the signal has a unique driver, no conflict, and no floating, meeting the basic requirement of unidirectional signal transmission for intermediate connections. The second condition is that the third port is a connector type, the fourth port is an input type, and the signal source of the fourth port is empty, ensuring that the input port is driven only by the connector and there are no multiple driver issues. The above verification rules strictly adhere to the circuit principles that intermediate connections are used for signal transfer, bidirectional floating or bidirectional driving is not allowed, and input ports must be driven by valid connections. By clearly defining the conditions, connection risks such as signal short circuits, no driver, and multiple drivers are avoided.

[0059] Therefore, by clearly defining the two valid verification scenarios for connection cable type ports, the signal transfer scenarios of intermediate connections can be fully covered, effectively avoiding typical problems such as signal idling, multiple drives, and connection conflicts, making the overall verification rules more comprehensive and rigorous. At the same time, it complements the aforementioned input and output port rules, greatly improving the accuracy and robustness of connection determination, thereby ensuring the stability and accuracy of chip integrated connections.

[0060] In some embodiments, based on the first parameter, the second parameter, and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, the integration code is generated, including: based on the first parameter, generating interface definition code and parameter definition code to describe the parent circuit module interface, wherein the interface definition code is used to declare the hardware description of the parent circuit module interface, and the parameter definition code is used to declare the first parameter; traversing the sub-circuit modules, based on the second parameter and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, generating module instantiation code and parameter mapping code for the sub-circuit module within the parent circuit module, wherein the module instantiation code is used to declare the hardware description of the sub-circuit module interface, and the parameter mapping code is used to declare the mapping relationship between the sub-circuit module interface with the established connection relationship and the corresponding first and second parameters of the parent circuit module interface, and the integration code includes interface definition code, parameter definition code, module instantiation code, and parameter mapping code.

[0061] In the example, when generating integration code, interface definition code and parameter definition code can be generated based on the information recorded in the first parameter, such as the parent circuit module interface name and the first port attribute. The former is used to complete the hardware declaration of the parent module interface, and the latter is used to fix the configuration content of the first parameter, ensuring that the top-level interface specification is readable. Then, by traversing all legally connected sub-circuit modules and combining the second parameter with the determined connection relationship, corresponding module instantiation code and parameter mapping code can be generated. The module instantiation code is used to complete the hardware instantiation declaration of the sub-circuit module within the parent circuit module, clarifying, for example, the hardware structure and form of the sub-module interface; the parameter mapping code can convert the connection relationship between the sub- and parent circuit module interfaces into a parameter correspondence relationship, ensuring accurate matching of configurations such as port attributes, signal flow direction, and bit width. The final integrated code can contain four parts: interface definition, parameter definition, module instantiation, and parameter mapping, to fully characterize the code elements required for chip integration.

[0062] In the example, during the generation of integration code, additionally, custom strings can be added within the parent circuit module to meet flexible expansion needs during chip integration. Custom strings can be managed, for example, in list form, to carry additional design content that cannot be automatically generated through standardized interfaces, ports, parameters, and connection relationships within the module. This content can be directly embedded into the final generated integration code. This part does not affect the core processes of port connection validity verification, parameter mapping, and module instantiation; it exists only as supplementary configuration. When generating integration code, for example, custom strings can be inserted into the corresponding areas of the parent circuit module at preset positions, thus forming a complete chip integration code together with interface definition code, parameter definition code, module instantiation code, and parameter mapping code. This achieves standardized and automated generation while improving the adaptability and scalability of the solution to complex chip design scenarios and special design requirements.

[0063] In the example, there may be cases where there is no corresponding match between the parent circuit module interface and the child circuit module interface. For example, when the output port of the child circuit module does not have a corresponding input port in the parent circuit module, the output port can be marked as a blank character or ignored directly in the module instantiation code; when the input port of the child circuit module does not have a corresponding output port in the parent circuit module, the input port can be connected to a preset default constant in the module instantiation code to satisfy RTL syntax rules and avoid invalid connections or floating signals affecting the integration code generation.

[0064] Therefore, by generating standardized integration code in steps and modules, we can ensure that the code structure is standardized, the attributes are accurate, and the mapping relationship is clear, which greatly improves the readability and maintainability of the code and facilitates possible manual modification or maintenance in the future. The automatically generated parameter mapping code can realize signal matching and parameter transmission between different protocol interfaces, reduce the interface adaptation cost, and improve the efficiency of SoC integration.

[0065] Figure 2 This is a schematic diagram illustrating the internal structure of a parent circuit module according to an embodiment of the present disclosure.

[0066] like Figure 2 As shown, in some examples, the parent circuit module 201 can be a top-level integrated unit that carries the instantiated circuit module, and its internal components may include a first parameter 202, an external interface 203, internal wiring 204, and the instantiated child circuit module 206 (e.g., Figure 2For example, it includes sub-circuit module 1 and sub-circuit module 2) and custom code 205. The external interface 203 and internal connection 204 together constitute the parent circuit module interface, which can be used to realize signal interaction between the parent circuit module 201 and sub-circuit module 206, and between sub-circuit module 206; the first parameter 202 can be used to characterize the attributes of the parent circuit module interface; the external interface 203 and sub-circuit module 206 can be connected through connection relationship 208 to realize signal interaction between the parent circuit module 201 and sub-circuit module 206; the internal connection 204 can serve as the interconnection structure within the parent circuit module 201, and the interconnection between sub-circuit modules 206 can be realized through connection relationship 209; connection relationship 207 can reflect the logic of passing the first parameter 202 to sub-circuit module 206 when instantiating sub-circuit module 206; the custom code 205 can be a custom string code additionally included within the parent circuit module to achieve the integration of standardized generation and customized design, adapting to personalized design needs such as special circuit logic and constraint configuration. The overall architecture described above provides clear structural support for connection validity verification, connection relationship establishment, and integration code generation.

[0067] and Figure 2 Correspondingly, Figure 3 This is a schematic diagram illustrating chip integration code according to an embodiment of the present disclosure.

[0068] like Figure 3 As shown, in some examples, the final generated integrated code can begin with the parent circuit module 201 declaration section 301. The parameter definition section 302 declares the first parameter 202 corresponding to the parent circuit module interface; the interface declaration section 303 defines the external interface 203; the internal signal declaration section 304 defines the internal connection 204; the custom string section 305 embeds custom code 205; the sub-circuit module instantiation declaration section 306 and parameter mapping section 307 complete the logic for passing the first parameter 202 to the sub-circuit module 206; and the external interface mapping section 308 and internal connection mapping section 309 respectively implement the signal connections between the sub-circuit module interface and the external interface 203 and internal connection 204. The external interface mapping section 308 represents the connection relationship between the parent circuit module interface and the sub-circuit module interface, corresponding to... Figure 2 The connection logic of the connection relationship 208; the internal connection mapping part 309 can represent the connection between sub-circuit modules 206 through internal connection 204, corresponding to Figure 2The connection logic of connection relationship 209 is shown in the example code. This integrated code example uses a structured approach to map interface attributes, connection relationships, and parameter configurations to different code segments. This allows for a complete representation of the signal interaction and parameter configuration relationships between the parent circuit module and the child circuit module. It also makes the integrated code automatically generated, highly readable, traceable, and maintainable.

[0069] According to embodiments of this disclosure, an automated chip integration apparatus is also provided.

[0070] Figure 4 This is a block diagram illustrating a chip automation integration apparatus according to an embodiment of the present disclosure.

[0071] like Figure 4 As shown, in some embodiments, the chip automated integration device 400 includes a parent circuit module construction unit 401, a child circuit module construction unit 402, a validity verification unit 403, a connection relationship establishment unit 404, an integration code generation unit 405, and an integration unit 406.

[0072] The parent circuit module construction unit 401 is configured to: construct a parent circuit module, which is used to accommodate the instantiated circuit module. The parent circuit module has a parent circuit module interface, which includes at least one first port and has a corresponding first parameter. The first parameter is used to characterize the attributes of the parent circuit module interface and the at least one first port.

[0073] The sub-circuit module construction unit 402 is configured to: construct a sub-circuit module, which is used to characterize a circuit module instantiated in a parent circuit module. The sub-circuit module has a sub-circuit module interface for interacting with the parent circuit module via circuit signals. The sub-circuit module interface includes at least one second port and has a corresponding second parameter, which is used to characterize the attributes of the sub-circuit module interface and the at least one second port.

[0074] The legality verification unit 403 is configured to perform connection legality verification on the sub-circuit module interface and the parent circuit module interface based on preset connection legality verification rules, first parameters and second parameters. The connection legality verification is used to determine whether a connection can be successfully established between the sub-circuit module interface and the parent circuit module interface.

[0075] The connection establishment unit 404 is configured to establish a connection between the sub-circuit module interface and the parent circuit module interface in response to the connection validity verification passing.

[0076] The integrated code generation unit 405 is configured to generate integrated code based on the first parameter, the second parameter, and the established connection relationship between the sub-circuit module interface and the parent circuit module interface. The integrated code is used to characterize the signal interaction and parameter configuration between the circuit modules of the chip to be integrated.

[0077] Integration unit 406 is configured to automatically integrate chips based on integration code.

[0078] The operations of the aforementioned parent circuit module construction unit 401, child circuit module construction unit 402, legality verification unit 403, connection relationship establishment unit 404, integrated code generation unit 405, and integration unit 406 can be combined. Figure 1 The operations of steps S101-S106 are the same, so the details of each aspect will not be repeated here.

[0079] In some embodiments, the legality verification unit 403 further includes a first determination unit 4031, configured to: determine the parent circuit module interface and the child circuit module interface to be connected to each other as the first interface to be connected and the second interface to be connected, respectively.

[0080] In some embodiments, the validity verification unit 403 further includes an execution unit 4032, configured to: perform connection validity verification one by one for each group of ports to be connected to each other in the first interface to be connected and the second interface to be connected, wherein each group of ports to be connected to each other includes a third port and a fourth port, wherein the third port is located in either the first interface to be connected or the second interface to be connected, and the fourth port is located in the other.

[0081] In some embodiments, the legitimacy verification unit 403 further includes a second determination unit 4033, configured to: determine that the connection legitimacy verification between the first interface to be connected and the second interface to be connected has passed in response to each group of ports to be interconnected passing the connection legitimacy verification.

[0082] In some embodiments, the execution unit 4032 further includes a first determination unit 4032-1, configured to: determine whether the signal transmission type of the fourth port is an input type in response to the signal transmission type of the third port being an output type.

[0083] In some embodiments, the execution unit 4032 further includes a second determination unit 4032-2, configured to: determine whether the signal source of the third port is empty in response to the signal transmission type of the fourth port not being an input type.

[0084] In some embodiments, the execution unit 4032 further includes a third determining unit 4032-3, configured to: determine that the connection validity verification has passed in response to the signal source of the third port being empty.

[0085] In some embodiments, the execution unit 4032 further includes a fourth determination unit 4032-4, configured to: determine that the connection validity verification has passed in response to the signal transmission type of the third port being an input type and the signal source of the third port being non-empty.

[0086] In some embodiments, the execution unit 4032 further includes a fifth determining unit 4032-5, configured to: determine that the connection validity verification passes in response to the signal transmission type of the third port being a connection line type and the signal source of either the third port or the fourth port being empty, while the signal source of the other port is not empty; or in response to the signal transmission type of the third port being a connection line type, the signal transmission type of the fourth port being an input type, and the signal source of the fourth port being empty.

[0087] In some embodiments, the integrated code generation unit 405 further includes a first generation unit 4051, configured to: generate interface definition code and parameter definition code for describing the interface of the parent circuit module based on the first parameter, wherein the interface definition code is used to declare the hardware description of the interface of the parent circuit module, and the parameter definition code is used to declare the first parameter.

[0088] In some embodiments, the integrated code generation unit 405 further includes a second generation unit 4052, configured to: traverse the sub-circuit modules, and based on the second parameters and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, generate module instantiation code and parameter mapping code for the sub-circuit module within the parent circuit module. The module instantiation code is used to declare the hardware description of the sub-circuit module interface, and the parameter mapping code is used to declare the mapping relationship between the first and second parameters corresponding to the sub-circuit module interface with the connection relationship and the parent circuit module interface. The integrated code includes interface definition code, parameter definition code, module instantiation code, and parameter mapping code.

[0089] According to one aspect of this disclosure, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0090] According to one aspect of this disclosure, a non-transitory computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0091] According to one aspect of this disclosure, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above.

[0092] Figure 5An example computer device 500 is shown in which any of the embodiments described herein may be implemented. The computer device 500 may be used to implement one or more components of the systems and methods described above. The computer device 500 may include a bus 502 or other communication mechanism for communicating information, and one or more processors 504 coupled to the bus 502 for processing information. The processor 504 may be, for example, one or more general-purpose microprocessors.

[0093] Computer device 500 may also include main memory 506, such as random access memory (RAM), cache, and / or other dynamic storage devices, coupled to bus 502, for storing information and instructions to be executed by processor 504. Main memory 506 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 504. Such instructions, when stored in a storage medium accessible to processor 504, can make computer device 500 a special-purpose machine customized to perform the operations specified in the instructions. Main memory 506 may include non-volatile media and / or volatile media. Non-volatile media may include, for example, optical discs or magnetic disks. Volatile media may include dynamic memory. Common media formats may include, for example, floppy disks, collapsible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs (read-only optical disc drives), any other optical data storage media, any physical media with a perforated arrangement, RAM (random access memory), DRAM (dynamic random access memory), PROM (programmable read-only memory) and EPROM (erasable programmable read-only memory), FLASH-EPROM (fast erase programmable read-only memory), NVRAM (non-volatile random access memory), any other memory chips or tape cartridges, or network versions of the above.

[0094] Computer device 500 may implement the techniques described herein using custom hardwired logic, one or more ASICs (Application-Specific Integrated Circuits) or FPGAs (Field-Programmable Gate Arrays), firmware, and / or program logic, which, when combined with computer device 500, enable computer device 500 to become a special-purpose machine or to be programmed therein. According to one embodiment, the techniques herein are executed by computer device 500 in response to processor 504 executing one or more sequences of one or more instructions contained in main memory 506. Such instructions may be read into main memory 506 from another storage medium, such as storage device 508. Executing the sequence of instructions contained in main memory 506 causes processor 504 to perform the processing steps described herein. For example, the processes / methods disclosed herein may be implemented by computer program instructions stored in main memory 506. When these instructions are executed by processor 504, they may perform the steps shown in the corresponding figures and as described above. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0095] Computer device 500 also includes a network interface 510 coupled to bus 502. Network interface 510 can provide bidirectional data communication coupled to one or more network links connected to one or more networks. As another example, network interface 510 can be a local area network (LAN) card to provide data communication connectivity with a compatible LAN (or a WAN component communicating with a WAN (wide area network)). Wireless links can also be implemented.

[0096] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or processor-implemented engine may be distributed across many geographic locations.

[0097] Each process, method, and algorithm described in the preceding sections can be embodied in a code module executed by one or more computer systems or computer processors including computer hardware, and can be fully or partially automated by them. These processes and algorithms can be implemented, in part or in whole, in a specific application circuit.

[0098] When the functions disclosed herein are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, can be embodied in the form of a software product. This software product can be stored in a storage medium and includes instructions to cause a computer device (which may be a personal computer, server, network device, etc.) to perform all or part of the steps of the methods described in the embodiments of this application. The storage medium may include a flash drive, a portable hard drive, ROM, RAM, a magnetic disk, an optical disk, another medium suitable for storing program code, or any combination thereof.

[0099] The embodiments disclosed herein can be implemented via a cloud platform, server, or group of servers that interact with a client. The client can be a terminal device or a client registered by a user on the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can install platform applications.

[0100] The various features and processes described above can be used independently or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Furthermore, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in a non-specifically disclosed order, or multiple blocks or states may be combined in a single block or state. Exemplary blocks or states may be executed serially, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed exemplary embodiments. The exemplary systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed exemplary embodiments.

[0101] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. An algorithm may consist of program code or instructions stored in memory (such as the non-transitory computer-readable storage medium described above). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not be explicitly programmed into the computer to perform the function, but may learn from training data to obtain a predictive model for performing that function.

[0102] The various operations of the exemplary methods described herein can be performed at least in part by one or more processors, which are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors can constitute the engine of a processor implementation whose operation is to perform one or more of the operations or functions described herein.

[0103] Similarly, the methods described herein can be implemented at least partially by a processor, where a specific processor or one or more processors are examples of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also run in a “cloud computing” environment or as “Software as a Service” (SaaS) to support the execution of the relevant operations. For example, at least some operations can be performed by a group of computers (as an example of a machine including processors), which can be accessed via a network (e.g., the Internet) and through one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0104] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0105] In this specification, multiple instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are described and illustrated as independent operations, one or more individual operations may be performed concurrently, and these operations are not required to be performed in the order shown. Structures and functionalities presented as independent components in the example configuration may be implemented as combined structures or components. Similarly, structures and functionalities presented as individual components may be implemented as independent components. These and other variations, modifications, additions, and improvements are all within the scope of this document.

[0106] As used herein, “or” is inclusive rather than exclusive unless explicitly stated or indicated by context. Furthermore, “and” is both common and individual unless explicitly stated or indicated by context. Moreover, multiple instances may be provided for the resources, operations, or structures described herein as a single example. Furthermore, the boundaries between various resources, operations, engines, and data stores are somewhat arbitrary, and specific operations are illustrated within the context of a particular illustrative configuration. The allocation of other functionalities is conceivable and may fall within the scope of various embodiments of this disclosure. Generally, structures and functionalities presented as independent resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functionalities presented as individual resources may be implemented as independent resources. These and other variations, modifications, additions, and improvements are all within the scope of embodiments of this disclosure. Therefore, this specification and accompanying drawings should be viewed in an illustrative rather than restrictive sense.

[0107] The terms “comprising” or “including” are used to indicate the presence of a subsequently stated feature, but do not preclude the addition of other features. Conditional language, in particular, such as “may,” “can,” or “may,” unless specifically stated or otherwise understood in the context of use, is generally intended to express that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Therefore, such conditional language generally does not imply that a feature, element, and / or step is necessary in any way for one or more embodiments, or that one or more embodiments must include logic that, with or without user input or prompting, determines whether such features, elements, and / or steps are included in any particular embodiment, or whether they are to be performed in any particular embodiment.

Claims

1. A method for automated chip integration, characterized in that, The method includes: A parent circuit module is constructed to accommodate the instantiated circuit module. The parent circuit module has a parent circuit module interface, which includes at least one first port. The parent circuit module interface has corresponding first parameters, which include the name of the parent circuit module interface and a list of first ports. The first port list includes the name, bit width, signal transmission type, signal source, and signal destination of the at least one first port. The signal transmission type includes input type, output type, and connection type. A sub-circuit module is constructed, which is used to characterize the circuit module instantiated in the parent circuit module. The sub-circuit module has a sub-circuit module interface for interacting with the parent circuit module through circuit signals. The sub-circuit module interface includes at least one second port. The sub-circuit module interface has a corresponding second parameter. The second parameter includes the name of the sub-circuit module interface and a list of second ports. The second port list includes the name, bit width, signal transmission type, signal source, and signal destination of the at least one second port. Based on preset connection validity verification rules, the first parameter, and the second parameter, a connection validity verification is performed on the sub-circuit module interface and the parent circuit module interface. This connection validity verification determines whether a connection can be successfully established between the sub-circuit module interface and the parent circuit module interface. The process of performing the connection validity verification on the sub-circuit module interface and the parent circuit module interface based on preset connection validity verification rules, the first parameter, and the second parameter includes: The parent circuit module interface and the child circuit module interface to be connected to each other are respectively designated as the first interface to be connected and the second interface to be connected. For each group of ports in the first interface to be connected and the second interface to be connected, a connection validity check is performed one by one. Each group of ports to be connected includes a third port and a fourth port. The third port is located in either the first interface to be connected or the second interface to be connected, and the fourth port is located in the other. In response to the fact that each group of ports to be connected to each other has passed the connection validity check, it is determined that the connection validity check between the first interface to be connected and the second interface to be connected has passed; In response to the successful connection validity verification, a connection relationship is established between the sub-circuit module interface and the parent circuit module interface; Based on the first parameter, the second parameter, and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, integration code is generated. The integration code is used to characterize the signal interaction and parameter configuration between the circuit modules of the chip to be integrated. The chip is automatically integrated based on the integration code.

2. The method according to claim 1, characterized in that, The parent circuit module interface includes an external interface and internal connections. The external interface is used to connect the parent circuit module to the child circuit module instantiated in the parent circuit module, and the internal connections are used to connect the child circuit module instantiated in the parent circuit module.

3. The method according to claim 1, characterized in that, The process of performing connection validity verification for each group of ports in the first and second interfaces to be connected, including: In response to the signal transmission type of the third port being an output type, it is determined whether the signal transmission type of the fourth port is an input type; In response to the fact that the signal transmission type of the fourth port is not an input type, it is determined whether the signal source of the third port is empty; If the signal source of the third port is empty, the connection validity check is deemed to have passed.

4. The method according to claim 1, characterized in that, The process of performing connection validity verification for each group of ports in the first and second interfaces to be connected, including: In response to the fact that the signal transmission type of the third port is input type and the signal source of the third port is not empty, the connection validity check is determined to be successful.

5. The method according to any one of claims 1-4, characterized in that, The process of performing connection validity verification for each group of ports in the first and second interfaces to be connected, including: If the signal transmission type of the third port is a connection type and the signal source of either the third port or the fourth port is empty, while the signal source of the other port is not empty, or if the signal transmission type of the third port is a connection type, the signal transmission type of the fourth port is an input type, and the signal source of the fourth port is empty, then the connection validity check is determined to be successful.

6. The method according to any one of claims 1-4, characterized in that, The generation of integration code based on the first parameter, the second parameter, and the established connection relationship between the sub-circuit module interface and the parent circuit module interface includes: Based on the first parameter, interface definition code and parameter definition code are generated to describe the interface of the parent circuit module, wherein the interface definition code is used to declare the hardware description of the interface of the parent circuit module, and the parameter definition code is used to declare the first parameter. The sub-circuit modules are traversed. Based on the second parameter and the established connection relationship between the sub-circuit module interface and the parent circuit module interface, module instantiation code and parameter mapping code for the sub-circuit module within the parent circuit module are generated. The module instantiation code declares the hardware description of the sub-circuit module interface, and the parameter mapping code declares the mapping relationship between the first and second parameters corresponding to the connected sub-circuit module interface and the parent circuit module interface. The integration code includes the interface definition code, the parameter definition code, the module instantiation code, and the parameter mapping code.

7. A chip automated integration device, characterized in that, The automated chip integration device includes: A parent circuit module construction unit is configured to construct a parent circuit module, which is used to accommodate an instantiated circuit module. The parent circuit module has a parent circuit module interface, which includes at least one first port. The parent circuit module interface has corresponding first parameters, which include the name of the parent circuit module interface and a list of first ports. The first port list includes the name, bit width, signal transmission type, signal source, and signal destination of the at least one first port. The signal transmission type includes input type, output type, and connection type. A sub-circuit module construction unit is configured to construct a sub-circuit module, the sub-circuit module being used to characterize a circuit module instantiated in the parent circuit module. The sub-circuit module has a sub-circuit module interface for interacting with the parent circuit module via circuit signals. The sub-circuit module interface includes at least one second port. The sub-circuit module interface has corresponding second parameters. The second parameters include the name of the sub-circuit module interface and a list of second ports. The second port list includes the name, bit width, signal transmission type, signal source, and signal destination of the at least one second port. A validity verification unit is configured to perform connection validity verification on the sub-circuit module interface and the parent circuit module interface based on preset connection validity verification rules, the first parameter, and the second parameter. The connection validity verification is used to determine whether a connection can be successfully established between the sub-circuit module interface and the parent circuit module interface. The validity verification unit includes: The first determining unit is configured to determine the parent circuit module interface and the child circuit module interface to be connected to each other as the first interface to be connected and the second interface to be connected, respectively. The execution unit is configured to perform connection validity checks one by one for each group of ports to be connected in the first interface to be connected and the second interface to be connected. Each group of ports to be connected includes a third port and a fourth port. The third port is located in either the first interface to be connected or the second interface to be connected, and the fourth port is located in the other. The second determining unit is configured to determine that the connection validity check between the first interface to be connected and the second interface to be connected has passed in response to each group of ports to be interconnected passing the connection validity check. The connection relationship establishment unit is configured to establish a connection relationship between the sub-circuit module interface and the parent circuit module interface in response to the successful connection validity verification; An integrated code generation unit is configured to generate integrated code based on the first parameter, the second parameter, and the established connection relationship between the sub-circuit module interface and the parent circuit module interface. The integrated code is used to characterize the signal interaction and parameter configuration between the circuit modules of the chip to be integrated. An integration unit is configured to automatically integrate the chip based on the integration code.

8. A computer device, characterized in that, The computer device includes: At least one processor; A memory having a computer program stored thereon, wherein, when executed by the at least one processor, the computer program causes the at least one processor to perform the method of any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-6.

Images