Gate driving circuit and control method thereof, display panel and display device

Abstract

The application discloses a gate driving circuit and a control method thereof, a display panel and a display device, and relates to the technical field of display. The circuit comprises a plurality of cascaded gate driving units and a corresponding logic gate circuit. When a certain gate driving unit provides a gate scanning signal for a pixel row corresponding to the gate driving unit, the logic gate circuit corresponding to the gate driving unit determines a neighbor scanning signal according to the gate scanning signal, and drives a neighbor pixel row (i.e. the next pixel row adjacent to the pixel row corresponding to the gate driving unit) through the neighbor scanning signal, so that the number of gate driving units is half of the number of pixel rows, the via corrosion risk of the gate driving circuit is effectively reduced, and the display quality of the panel is significantly improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit and its control method, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, the technology of integrating GDL (Gate Driver on Array, also known as gate driving circuit) into the display panel is widely used in liquid crystal display devices. This gate driving circuit typically includes multiple cascaded gate driving units, each corresponding to a row of pixel units, used to output scan signals to the corresponding gate lines.

[0003] Currently, gate drive units typically consist of a thin-film transistor (TFT), a first metal layer, a second metal layer, and vias penetrating a passivation layer. The first metal layer forms the gate of the TFT and facilitates short-distance wiring, while the second metal layer forms the source and drain of the TFT and facilitates long-distance signal transmission lines. To achieve electrical connections between different metal layers, vias are created in the passivation layer and filled with conductive material (such as indium tin oxide, ITO) to form vertical conductive channels. However, the physical structure of existing gate drive circuits has inherent reliability vulnerabilities. Because the passivation layer is exposed to form vias, the integrity of the passivation layer's insulating material is compromised. In high-temperature and high-humidity environments (such as 85°C / 85% humidity, i.e., double 85 testing), external moisture can easily penetrate the display panel through the via structure. This moisture combines with residual etching solutions and metal ions from the panel manufacturing process to form a galvanic cell effect, accelerating metal corrosion at the vias. This leads to abnormal gate drive signal transmission, ultimately resulting in display defects such as horizontal lines on the screen, severely impacting display quality.

[0004] Therefore, how to reduce the risk of via corrosion in the gate drive circuit to improve the display quality of the panel is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a gate driving circuit and its control method, a display panel, and a display device, which aim to reduce the risk of via corrosion in the gate driving circuit to improve the display quality of the panel.

[0006] To achieve the above objectives, this application provides a gate driving circuit, the gate driving circuit comprising: Multiple cascaded gate driving units, one gate driving unit corresponds to one pixel row, and the current gate driving unit is configured to provide a gate scan signal to the corresponding pixel row. The current gate driving unit is any one of the multiple gate driving units. The logic gate circuits are distributed at the signal output terminals of each gate driving unit. The logic gate circuit corresponding to the gate driving unit of that level is called the local level logic gate circuit. The input terminal of the local level logic gate circuit is electrically connected to the signal output terminal of the gate driving unit of that level, and the output terminal of the local level logic gate circuit is electrically connected to the neighboring pixel row. The logic gate circuit is configured to determine the neighboring level scan signal based on the gate scan signal output by the local level gate driving unit, and to drive the neighboring pixel row to scan using the neighboring level scan signal, such that the number of gate driving units is half the number of pixel rows. The neighboring pixel row is the next pixel row adjacent to the pixel row corresponding to the gate driving unit of this level.

[0007] In one embodiment, the logic gate circuit at this level includes: a non-inverting delay unit, an inverting delay unit, and a low-potential terminal; The first input terminal of the in-phase delay unit is electrically connected to the signal output terminal of the gate driving unit of the same level, the second input terminal of the in-phase delay unit is electrically connected to the output terminal of the inverting delay unit, and the output terminal of the in-phase delay unit constitutes the output terminal of the logic gate circuit of the same level and is electrically connected to the neighboring pixel row. The first input terminal of the inverting delay unit is electrically connected to the signal output terminal of the gate driving unit of the same stage, the second input terminal of the inverting delay unit is electrically connected to the output terminal of the non-inverting delay unit, and the output terminal of the inverting delay unit is electrically connected to the low potential terminal. The first input terminal of the in-phase delay unit is electrically connected to the first input terminal of the in-phase delay unit, and the connection point of the first input terminal of the in-phase delay unit electrically connected to the first input terminal of the in-phase delay unit constitutes the input terminal of the logic gate circuit of this level.

[0008] In one embodiment, the in-phase delay unit includes a NOT gate and a first NOR gate; The input terminal of the NOT gate constitutes the first input terminal of the in-phase delay unit and is electrically connected to the signal output terminal of the gate drive unit of this stage. The output terminal of the NOT gate is electrically connected to the first input terminal of the first NOR gate, and the second input terminal of the first NOR gate is electrically connected to the output terminal of the inverting delay unit. The output of the first NOR gate constitutes the output of the logic gate circuit of this level and is electrically connected to the neighboring pixel row.

[0009] In one embodiment, the inverting delay unit includes a buffer and a second NOR gate; The first end of the buffer constitutes the first input end of the inverting delay unit and is electrically connected to the signal output end of the gate drive unit of this stage. The second end of the buffer is electrically connected to the first input end of the second NOR gate, the second input end of the second NOR gate is electrically connected to the output end of the in-phase delay unit, and the output end of the second NOR gate forms the output end of the in-phase delay unit and is electrically connected to the low potential end.

[0010] Furthermore, this application also provides a control method for a gate driving circuit, the control method being applied to the gate driving circuit described above, the control method comprising: When the gate driving unit of the gate driving circuit provides a gate scan signal to the corresponding pixel row, the logic gate circuit of the current level is enabled to determine the adjacent level scan signal based on the gate scan signal. The logic gate circuit of the current level is a logic gate circuit that is configured corresponding to the gate driving unit of the current level. The neighboring pixel rows are scanned and driven according to the neighboring level scan signal, so that the number of gate driving units is half the number of pixel rows, wherein the neighboring pixel row is the next pixel row adjacent to the pixel row corresponding to the current level gate driving unit.

[0011] In one embodiment, the local logic gate circuit includes a non-inverting delay unit and an inverting delay unit, and the step of enabling the local logic gate circuit to determine the adjacent stage scan signal based on the gate scan signal includes: Enable the inverting delay unit to output an inverted output signal according to the gate scan signal; The in-phase delay unit and the out-of-phase delay unit are cross-coupled to enable the in-phase delay unit to perform delay processing based on the out-of-phase output signal and the gate scan signal to obtain the adjacent stage scan signal.

[0012] In addition, this application also provides a display panel, the display panel including: a display area; a non-display area, the non-display area being disposed around the periphery of the display area, the non-display area being provided with the gate driving circuit described above, the gate driving circuit being disposed on both sides of the display area.

[0013] In one embodiment, a plurality of pixel rows are arranged in the display area, wherein the pixel rows with odd numbers are odd-numbered pixel rows, and the pixel rows with even numbers are even-numbered pixel rows; The gate driving circuit located on one side of the display area is an odd-numbered row driving circuit that is electrically connected to all the odd-numbered pixel rows. The pixel row corresponding to the gate driving unit of the current level in the odd-numbered row driving circuit is the 4N-3rd pixel row, and the next pixel row adjacent to the pixel row corresponding to the gate driving unit of the current level in the odd-numbered row driving circuit is the 4N-1th pixel row, where N is a natural number. The gate driving circuit located on the other side of the display area is an even-numbered row driving circuit that is electrically connected to all even-numbered pixel rows; wherein, the pixel row corresponding to the gate driving unit of the even-numbered row driving circuit is the 4N-2th pixel row, and the next pixel row adjacent to the pixel row corresponding to the gate driving unit of the even-numbered row driving circuit is the 4Nth pixel row.

[0014] In one embodiment, the display panel is configured such that when the gate driving unit of the odd-numbered row driving circuit outputs a gate scan signal to drive the 4N-3 pixel row, the logic gate circuit corresponding to the gate driving unit in the odd-numbered row driving circuit delays the gate scan signal, and after the gate driving unit of the even-numbered row driving circuit completes the scanning drive of the 4N-2 pixel row, the delayed gate scan signal is used as the neighboring scanning signal to drive the 4N-1 pixel row.

[0015] In addition, this application also provides a display device, the display device including the display panel described above; and / or, a memory, a processor and a computer program stored in the memory and executable on the processor, the computer program implementing the steps of the control method of the gate drive circuit as described above when executed by the processor.

[0016] This application significantly reduces the risk of via corrosion by setting a gate drive circuit that includes multiple cascaded gate drive units and logic gate circuits located at the signal output terminals of each gate drive unit, thereby improving the display reliability of the display panel in high temperature and high humidity environments. Specifically, while the gate driving unit (i.e., any gate driving unit) provides a gate scan signal to the corresponding pixel row, the logic gate circuit corresponding to the gate driving unit determines the neighboring scanning signal based on the gate scan signal, and drives the next pixel row (i.e., the neighboring pixel row) adjacent to the corresponding pixel row through the neighboring scanning signal. This achieves scanning drive of two pixel rows by one gate driving unit. Since one gate driving unit can drive two pixel rows, the total number of gate driving units is only half the number of pixel rows, which greatly reduces the number of gate driving units used. The halving of the number of gate driving units directly leads to a corresponding halving of the number of vias penetrating the passivation layer, which reduces the probability of moisture intrusion and galvanic cell formation from the source. It effectively overcomes the problem of electrochemical corrosion caused by dense vias in the prior art, significantly reduces the risk of via corrosion in the gate driving circuit, enhances the reliability of the display panel in the dual 85 test, and thus ensures the display quality of the display panel in high temperature and high humidity environments. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a structural block diagram of the first embodiment of the gate drive circuit of this application; Figure 2 This is a schematic diagram of the gate driving unit circuit involved in the embodiments of this application; Figure 3 This is a schematic diagram showing the connection between the gate driving unit and the corresponding logic gate circuit involved in the embodiments of this application; Figure 4 This is a schematic diagram of the signal timing waveform involved in the embodiment of this application; Figure 5 This is a schematic diagram of the display panel involved in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the display device involved in the embodiments of this application.

[0020] Explanation of icon numbers: 100. Gate drive circuit; 10. Gate drive unit; 20. Logic gate circuit; 21. Non-inverting delay unit; 22. Inverting delay unit; VGL, low potential terminal; A0. Buffer; A1. NOT gate; B1. First NOR gate; B2. Second NOR gate; 1001. Processor; 1002. Communication bus; 1003. User interface; 1004. Network interface; 1005. Memory.

[0021] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0024] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0026] As the consumer electronics market continues to demand higher reliability from mobile terminal devices, products such as mobile phones and tablets must undergo a series of stringent environmental reliability tests before leaving the factory. Among these tests, the high-temperature and high-humidity operation test (i.e., the dual 85 test, temperature 85℃ / humidity 85%) is a key indicator for evaluating the stability of the screen under extreme conditions. During the dual 85 test, the GDL (Gate Driver on Array) circuit area inside the display panel is highly susceptible to via corrosion, which can lead to display abnormalities such as horizontal lines and other defects.

[0027] Currently, the GDL circuitry in panels requires extensive use of vias to achieve electrical connections between different metal layers (such as the first and second metal layers) and the ITO (Indium Tin Oxide) thin film. Because the PAS (Passivation Layer) in the via area is etched open to expose the metal, external moisture can easily penetrate the panel's interior under high temperature and humidity conditions. Simultaneously, residual chemicals such as H3PO4, HNO3, and CH3COOH from the etching process combine with moisture and react with metal ions (such as Cu). 2+The via forms an electrolyte solution, which makes the via area a natural galvanic cell due to its multi-layered metal stacked structure. Under the accelerated action of high temperature, the metal layers are rapidly electrochemically corroded. Once via corrosion occurs, it will cause abnormal driving waveforms input to the pixel area, ultimately manifesting as display defects such as horizontal lines on the screen.

[0028] Therefore, how to effectively reduce the number of vias in GDL circuits and reduce the risk of corrosion of vias in high temperature and high humidity environments, thereby improving the reliability and display uniformity of the display panel in the dual 85 test, is a technical problem that urgently needs to be solved.

[0029] To address the aforementioned technical deficiencies, this application provides a gate driving circuit and its control method, a display panel, and a display device.

[0030] This application provides a gate driving circuit 100, referring to... Figure 1 As shown, Figure 1 This is a structural block diagram of the first embodiment of the gate driving circuit 100 of this application. The gate driving circuit 100 provided in this application includes: Multiple cascaded gate driving units 10, one gate driving unit 10 corresponding to one pixel row, the current gate driving unit is configured to provide a gate scan signal Gout to the corresponding pixel row, and the current gate driving unit is any one of the multiple gate driving units 10.

[0031] In this embodiment, by setting multiple gate driving units 10 in a cascaded structure and making each gate driving unit 10 uniquely correspond to a pixel row, the row-by-row scanning driving of each row of pixels on the display panel is realized. This provides a basic timing control framework for the normal image display of the display panel, enabling each pixel row to be turned on sequentially according to a preset row scanning order. This ensures the accurate writing of the display signal and avoids display timing disorder caused by multiple pixel rows being turned on simultaneously, laying a reliable logical foundation for subsequent refined driving design.

[0032] It should be noted that the gate driving unit 10 is a basic component of the gate driving circuit 100 integrated on the array substrate, used to generate and output the gate scan signal Gout. This gate driving unit 10 can be composed of... Figure 2 The diagram shows multiple thin-film transistors Ti and capacitor C1, which can also be customized according to application requirements. This application does not impose any restrictions here.

[0033] Cascading refers to the connection method between multiple gate driving units 10, that is, the gate scan signal Gout output by the previous stage gate driving unit 10 is used as the input trigger signal of the next stage gate driving unit 10; the current stage gate driving unit refers to any one of the multiple cascaded gate driving units 10.

[0034] Logic gate circuits 20 are distributed at the signal output terminals of each gate driving unit 10. The logic gate circuit 20 corresponding to the gate driving unit of the current level is the logic gate circuit of the current level. The input terminal of the logic gate circuit of the current level is electrically connected to the signal output terminal of the gate driving unit of the current level, and the output terminal of the logic gate circuit of the current level is electrically connected to the neighboring pixel row. The logic gate circuit 20 is configured to determine the neighboring level scan signal based on the gate scan signal Gout output by the gate driving unit of the current level, and to scan and drive the neighboring pixel row through the neighboring level scan signal, so that the number of gate driving units 10 is half the number of pixel rows; wherein, the neighboring pixel row is the next pixel row adjacent to the pixel row corresponding to the gate driving unit of the current level.

[0035] In this embodiment, by setting logic gate circuits 20 at the signal output terminals of each level of gate driving unit 10, and electrically connecting the signal output terminal of each gate driving unit 10 to the corresponding pixel row, the signal output terminal of each gate driving unit 10 is also electrically connected to the neighboring pixel row (i.e., the next pixel row adjacent to the corresponding pixel row) through the logic gate circuit 20. This realizes the driving control of two adjacent rows of pixels by a single gate driving unit 10. Through the above-mentioned circuit connection structure, the number of gate driving units 10 is reduced to half the number of pixel rows, which significantly reduces the via density in the gate driving circuit 100. This significantly reduces the potential risks of water vapor intrusion and galvanic cell effect in high temperature and high humidity environments, effectively improving the corrosion resistance reliability and long-term stability of the display panel in the dual 85 test. At the same time, halving the number of gate driving units 10 releases valuable layout space around the array substrate, allowing the size of key transistors in the remaining gate driving units 10 to be optimized, enhancing the output driving capability of the gate driving circuit 100, thereby improving the charging efficiency in low temperature environments and the display uniformity of low-frequency refresh areas, ultimately improving the overall performance and product competitiveness of the display panel.

[0036] It should be noted that the neighboring pixel row refers to the next row of pixels adjacent to the pixel row corresponding to the current gate driving unit; the neighboring scan signal refers to the gate scan signal Gout generated by logic gate circuit 20 based on the current gate scan signal Gout, which is used to drive the neighboring pixel row.

[0037] For example, in a display panel with a resolution of 1920×1080, there are 1080 rows of pixels, while the number of gate driving units 10 is only 540. Taking the Nth level gate driving unit 10 (corresponding to the Nth row of pixels) as an example, the gate scan signal Gout(n) output by the gate driving unit 10 is directly connected to the gate line of the Nth row of pixels, thereby driving the thin film transistor of the Nth row of pixels to turn on. On the other hand, it is connected to the input terminal of the logic gate circuit of this level, so that the neighboring level scan signal PH1 generated by the logic gate circuit 20 according to the gate scan signal Gout(N) can be applied to the N+1th row of pixels (i.e., the neighboring pixel row) to drive the thin film transistor of the N+1th row of pixels to turn on. Thus, scanning and driving of two adjacent rows of pixels can be achieved by one gate driving unit 10 and one logic gate circuit 20. Similarly, 540 gate driving units 10, together with 540 logic gate circuits 20, can fully drive all 1080 rows of pixels, achieving the design goal of halving the number of gate driving units 10 and halving the number of vias, effectively reducing the risk of via corrosion in high temperature and high humidity environments, and improving the reliability and display uniformity of the panel.

[0038] Furthermore, in some other feasible embodiments, reference is made to... Figure 3 The logic gate circuit of this level includes: a non-inverting delay unit 21, an inverting delay unit 22, and a low-potential terminal VGL; the first input terminal of the non-inverting delay unit 21 is electrically connected to the signal output terminal of the gate driving unit of this level, the second input terminal of the non-inverting delay unit 21 is electrically connected to the output terminal of the inverting delay unit 22, and the output terminal of the non-inverting delay unit 21 constitutes the output terminal of the logic gate circuit of this level and is electrically connected to the neighboring pixel row; the first input terminal of the inverting delay unit 22 is electrically connected to the signal output terminal of the gate driving unit of this level, the second input terminal of the inverting delay unit 22 is electrically connected to the output terminal of the non-inverting delay unit 21, and the output terminal of the inverting delay unit 22 is electrically connected to the low-potential terminal VGL; the first input terminal of the non-inverting delay unit 21 is electrically connected to the first input terminal of the inverting delay unit 22, and the connection node between the first input terminal of the non-inverting delay unit 21 and the first input terminal of the inverting delay unit 22 constitutes the input terminal of the logic gate circuit of this level.

[0039] In this embodiment, the logic gate circuit of this level is configured to be composed of... Figure 3The cross-coupled structure formed by the in-phase delay unit 21 and the out-of-phase delay unit 22, and the introduction of a low-potential terminal VGL, realizes precise timing transformation and signal allocation of the gate scan signal Gout output by the gate drive unit of this stage. Specifically, the neighboring scan signal PH1 output by the in-phase delay unit 21 has the same waveform as the original gate scan signal Gout but is delayed by a preset delay period, thus ensuring that neighboring pixel rows can be opened within the correct timing window. Simultaneously, the signal PH2 output by the out-of-phase delay unit 22, which is inversely phase to the neighboring scan signal PH1, is connected to the low-potential terminal VGL, providing a stable potential reference for the cross-coupled structure and ensuring the stability of the logic gate circuit's operating state. Furthermore, through this cross-coupling structure, the logic gate circuit at this level can achieve the synchronous generation of one in-phase delayed drive signal (i.e., adjacent scan signal PH1) and one inverted reference signal (i.e., signal PH2) using a simple combination of logic gates. This avoids complex timing circuit design, reduces circuit layout complexity, further reduces the number of vias, and improves the reliability and corrosion resistance of the gate drive circuit 100 in high temperature and high humidity environments. Ultimately, it realizes the function of driving two adjacent rows of pixels through a single gate drive unit 10.

[0040] It should be noted that, Figures 2 to 3 The signals LC1 and LC2 shown are a pair of AC control signals with opposite phases that operate alternately. Essentially, signals LC1 and LC2 are inter-stage reset signals used to reset the internal node states of the gate drive unit 10. That is, signals LC1 and LC2 operate periodically at a frame rate, completing one complete alternation cycle per frame refresh. The specific switching frequency is related to the refresh rate of the display panel. For example, when the display panel operates at a 180Hz refresh rate, LC1 and LC2 alternate once per frame, completing 180 complete phase alternation cycles per second.

[0041] Figures 2 to 3 The signal Total Reset shown is a global reset signal between frames, which periodically acts on the reset thin-film transistors of each gate drive unit 10 at the frame rate. For example, the signal Total Reset generates a forced reset pulse before the start of each frame scan (usually during the vertical blanking period), which globally resets all critical nodes (such as pull-up nodes Q) inside all gate drive units 10 in one go, forcibly discharging residual charge to the initial state, ensuring that the scan of the new frame starts from a pure zero state, and avoiding cascading errors caused by residual signals from the previous frame interfering with the timing of the next frame.

[0042] Furthermore, it should be noted that each gate driving unit 10 can also output... Figure 4The auxiliary trigger signal Cout shown is consistent with the waveform of the gate scan signal Gout. This auxiliary trigger signal Cout can be used to provide a reset signal to the previous stage gate driving unit 10 and / or to the next stage gate driving unit 10, thereby effectively reducing the single-node load of the gate scan signal Gout, reducing the rise / fall time of the output waveform of the gate scan signal Gout, and making the gate scan signal Gout input to the pixel area steeper and more stable, thereby improving the charging uniformity.

[0043] The adjacent scan signal PH1 output by the in-phase delay unit 21 in each logic gate circuit 20 is consistent with the waveform of the gate scan signal Gout output by the corresponding gate drive unit 10, only shifted backward in time. Figure 4 The preset delay period T0 is shown. This delay period T0 is determined based on the gate driving architecture of the display panel.

[0044] For example, when the display panel uses only one gate driving circuit 100 for progressive scan driving, the time interval between the activation of two adjacent rows of pixels is one horizontal time period T. That is, the delay period of the adjacent scan signal PH1 relative to the gate scan signal Gout is one horizontal time period T. This ensures that, under the single-sided driving architecture, the logic gate circuit 20 can accurately match the progressive scan timing to achieve accurate driving of neighboring pixel rows. When the display panel uses two gate driving circuits 100 for interleaved scan driving, the time interval between the activation of the pixel row electrically connected to each gate driving unit 10 in each gate driving circuit 100 and the next pixel row is two horizontal time periods T. That is, the delay period of the adjacent scan signal PH1 relative to the gate scan signal Gout is two horizontal time periods T, to match the timing requirements of bilateral interleaved driving. In other words, the design of this application based on the gate driving architecture with flexible configuration of delay periods can be compatible with various display panel driving modes and achieve precise timing control of two adjacent rows of pixels by a single gate driving unit 10 in the gate driving circuit 100.

[0045] Furthermore, in some feasible embodiments, the in-phase delay unit 21 includes a NOT gate A1 and a first NOR gate B1; the input terminal of the NOT gate A1 constitutes the first input terminal of the in-phase delay unit 21 and is electrically connected to the signal output terminal of the gate driving unit of this stage; the output terminal of the NOT gate A1 is electrically connected to the first input terminal of the first NOR gate B1, and the second input terminal of the first NOR gate B1 is electrically connected to the output terminal of the inverting delay unit 22; the output terminal of the first NOR gate B1 constitutes the output terminal of the logic gate circuit of this stage and is electrically connected to the neighboring pixel row.

[0046] In this embodiment, by combining NOT gate A1 and the first NOR gate B1, and in conjunction with the cross-coupled feedback structure formed by the inverting delay unit 22, the gate scan signal Gout is delayed by a preset delay period T0 to generate a neighboring scan signal PH1 with the same waveform. Specifically, the gate scan signal Gout is inverted by NOT gate A1 to obtain an inverted signal Gout_A1, which is input to the first input terminal of the first NOR gate B1, while the second input terminal of the first NOR gate B1 receives the signal PH2 output from the inverting delay unit 22. Next, the first NOR gate B1 generates a neighboring scan signal PH1 with a delay period T0 and the same waveform as the gate scan signal Gout based on the logical operation of the inverted signal Gout_A1 and the signal PH2, thereby ensuring that the neighboring pixel row can be stably opened within the correct timing window. Meanwhile, the in-phase delay unit 21 is composed of only basic logic gate units, with a simple circuit topology that is easy to integrate on the array substrate. It does not require the introduction of complex timing control modules, effectively reducing the complexity of the gate drive circuit 100 layout, reducing the number of wiring and vias used, thereby improving the reliability and corrosion resistance of the gate drive circuit 100 in high temperature and high humidity environments.

[0047] It should be noted that the logic operation characteristic of the first NOR gate B1 can be understood as outputting 1 when all inputs are 0, and outputting 0 when all inputs are 1. That is, when either input of the first NOR gate B1 is high, the output of the first NOR gate B1 is low; only when both inputs of the first NOR gate B1 are low simultaneously, the output of the first NOR gate B1 is high.

[0048] For example, when the gate scan signal Gout is high, the inverted signal Gout_A1 obtained after inversion by NOT gate A1 is low. This inverted signal Gout_A1 is connected to the first input terminal of the first NOR gate B1. Since signal PH2 is connected to VGL, regardless of the level state of signal PH2 in the actual circuit, the level connected to the second input terminal of the first NOR gate B1 is always low. At this time, since both inputs of the first NOR gate B1 are low, according to the logic characteristic of all 0s outputting 1, the output terminal of the first NOR gate B1 outputs a high level, that is, the adjacent scan signal PH1 is high, which is consistent with the high level of the gate scan signal Gout.

[0049] When the gate scan signal Gout is low, the inverted signal Gout_A1, obtained after inversion by NOT gate A1, is high and connected to the first input of the first NOR gate B1. Similarly, since the signal PH2 is connected to the low-level terminal VGL, the second input of the first NOR gate B1 remains low. At this time, the two inputs of the first NOR gate B1 are high and low, respectively. According to the logic characteristic of 1 for 0, the adjacent scan signal PH1 output by the first NOR gate B1 is low, consistent with the low level of the gate scan signal Gout.

[0050] Therefore, with the signal PH2 connected to the low-potential terminal VGL, the first NOR gate B1, through its logic characteristic of "all 0s output 1, any 1 outputs 0," successfully inverts the signal after it has been inverted by the NOT gate A1, thus recovering the adjacent scan signal PH1, which has the same waveform as the gate scan signal Gout. The delay period T0 of the adjacent scan signal PH1 relative to Gout is accumulated by the propagation delay of the gate scan signal Gout as it passes through the NOT gate A1 and the first NOR gate B1. For example, in a single-sided driving architecture, the preset delay period T0 is one horizontal time period T. In this case, the propagation delay of NOT gate A1 can be designed to be 0.5T, and the propagation delay of the first NOR gate B1 can also be designed to be 0.5T, with the sum being 1T. Alternatively, other combinations can be used to achieve a total delay of 1T. In a double-sided interleaved driving architecture, the preset delay period T0 is two horizontal time periods T. Therefore, the propagation delay of NOT gate A1 can be designed to be 1T, and the propagation delay of the first NOR gate B1 can also be designed to be 1T. Alternatively, other combinations can be used to achieve a total delay of 2T. This delay control method based on the propagation delay of basic logic gates allows the in-phase delay unit 21 to flexibly adapt to different gate driving architectures, providing a precise timing basis for a single gate driving unit 10 to drive two rows of pixels.

[0051] Furthermore, in some other feasible embodiments, the inverting delay unit 22 includes a buffer A0 and a second NOR gate B2; the first end of the buffer A0 constitutes the first input terminal of the inverting delay unit 22 and is electrically connected to the signal output terminal of the gate driving unit of this stage; the second end of the buffer A0 is electrically connected to the first input terminal of the second NOR gate B2, the second input terminal of the second NOR gate B2 is electrically connected to the output terminal of the non-inverting delay unit 21, and the output terminal of the second NOR gate B2 constitutes the output terminal of the inverting delay unit 22 and is electrically connected to the low potential terminal VGL.

[0052] In this embodiment, by configuring the inverting delay unit 22 as a circuit structure composed of buffer A0 and a second NOR gate B2, and combining it with the cross-coupled feedback formed with the non-inverting delay unit 21, the inversion of the input gate scan signal Gout is achieved and stably connected to the low-potential terminal VGL. Specifically, the gate scan signal Gout is processed by buffer A0 to obtain the signal Gout_A0, which is input to the first input terminal of the second NOR gate B2; the second input terminal of the second NOR gate B2 receives the adjacent scan signal PH1 output from the non-inverting delay unit 21; the second NOR gate B2 performs NOR operation on the two inputs and outputs the signal PH2, which is inverted by the gate scan signal Gout, and connects the inverted signal PH2 to the low-potential terminal VGL, ensuring that the output of the inverting delay unit 22 is stably pulled down to a low potential, providing an accurate feedback reference for the non-inverting delay unit 21. At the same time, the signal waveform quality is optimized by buffer A0, making the timing relationship of the entire logic gate circuit 20 more accurate.

[0053] For example, when the gate scan signal Gout is high, after processing by buffer A0, Gout_A0 is input as a high level to the first input of the second NOR gate B2; at this time, the adjacent scan signal PH1 output by the in-phase delay unit 21 is high (as mentioned before, PH1 is high when Gout is high), and is input to the second input of the second NOR gate B2. Both inputs of the second NOR gate B2 are high. According to the logic characteristic of NOR gate A1 (1 outputs 0), the signal PH2 output by the second NOR gate B2 is low, which is consistent with the requirement of connecting to the low potential terminal VGL. When the gate scan signal Gout is low, the signal Gout_A0 is low, and the adjacent scan signal PH1 is low (as mentioned earlier, PH1 is low when Gout is low). Both inputs of the second NOR gate B2 are low. According to the logic characteristic of NOR gate A1 (all 0s, one output), the output signal PH2 of the second NOR gate B2 is high. However, since the output of the second NOR gate B2 is directly connected to the low-potential terminal VGL, the high-level signal PH2 output by the second NOR gate B2 is forcibly pulled low by the low-potential terminal VGL, ensuring that the node of signal PH2 is always in a stable low-level state. This provides a stable low-level feedback reference for the in-phase delay unit 21, enabling the entire cross-coupled structure to continuously generate the accurate adjacent scan signal PH1. In addition, the introduction of buffer A0 enhances the signal driving capability and optimizes the waveform quality, reduces distortion and noise interference during signal transmission, and further improves the anti-interference capability and working stability of the circuit in high temperature and high humidity environments. Meanwhile, the inverting delay unit 22 is composed of only basic logic gate units, with a simple circuit topology that is easy to integrate on the array substrate, effectively reducing the complexity of the gate drive circuit 100 layout and reducing the number of wiring and vias used.

[0054] In summary, by setting up a gate drive circuit 100 that includes multiple cascaded gate drive units 10 and logic gate circuits 20 disposed at the signal output terminals of each gate drive unit 10, this application significantly reduces the risk of via corrosion, thereby improving the display reliability of the display panel in high temperature and high humidity environments. Specifically, while the gate driving unit (i.e., any gate driving unit 10) provides the gate scan signal Gout to the corresponding pixel row, the logic gate circuit corresponding to the gate driving unit determines the neighboring scan signal based on the gate scan signal Gout, and drives the next pixel row (i.e., the neighboring pixel row) adjacent to the corresponding pixel row through the neighboring scan signal. This realizes that one gate driving unit 10 can drive two pixel rows. Since one gate driving unit 10 can drive two pixel rows, the total number of gate driving units 10 is only half the number of pixel rows, which greatly reduces the number of gate driving units 10 used. The halving of the number of gate driving units 10 directly leads to a corresponding halving of the number of vias penetrating the passivation layer, which reduces the probability of moisture intrusion and galvanic cell formation from the source. It effectively overcomes the problem of electrochemical corrosion caused by dense vias in the prior art, significantly reduces the risk of via corrosion of the gate driving circuit 100, enhances the reliability of the display panel in the dual 85 test, and thus ensures the display quality of the display panel in high temperature and high humidity environment.

[0055] Furthermore, based on the first embodiment of the gate drive circuit 100 of this application, a second embodiment of the control method of the gate drive circuit 100 of this application is proposed.

[0056] The control method of the gate driving circuit 100 of this application is applied to the gate driving circuit 100 described above. The control method of the gate driving circuit 100 of this application is executed by a display device applied to the gate driving circuit 100. The control method of the gate driving circuit 100 of this application includes the following implementation steps S10 to S20.

[0057] Step S10: When the local gate driving unit in the gate driving circuit 100 provides the gate scan signal Gout to the corresponding pixel row, the local logic gate circuit is enabled to determine the neighboring scan signal based on the gate scan signal Gout. The local logic gate circuit is a logic gate circuit 20 corresponding to the local gate driving unit.

[0058] In this embodiment, when the current gate driving unit starts working in response to the output of the previous gate driving unit 10, the gate scan signal Gout output by the current gate driving unit can be directly transmitted to the corresponding pixel row of the current stage, thereby driving the thin film transistor of the pixel in that row to turn on; or the gate scan signal Gout can be input to the logic gate circuit of the current stage as the input source for the logic gate circuit of the current stage to generate the adjacent stage scan signal. At this time, after receiving the gate scan signal Gout, the in-phase delay unit 21 (i.e., NOT gate A1 and first NOR gate B1) set inside the logic gate circuit performs logic transformation and timing processing on the gate scan signal Gout. That is, the gate scan signal Gout is first inverted by NOT gate A1 to obtain the inverted signal Gout_A1, which is input to the first input terminal of the first NOR gate B1. The second input terminal of the first NOR gate B1 receives the output signal PH2 from the inverting delay unit 22. Since the signal PH2 is connected to the low potential terminal VGL and is always at a low level, the first NOR gate B1 is actually working in the in-phase buffer A0 mode. Thus, the output of the first NOR gate B1 is the neighboring scan signal PH1 with the same waveform as the gate scan signal Gout but with a preset delay period T0. This achieves accurate delay copying of the gate scan signal Gout and provides a timing-accurate scan drive signal for driving the neighboring pixel row.

[0059] Step S20: Scan and drive the neighboring pixel rows according to the neighboring level scan signal, so that the number of gate driving units 10 is half the number of pixel rows, wherein the neighboring pixel row is the next pixel row adjacent to the pixel row corresponding to the current level gate driving unit.

[0060] In this embodiment, the neighboring scan signal PH1 generated by the local logic gate circuit is transmitted to the gate line of the neighboring pixel row to drive the thin-film transistors of each pixel in the neighboring pixel row to turn on. Since the neighboring scan signal PH1 has the same waveform as the gate scan signal Gout, only delayed by a preset delay period T0 in timing, the neighboring pixel row can be stably turned on within the correct timing window, forming a precise match with the scanning timing of the corresponding pixel row. This allows one local gate driving unit and one local logic gate circuit to drive two adjacent rows of pixels. The pixel row corresponding to the local gate driving unit is directly driven by the gate scan signal Gout, while the neighboring pixel row is indirectly driven by the neighboring scan signal PH1. Similarly, in a display panel containing M rows of pixels, only M / 2 gate driving units 10 and M / 2 local logic gates are needed to complete the row-by-row scanning drive of all pixel rows. This reduces the number of gate driving units 10 to half the number of pixel rows, thereby significantly reducing the number of vias used in the gate driving circuit 100 while achieving basic scanning functions. This reduces the risk of moisture intrusion and galvanic effect formation under high temperature and high humidity environments, effectively improving the corrosion resistance, reliability, and long-term stability of the display panel.

[0061] Furthermore, in some other feasible embodiments, the local logic gate circuit includes an in-phase delay unit 21 and an in-phase delay unit 22. The above step S10: enabling the local logic gate circuit to determine the neighboring stage scan signal according to the gate scan signal Gout may also include the following implementation steps S101 to S102.

[0062] Step S101: Enable the inverting delay unit 22 to output an inverted output signal according to the gate scan signal Gout.

[0063] In this embodiment, by configuring the inverting delay unit 22 as a circuit structure composed of buffer A0 and a second NOR gate B2, and combining it with the cross-coupled feedback formed with the non-inverting delay unit 21, the inversion of the input gate scan signal Gout is achieved and stably connected to the low-potential terminal VGL. Specifically, the gate scan signal Gout is processed by buffer A0 to obtain the signal Gout_A0, which is input to the first input terminal of the second NOR gate B2; the second input terminal of the second NOR gate B2 receives the adjacent scan signal PH1 output from the non-inverting delay unit 21; the second NOR gate B2 performs NOR operation on the two inputs and outputs the signal PH2, which is inverted by the gate scan signal Gout, and connects the inverted signal PH2 to the low-potential terminal VGL, ensuring that the output of the inverting delay unit 22 is stably pulled down to a low potential, providing an accurate feedback reference for the non-inverting delay unit 21. At the same time, the signal waveform quality is optimized by buffer A0, making the timing relationship of the entire logic gate circuit 20 more accurate.

[0064] Step S102: Through the cross-coupling connection of the in-phase delay unit 21 and the inverting delay unit 22, the in-phase delay unit 21 is enabled to perform delay processing based on the inverting output signal and the gate scan signal Gout to obtain the adjacent stage scan signal.

[0065] In this embodiment, by combining NOT gate A1 and the first NOR gate B1, and in conjunction with the cross-coupled feedback structure formed by the inverting delay unit 22, the gate scan signal Gout is delayed by a preset delay period T0 to generate a neighboring scan signal PH1 with the same waveform. Specifically, the gate scan signal Gout is inverted by NOT gate A1 to obtain the inverted signal Gout_A1, which is input to the first input terminal of the first NOR gate B1, while the second input terminal of the first NOR gate B1 receives the signal PH2 output from the inverting delay unit 22. The signal PH2 output by the inverting delay unit 22 is always low because it is connected to the low potential terminal VGL, which makes the first NOR gate B1 actually work in the non-inverting buffer A0 mode. When the gate scan signal Gout is high, it is inverted by NOT gate A1 to obtain a low-level signal Gout_A1. Both inputs of the first NOR gate B1 are low. According to the logic characteristic of NOR gate A1 (all 0s output 1), the first NOR gate B1 outputs a high-level neighbor scan signal PH1. When the gate scan signal Gout is low, it is inverted by NOT gate A1 to obtain a high-level signal Gout_A1. The two inputs of the first NOR gate B1 are connected to low and high levels respectively. According to the logic characteristic of NOR gate A1 (one 1 output 0), it outputs a low-level gate scan signal GoutPH1. Thus, the first NOR gate B1 successfully recovers the neighbor scan signal PH1, which has the same waveform as the gate scan signal Gout. The delay period T0 is accumulated by the propagation delay of the gate scan signal Gout through NOT gate A1 and the first NOR gate B1, thereby ensuring that the neighboring pixel row can be stably opened within the correct timing window. Meanwhile, the in-phase delay unit 21 is composed of only basic logic gate units, with a simple circuit topology that is easy to integrate on the array substrate. It does not require the introduction of complex timing control modules, effectively reducing the complexity of the gate drive circuit 100 layout, reducing the number of wiring and vias used, thereby improving the reliability and corrosion resistance of the gate drive circuit 100 in high temperature and high humidity environments.

[0066] In addition, this application also provides a display panel, as shown in the reference. Figure 5 The display panel includes: a display area; a non-display area, the non-display area being disposed around the periphery of the display area, and the non-display area being provided with a gate driving circuit 100 as described in any one of claims 1 to 4, the gate driving circuit 100 being disposed on both sides of the display area.

[0067] In this embodiment, by distributing the gate driving circuits 100 on both sides of the display area, a dual-sided driving layout for the display panel is achieved, effectively reducing the load pressure of single-sided driving and optimizing the uniformity of scan signal transmission. Specifically, each gate driving unit 10 in the gate driving circuit 100, in conjunction with a corresponding logic gate circuit 20, enables a single gate driving unit 10 to drive two rows of pixels, thereby further reducing the number of vias in the dual-sided driving layout and improving the corrosion resistance and reliability of the display panel. Simultaneously, the dual-sided driving layout allows the gate scan signal Gout to be transmitted simultaneously from both sides to the center, shortening the signal transmission distance, reducing RC (resistance-capacitance) delay, and improving display uniformity.

[0068] It should be noted that the display area refers to the area in the display panel actually used for image display, which consists of pixel rows and pixel columns distributed in an array; the non-display area refers to the peripheral area outside the display area, which is used to arrange the gate driving circuit 100 and the driver chip bonding area and other peripheral circuits; the gate driving circuit 100 is located on both sides of the display area, and can be symmetrically arranged (such as the left and right sides) or on the top and bottom sides, depending on the panel design requirements.

[0069] For example, if the display area of ​​the display panel contains 1080 rows of pixels, an odd-numbered row driving circuit is provided on the left side of the non-display area near the display area, and an even-numbered row driving circuit is provided on the right side of the non-display area near the display area. The odd-numbered row driving circuit includes 270 gate driving units 10 and corresponding logic gate circuits 20. Each gate driving unit 10 drives one row of odd-numbered pixels and its adjacent next row of odd-numbered pixels (such as row 1 and row 3, row 3 and row 5, and so on), driving a total of 540 rows of odd-numbered pixels. The even-numbered row driving circuit also includes 270 gate driving units 10 and corresponding logic gate circuits 20. Each gate driving unit 10 drives one row of even-numbered pixels and its adjacent next row of even-numbered pixels (such as row 2 and row 4, row 4 and row 6, and so on), driving a total of 540 rows of even-numbered pixels. This bilateral symmetrical layout completely covers all 1080 rows of pixels in the display area. Each side gate driving circuit 100 requires only 270 gate driving units 10, for a total of 540 gate driving units 10 on both sides. Compared to the traditional design with 1080 gate driving units 10 on one side, the number of vias is reduced by half, significantly improving the display panel's corrosion resistance in high-temperature and high-humidity environments. Simultaneously, because the gate scan signal Gout is transmitted from both sides towards the center, the maximum transmission distance is only half the width of the display area, effectively reducing the RC delay of signal transmission and improving display uniformity.

[0070] Furthermore, in some other feasible embodiments, a plurality of pixel rows are arranged in the display area, wherein the pixel rows with odd-numbered sequences are odd-numbered pixel rows, and the pixel rows with even-numbered sequences are even-numbered pixel rows; the gate driving circuit 100 disposed on one side of the display area is an odd-numbered row driving circuit electrically connected to all the odd-numbered pixel rows, wherein the pixel row corresponding to the current gate driving unit in the odd-numbered row driving circuit is the 4N-3rd pixel row, and the next pixel row adjacent to the pixel row corresponding to the current gate driving unit in the odd-numbered row driving circuit is the 4N-1th pixel row, where N is a natural number; the gate driving circuit 100 disposed on the other side of the display area is an even-numbered row driving circuit electrically connected to all the even-numbered pixel rows; wherein the pixel row corresponding to the current gate driving unit in the even-numbered row driving circuit is the 4N-2th pixel row, and the next pixel row adjacent to the pixel row corresponding to the current gate driving unit in the even-numbered row driving circuit is the 4Nth pixel row.

[0071] In this embodiment, by precisely controlling the timing coordination between the odd-row driving circuit and the even-row driving circuit, interleaved scanning driving is achieved, ensuring that each row of pixels can be turned on within the correct timing window. Specifically, the gate driving unit of the odd-row driving circuit first outputs the gate scan signal Gout, which directly drives the 4N-3 row of pixels to turn on; at the same time, the gate scan signal Gout is input to the logic gate circuit of the same stage, and after being delayed by the in-phase delay unit 21 for a preset delay period T0, the adjacent stage scan signal PH1 is generated. The delay period T0 is set to be exactly equal to the time required for the even-numbered row driving circuit to scan the 4N-2th row. That is, after the gate driving unit of the even-numbered row driving circuit completes the driving of the 4N-2th row, the adjacent scanning signal PH1 of the odd-numbered row driving circuit arrives at the 4N-1th row, turning on the pixels of the 4N-1th row. This makes the entire pixel row scanning process of the display area form an alternating timing of "odd row - even row - next odd row - next even row", avoiding overlap or gaps between rows and ensuring the continuity and stability of the image.

[0072] It should be noted that the delay period T0 must be set to match the timing of the dual-sided interleaved drive. In the dual-sided drive architecture, since odd and even rows are driven independently by the gate drive circuits 100 on both sides, the time interval between the activation of two adjacent rows of pixels in the display area (such as rows 4N-3 and 4N-2) is usually one horizontal time period T. However, within the odd-numbered row drive circuit, adjacent rows (such as rows 4N-3 and 4N-1) are spaced two horizontal time periods T apart (because an even-numbered row is inserted in the middle). Therefore, the logic gate circuit at this level in the odd-numbered row drive circuit needs to delay the gate scan signal Gout by 2T to drive the next odd-numbered pixel row; similarly, the logic gate circuit at this level in the even-numbered row drive circuit also needs to delay by 2T to drive the next even-numbered pixel row. With this timing configuration, the scanning order of the entire display panel can be: row 1 (odd) → row 2 (even) → row 3 (odd) → row 4 (even)..., and so on.

[0073] For example, in combination Figure 5 Assuming a horizontal time period of T, at time t0, the first-stage gate driving unit 10 of the odd-numbered row driving circuit outputs a high-level gate scan signal Gout_1, driving the first row of pixels to turn on. This gate scan signal Gout_1 is simultaneously input to the corresponding logic gate circuit 20, and after a delay of 2T, outputs a high-level neighbor scan signal PH1_1 at time t0+2T, driving the third row of pixels to turn on. At time t0+1T, the first-stage gate driving unit 10 of the even-numbered row driving circuit outputs a high-level gate scan signal Gout_2, driving the second row of pixels to turn on. This gate scan signal Gout_2 is simultaneously input to the corresponding logic gate circuit 20, and after a delay of 2T, outputs a high-level neighbor scan signal PH1_2 at time t0+3T, driving the fourth row of pixels to turn on. This cycle continues, and all pixel rows are turned on sequentially. Each gate driving unit 10 only needs to handle two pixel rows of the same parity, and the timing is completely guaranteed by the delay period of 2T, achieving efficient and reliable scan driving.

[0074] Furthermore, in some feasible embodiments, the display panel is configured such that when the gate drive unit of the odd-numbered row driving circuit outputs a gate scan signal Gout to drive the 4N-3 pixel row, the logic gate circuit corresponding to the gate drive unit in the odd-numbered row driving circuit delays the gate scan signal Gout, and after the gate drive unit of the even-numbered row driving circuit completes the scanning drive of the 4N-2 pixel row, the delayed gate scan signal Gout is used as the neighboring scan signal to drive the 4N-1 pixel row.

[0075] In this embodiment, by dividing the pixel rows into two groups according to their odd and even numbers, and driving each group independently by the gate driving circuits 100 on both sides, a bilateral interleaved driving architecture with separate odd and even rows is achieved. Specifically, Figure 5 In the odd-row driving circuit shown, each gate driving unit 10 corresponds to an odd-numbered pixel row (e.g., the 1st-level gate driving unit, the 2nd-level gate driving unit, the 3rd-level gate driving unit, the 4th-level gate driving unit, ..., the Nth-level gate driving unit correspond to the 1st row of pixels, the 5th row of pixels, the 9th row of pixels, the 13th row of pixels, ..., the 4N-3rd row of pixels, respectively), and drives the next adjacent odd-numbered pixel row (i.e., the 3rd row of pixels, the 7th row of pixels, the 11th row of pixels, the 15th row of pixels, ..., the 4N-1st row of pixels) through the corresponding logic gate circuit 20. Each gate driving unit 10 in the even-numbered row driving circuit corresponds to an even-numbered pixel row (such as the first-level gate driving unit, the second-level gate driving unit, the third-level gate driving unit, the fourth-level gate driving unit, ..., the Nth-level gate driving unit, which correspond to the second row of pixels, the sixth row of pixels, the tenth row of pixels, the fourteenth row of pixels, ..., the 4N-2th row of pixels, respectively), and drives the next even-numbered pixel row adjacent to the even-numbered pixel row (i.e., the fourth row of pixels, the eighth row of pixels, the twelfth row of pixels, the sixteenth row of pixels, ..., the 4Nth row of pixels) through the corresponding logic gate circuit 20.

[0076] It should be noted that N is a natural number (N=1,2,3,…) used to represent the number of levels of the gate driving unit 10. For odd-numbered row driving circuits, the pixel row corresponding to the Nth level gate driving unit 10 is the 4N-3th row (i.e., rows 1, 5, 9, 13…), and the neighboring pixel rows driven by the logic gate circuit 20 corresponding to the Nth level gate driving unit 10 are the 4N-1th row (i.e., rows 3, 7, 11, 15…). For even-numbered row driving circuits, the pixel row corresponding to the Nth level gate driving unit 10 is the 4N-2th row (i.e., rows 2, 6, 10, 14…), and the neighboring pixel rows driven by the logic gate circuit 20 corresponding to the Nth level gate driving unit 10 are the 4Nth row (i.e., rows 4, 8, 12, 16…). This ensures that the two sets of circuits for odd and even rows are completely symmetrical and do not interfere with each other, and that each pixel row is driven directly or indirectly by only one gate driving unit 10.

[0077] For example, in a display panel with 1080 rows of pixels, the value of N ranges from 1 to 540. In the odd-row driving circuit, when N=1, the current gate driving unit drives the first row of pixels, and the neighboring pixel row of the first row of pixels drives the third row of pixels; when N=2, the current gate driving unit drives the third row of pixels, and the neighboring pixel row of the third row of pixels drives the fifth row of pixels; and so on, until N=270, when the current gate driving unit drives the 1079th row of pixels. Since there are no odd-rows to drive after the 1079th row, the neighboring scan signal PH1 generated by the 270th level gate driving unit 10 in the odd-row driving circuit can be left floating in the actual design, or connected to a dummy (analog) pixel row load to maintain circuit symmetry and load consistency, and avoid signal reflection or waveform distortion caused by no load. In the even-numbered row driving circuit, when N=1, the gate driving unit of this stage drives the second row of pixels, and the neighboring pixel row of the second row of pixels is the fourth row of pixels; when N=2, the gate driving unit of this stage drives the sixth row of pixels, and the neighboring pixel row of the sixth row of pixels is the eighth row of pixels; and so on, until N=270, when the gate driving unit of this stage drives the 1078th row of pixels, and the neighboring pixel row of the 1078th row of pixels is the 1080th row of pixels.

[0078] In addition, this application also provides a display device. Please refer to... Figure 6 , Figure 6 This is a schematic diagram of the structure of a display device involved in an embodiment of this application. Specifically, the display device in this embodiment may be a device for controlling a locally running gate drive circuit.

[0079] The display device includes the gate driving circuit described above, and / or a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the control method for the gate driving circuit described above.

[0080] like Figure 6 As shown, the display device in this embodiment may include: a gate driving circuit, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0081] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk drive. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0082] Those skilled in the art will understand that Figure 6 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0083] like Figure 6 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a driver program for the gate drive circuit.

[0084] exist Figure 6 In the display device shown, the processor 1001 can be used to call the driver program of the gate drive circuit stored in the memory 1005 and execute the steps of the gate drive circuit control method as described above.

[0085] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0086] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0087] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0088] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes: Multiple cascaded gate driving units, one gate driving unit corresponds to one pixel row, and the current gate driving unit is configured to provide a gate scan signal to the corresponding pixel row. The current gate driving unit is any one of the multiple gate driving units. The logic gate circuits are distributed at the signal output terminals of each gate driving unit. The logic gate circuit corresponding to the gate driving unit of that level is called the local level logic gate circuit. The input terminal of the local level logic gate circuit is electrically connected to the signal output terminal of the gate driving unit of that level, and the output terminal of the local level logic gate circuit is electrically connected to the neighboring pixel row. The logic gate circuit is configured to determine the neighboring level scan signal based on the gate scan signal output by the local level gate driving unit, and to drive the neighboring pixel row to scan using the neighboring level scan signal, such that the number of gate driving units is half the number of pixel rows. The neighboring pixel row is the next pixel row adjacent to the pixel row corresponding to the gate driving unit of this level.

2. The gate driving circuit as described in claim 1, characterized in that, The logic gate circuit at this level includes: a non-inverting delay unit, an inverting delay unit, and a low-potential terminal; The first input terminal of the in-phase delay unit is electrically connected to the signal output terminal of the gate driving unit of the same level, the second input terminal of the in-phase delay unit is electrically connected to the output terminal of the inverting delay unit, and the output terminal of the in-phase delay unit constitutes the output terminal of the logic gate circuit of the same level and is electrically connected to the neighboring pixel row. The first input terminal of the inverting delay unit is electrically connected to the signal output terminal of the gate driving unit of the same stage, the second input terminal of the inverting delay unit is electrically connected to the output terminal of the non-inverting delay unit, and the output terminal of the inverting delay unit is electrically connected to the low potential terminal. The first input terminal of the in-phase delay unit is electrically connected to the first input terminal of the in-phase delay unit, and the connection point of the first input terminal of the in-phase delay unit electrically connected to the first input terminal of the in-phase delay unit constitutes the input terminal of the logic gate circuit of this level.

3. The gate driving circuit as described in claim 2, characterized in that, The in-phase delay unit includes a NOT gate and a first NOR gate; The input terminal of the NOT gate constitutes the first input terminal of the in-phase delay unit and is electrically connected to the signal output terminal of the gate drive unit of this stage. The output terminal of the NOT gate is electrically connected to the first input terminal of the first NOR gate, and the second input terminal of the first NOR gate is electrically connected to the output terminal of the inverting delay unit. The output of the first NOR gate constitutes the output of the logic gate circuit of this level and is electrically connected to the neighboring pixel row.

4. The gate driving circuit as described in claim 2, characterized in that, The inverting delay unit includes a buffer and a second NOR gate; The first end of the buffer constitutes the first input end of the inverting delay unit and is electrically connected to the signal output end of the gate drive unit of this stage. The second end of the buffer is electrically connected to the first input end of the second NOR gate, the second input end of the second NOR gate is electrically connected to the output end of the in-phase delay unit, and the output end of the second NOR gate forms the output end of the in-phase delay unit and is electrically connected to the low potential end.

5. A control method for a gate driving circuit, characterized in that, The control method is applied to the gate driving circuit according to any one of claims 1 to 4, and the control method includes: When the gate driving unit of the gate driving circuit provides a gate scan signal to the corresponding pixel row, the logic gate circuit of the current level is enabled to determine the adjacent level scan signal based on the gate scan signal. The logic gate circuit of the current level is a logic gate circuit that is configured corresponding to the gate driving unit of the current level. The neighboring pixel rows are scanned and driven according to the neighboring level scan signal, so that the number of gate driving units is half the number of pixel rows, wherein the neighboring pixel row is the next pixel row adjacent to the pixel row corresponding to the current level gate driving unit.

6. The control method as described in claim 5, characterized in that, The current-level logic gate circuit includes a non-inverting delay unit and an inverting delay unit. The step of enabling the current-level logic gate circuit to determine the adjacent-level scan signal based on the gate scan signal includes: Enable the inverting delay unit to output an inverted output signal according to the gate scan signal; The in-phase delay unit and the out-of-phase delay unit are cross-coupled to enable the in-phase delay unit to perform delay processing based on the out-of-phase output signal and the gate scan signal to obtain the adjacent stage scan signal.

7. A display panel, characterized in that, The display panel includes: Display area; A non-display area is provided around the periphery of the display area, and the non-display area is provided with a gate driving circuit as described in any one of claims 1 to 4, wherein the gate driving circuit is disposed on both sides of the display area.

8. The display panel as described in claim 7, characterized in that, The display area is provided with several pixel rows, where the pixel rows with odd numbers are odd-numbered and the pixel rows with even numbers are even-numbered. The gate driving circuit located on one side of the display area is an odd-numbered row driving circuit that is electrically connected to all the odd-numbered pixel rows. The pixel row corresponding to the gate driving unit of the current level in the odd-numbered row driving circuit is the 4N-3rd pixel row, and the next pixel row adjacent to the pixel row corresponding to the gate driving unit of the current level in the odd-numbered row driving circuit is the 4N-1th pixel row, where N is a natural number. The gate driving circuit located on the other side of the display area is an even-numbered row driving circuit that is electrically connected to all even-numbered pixel rows; wherein, the pixel row corresponding to the gate driving unit of the even-numbered row driving circuit is the 4N-2th pixel row, and the next pixel row adjacent to the pixel row corresponding to the gate driving unit of the even-numbered row driving circuit is the 4Nth pixel row.

9. The display panel as described in claim 8, characterized in that, The display panel is configured such that when the gate driving unit of the odd row driving circuit outputs a gate scan signal to drive the 4N-3 pixel row, the logic gate circuit corresponding to the gate driving unit in the odd row driving circuit delays the gate scan signal, and after the gate driving unit of the even row driving circuit completes the scanning drive of the 4N-2 pixel row, the delayed gate scan signal is used as the neighboring scanning signal to drive the 4N-1 pixel row.

10. A display device, characterized in that, The display device includes the display panel according to any one of claims 7 to 9; and / or, A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the control method for the gate drive circuit as described in any one of claims 5 to 6.

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