Lpddr5 memory system and data reception training circuit thereof

Abstract

The application discloses an LPDDR5 memory system and a data receiving training circuit thereof, and relates to the technical field of semiconductors.The LPDDR5 memory system comprises a comparator module and an amplifier module.The comparator module comprises four comparators, and the amplifier module comprises four sense amplifiers S / As which are connected to the four comparators in one-to-one correspondence.In a training mode, different reference voltages are connected to reference voltage input ends of at least two comparators in the four comparators, respectively, and the same clock signal is connected to clock input ends of S / As corresponding to the comparators with different reference voltages, respectively.The application improves the utilization efficiency of training information, thereby improving the training efficiency and the convergence speed and reducing the training time consumption.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an LPDDR5 memory system and its data receiving training circuit. Background Technology

[0002] In LPDDR5 (Low Power Double Data Rate 5 Synchronous Dynamic Random-Access Memory) storage systems, the data DQ signal is used to transmit high-speed read and write data, and its reception accuracy and training efficiency directly affect the system performance and stability.

[0003] Currently, LPDDR5 data receivers typically use a multi-phase clock in conjunction with a reference voltage to sample the input signal. For example... Figure 1 As shown, the four comparators in the receiving circuit are connected to the same reference voltage Ref, and the four sense amplifiers (S / A) are connected to different clock signals, such as WCK_0, WCK_90, WCK_180, and WCK_270. After the DQ signal is input to the receiving circuit, the comparator compares the DQ signal with the reference voltage to obtain preliminary level information. The comparison result is input to the sense amplifier (S / A) for regeneration and amplification, and latching is completed under the control of the corresponding clock, thereby realizing the conversion of serial data to parallel data.

[0004] However, the above-mentioned receiving training process requires the calibration of multiple phase clocks one by one, which increases the training complexity. Since each phase clock needs to participate in the training, the overall training process is quite lengthy and the training time is long. Furthermore, the results of sampling from different phase paths cannot be obtained in parallel at the same time, resulting in low efficiency in the utilization of training information and thus low training efficiency.

[0005] Therefore, how to improve the training efficiency of the receiving training circuit and reduce the training time is an urgent problem to be solved.

[0006] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0007] The main objective of this application is to provide an LPDDR5 memory system and its data receiving training circuit, aiming to solve the technical problem of how to improve the training efficiency of the receiving training circuit and reduce the training time.

[0008] To achieve the above objectives, the data receiving training circuit of the LPDDR5 memory system includes: a comparator module and an amplifier module; The comparator module includes four comparators, and the amplifier module includes four sense amplifiers S / A connected one-to-one with the four comparators. In training mode, different reference voltages are connected to the reference voltage input terminals of at least two of the four comparators, and the same clock signal is connected to the clock input terminals of the corresponding S / A of the comparators connected to different reference voltages.

[0009] In one embodiment, the comparator includes a first comparator, a second comparator, a third comparator, and a fourth comparator; the S / A includes a first S / A, a second S / A, a third S / A, and a fourth S / A. The output of the first comparator is connected to the data input of the first S / A, the output of the second comparator is connected to the data input of the second S / A, the output of the third comparator is connected to the data input of the third S / A, and the output of the fourth comparator is connected to the data input of the fourth S / A.

[0010] In one embodiment, the reference voltage input terminal of the first comparator is connected to a first reference voltage, and the clock input terminal of the first S / A is connected to a first clock signal; The reference voltage input terminal of the second comparator is connected to the first reference voltage, and the clock input terminal of the second S / A is connected to the second clock signal; The reference voltage input terminal of the third comparator is connected to the second reference voltage, and the clock input terminal of the third S / A is connected to the first clock signal; The reference voltage input terminal of the fourth comparator is connected to the second reference voltage, and the clock input terminal of the fourth S / A is connected to the second clock signal.

[0011] In one embodiment, the reference voltage input terminal of the first comparator is connected to a first reference voltage, and the clock input terminal of the first S / A is connected to a first clock signal; The reference voltage input terminal of the second comparator is connected to the first reference voltage, and the clock input terminal of the second S / A is connected to the second clock signal; The reference voltage input terminal of the third comparator is connected to the first reference voltage, and the clock input terminal of the third S / A is connected to the third clock signal; The reference voltage input terminal of the fourth comparator is connected to a second reference voltage, and the clock input terminal of the fourth S / A is connected to a first clock signal, a second clock signal, or a third clock signal.

[0012] In one embodiment, the reference voltage input terminal of the first comparator is connected to a first reference voltage, and the clock input terminal of the first S / A is connected to a first clock signal; The reference voltage input terminal of the second comparator is connected to the first reference voltage, and the clock input terminal of the second S / A is connected to the second clock signal; The reference voltage input terminal of the third comparator is connected to the second reference voltage, and the clock input terminal of the third S / A is connected to the first clock signal; The reference voltage input terminal of the fourth comparator is connected to the third reference voltage, and the clock input terminal of the fourth S / A is connected to the first clock signal.

[0013] In one embodiment, the reference voltage input terminal of the first comparator is connected to a first reference voltage, and the clock input terminal of the first S / A is connected to a first clock signal; The reference voltage input terminal of the second comparator is connected to a second reference voltage, and the clock input terminal of the second S / A is connected to a first clock signal; The reference voltage input terminal of the third comparator is connected to a third reference voltage, and the clock input terminal of the third S / A is connected to a first clock signal; The reference voltage input terminal of the fourth comparator is connected to a fourth reference voltage, and the clock input terminal of the fourth S / A is connected to a first clock signal.

[0014] In one embodiment, the data receiving training circuit of the LPDDR5 memory system further includes a first multiplexer (MUX); The input terminals of the first MUX are respectively connected to the first reference voltage, the second reference voltage, the third reference voltage and the fourth reference voltage; The output of the first MUX is connected to the reference voltage input of each of the four comparators. When the LPDDR5 memory system is detected to have entered training mode, the first MUX is controlled to provide different reference voltages to the reference voltage input terminals of at least two of the four comparators.

[0015] In one embodiment, the data receiving training circuit of the LPDDR5 memory system further includes a second MUX; The input terminals of the second MUX are respectively connected to the first clock signal, the second clock signal, the third clock signal and the fourth clock signal; The output of the second MUX is connected to the clock input of each of the four S / A inputs; When the LPDDR5 memory system is detected to have entered training mode, the second MUX is controlled to provide the same clock signal to the clock input terminals of the comparators corresponding to different reference voltages.

[0016] In one embodiment, when the LPDDR5 memory system is detected to have entered normal operating mode, the first MUX is controlled to provide the same reference voltage to the reference voltage input terminals of the four comparators, and the second MUX is controlled to provide different clock signals to the clock input terminals of the four S / A circuits.

[0017] In addition, to achieve the above objectives, this application also proposes an LPDDR5 storage system, which includes the aforementioned data receiving training circuit of the LPDDR5 storage system.

[0018] One or more technical solutions proposed in this application have at least the following technical effects: By connecting different reference voltages to the reference voltage input terminals of at least two comparators, and connecting the same clock signal to the clock input terminals of the corresponding S / A converters of the comparators connected to different reference voltages, the number of phase clocks involved in training is reduced, thereby reducing training time. The S / A converters with the same clock signal can acquire sampling results in parallel at the same time, improving the utilization efficiency of training information, thereby improving training efficiency and convergence speed, and reducing training time. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a circuit diagram of a receiving circuit in the prior art; Figure 2 This is a circuit diagram of the data receiving and training circuit of the LPDDR5 memory system of this application; Figure 3 This application provides a circuit structure diagram for the first embodiment of the data receiving training circuit of the LPDDR5 memory system. Figure 4 The circuit structure diagram provided in Embodiment 2 of the data receiving training circuit of the LPDDR5 memory system of this application; Figure 5 The circuit structure diagram provided in Embodiment 3 of the data receiving training circuit of the LPDDR5 memory system of this application; Figure 6The circuit structure diagram provided in Embodiment 4 of the data receiving training circuit of the LPDDR5 memory system of this application; Figure 7 The circuit structure diagram provided in Embodiment 5 of the data receiving training circuit of the LPDDR5 memory system of this application; Figure 8 This is a timing diagram of the data reception training circuit of an LPDDR5 memory system in related technologies; Figure 9 This is a timing diagram of the data receiving training circuit of the LPDDR5 memory system of this application; Figure 10 This is a flowchart illustrating an embodiment of the circuit control method of this application. Figure 11 This is a schematic diagram of the device structure of the hardware operating environment involved in the circuit control method in the embodiments of this application.

[0022] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0026] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0027] The main solution of this application embodiment is: the data receiving training circuit of the LPDDR5 memory system includes: a comparator module and an amplifier module; the comparator module includes four comparators, and the amplifier module includes four sense amplifiers (S / A) connected one-to-one with the four comparators; in training mode, at least two of the four comparators are connected to different reference voltages at their reference voltage input terminals, and the clock input terminals of the S / A corresponding to the comparators connected to different reference voltages are connected to the same clock signal.

[0028] In LPDDR5 (Low Power Double Data Rate 5 Synchronous Dynamic Random-Access Memory) storage systems, the data DQ signal is used to transmit high-speed read and write data, and its reception accuracy and training efficiency directly affect the system performance and stability.

[0029] Currently, LPDDR5 data receivers typically use a multi-phase clock in conjunction with a reference voltage to sample the input signal. For example... Figure 1 As shown, the four comparators in the receiving circuit are connected to the same reference voltage Ref, and the four sense amplifiers (S / A) are connected to different clock signals, such as WCK_0, WCK_90, WCK_180, and WCK_270. After the DQ signal is input to the receiving circuit, the comparator compares the DQ signal with the reference voltage to obtain preliminary level information. The comparison result is input to the sense amplifier (S / A) for regeneration and amplification, and latching is completed under the control of the corresponding clock, thereby realizing the conversion of serial data to parallel data.

[0030] However, the above-mentioned receiving training process requires the calibration of multiple phase clocks one by one, which increases the training complexity. Since each phase clock needs to participate in the training, the overall training process is quite lengthy and the training time is long. Furthermore, the results of sampling from different phase paths cannot be obtained in parallel at the same time, resulting in low efficiency in the utilization of training information and thus low training efficiency.

[0031] Therefore, how to improve the training efficiency of the receiving training circuit and reduce the training time is an urgent problem to be solved.

[0032] This application provides a solution that reduces the number of phase clocks involved in training by connecting different reference voltages to the reference voltage input terminals of at least two comparators, and connecting the same clock signal to the clock input terminals of the corresponding S / A converters of the comparators connected to different reference voltages. This reduces training time, and the S / A converters with the same clock signal can acquire sampling results in parallel at the same time, improving the utilization efficiency of training information, thereby improving training efficiency and convergence speed, and reducing training time.

[0033] This invention proposes a data receiving training circuit for an LPDDR5 memory system.

[0034] Please see Figure 2 In one embodiment of the present invention, the data receiving training circuit of the LPDDR5 memory system includes a comparator module and an amplifier module. The comparator module includes four comparators, and the amplifier module includes four sense amplifiers (S / A). The four sense amplifiers (S / A) are connected to the four comparators one-to-one. That is, each comparator is connected to one sense amplifier (S / A), and the data output terminal of the comparator is electrically connected to the data input terminal of the sense amplifier (S / A).

[0035] Among them, such as Figure 2 As shown, the data input terminals of the four comparators are respectively connected to input data DQ, the reference voltage input terminals of the four comparators are respectively connected to reference voltage Ref, and the clock input terminals of the four S / A converters are respectively connected to clock signal WCK. The reference voltage Ref may include one or more reference voltages, and the clock signal WCK may include one or more clock signals. For example, the reference voltage Ref may include one or more of the first reference voltage Ref1, the second reference voltage Ref2, the third reference voltage Ref3, and the fourth reference voltage Ref4, and the clock signal WCK may include one or more of the first clock signal WCK_0, the second clock signal WCK_90, the third clock signal WCK_180, and the fourth clock signal WCK_270.

[0036] In training mode, different reference voltages are connected to the reference voltage input terminals of at least two of the four comparators, and the same clock signal is connected to the clock input terminals of the corresponding S / A of the comparators connected to different reference voltages.

[0037] It should be noted that when the data receiving training circuit of the LPDDR5 memory system enters the training mode, different reference voltages are input to the reference voltage input terminals of at least two comparators, and the same clock signal is provided to the S / A connected to the comparators with different reference voltages. By providing the same clock signal to the S / A, the number of phase clocks participating in the training is reduced. The S / A with the same clock signal can acquire the sampling results in parallel at the same time, which improves the utilization efficiency of training information, thereby improving the training efficiency and convergence speed, and reducing the training time.

[0038] In one feasible implementation, please refer to Figure 3 The data reception training circuit of the LPDDR5 memory system also includes a first MUX (Multiplexer).

[0039] The input terminals of the first MUX301 are respectively connected to the first reference voltage Ref1, the second reference voltage Ref2, the third reference voltage Ref3, and the fourth reference voltage Ref4; the output terminal of the first MUX301 is respectively connected to the reference voltage input terminals of the four comparators.

[0040] When the LPDDR5 memory system is detected to have entered training mode, the first MUX301 is controlled to provide different reference voltages to the reference voltage input terminals of at least two of the four comparators.

[0041] In this embodiment, when the LPDDR5 memory system enters the training mode, the LPDDR5 memory system can send a training mode control command to the first MUX301. The first MUX301 switches the reference voltage of each comparator. Specifically, the first MUX301 provides different reference voltages to the reference voltage input terminals of at least two of the four comparators to accurately provide different reference voltages to the comparators.

[0042] In one feasible implementation, please refer to Figure 3 The data receiving training circuit of the LPDDR5 memory system also includes a second MUX302. The input terminals of the second MUX302 are respectively connected to the first clock signal WCK_0, the second clock signal WCK_90, the third clock signal WCK_180, and the fourth clock signal WCK_270; the output terminal of the second MUX302 is respectively connected to the clock input terminals of the four S / A.

[0043] When the LPDDR5 memory system is detected to have entered training mode, the second MUX302 is controlled to provide the same clock signal to the clock input terminals of the corresponding S / A terminals of comparators connected to different reference voltages.

[0044] In this embodiment, when the LPDDR5 memory system enters the training mode, the LPDDR5 memory system can simultaneously send training mode control commands to the first MUX301 and the second MUX302. The first MUX301 provides different reference voltages to the reference voltage input terminals of at least two of the four comparators, and the second MUX302 provides the same clock signal to the clock input terminals of the corresponding S / A of the comparators connected to different reference voltages. By providing the same clock signal to the S / A, the training efficiency and convergence speed are further improved, and the training time is reduced.

[0045] When the LPDDR5 memory system is detected to have entered normal operating mode, the first MUX is controlled to provide the same reference voltage to the reference voltage input terminals of the four comparators, and the second MUX is controlled to provide different clock signals to the clock input terminals of the four S / A circuits.

[0046] In this embodiment, when the LPDDR5 storage system enters the normal operation mode, it sends a normal operation mode control command to the first MUX301 and the second MUX302. At this time, the first MUX301 provides the same reference voltage to the reference voltage input terminals of the four comparators. For example, the reference voltage provided by the first MUX301 to the four comparators can be any one of the first reference voltage Ref1, the second reference voltage Ref2, the third reference voltage Ref3, and the fourth reference voltage Ref4. At the same time, the second MUX302 provides different clock signals to the clock input terminals of the four S / A circuits. For example, the clock signals provided by the second MUX302 to the S / A circuits are the first clock signal WCK_0, the second clock signal WCK_90, the third clock signal WCK_180, and the fourth clock signal WCK_270, respectively, so as to realize the normal operation of the LPDDR5 storage system.

[0047] In one feasible implementation, please refer to Figures 2 to 7 The comparator includes a first comparator 101, a second comparator 102, a third comparator 103, and a fourth comparator 104. The S / A includes a first S / A 201, a second S / A 202, a third S / A 203, and a fourth S / A 204.

[0048] The output of the first comparator 101 is connected to the data input of the first S / A 201, the output of the second comparator 102 is connected to the data input of the second S / A 202, the output of the third comparator 103 is connected to the data input of the third S / A 203, and the output of the fourth comparator 104 is connected to the data input of the fourth S / A 204.

[0049] In one feasible implementation, please refer to Figure 4 The reference voltage input terminal of the first comparator 101 is connected to the first reference voltage, and the clock input terminal of the first S / A201 is connected to the first clock signal. The reference voltage input terminal of the second comparator 102 is connected to the first reference voltage, and the clock input terminal of the second S / A202 is connected to the second clock signal; The reference voltage input terminal of the third comparator 103 is connected to the second reference voltage, and the clock input terminal of the third S / A203 is connected to the first clock signal; The reference voltage input terminal of the fourth comparator 104 is connected to the second reference voltage, and the clock input terminal of the fourth S / A204 is connected to the second clock signal.

[0050] In this embodiment, when the data receiving training circuit of the LPDDR5 memory system enters the training mode, the same reference voltage, namely the first reference voltage Ref1, is provided to the reference voltage input terminals of the first comparator 101 and the second comparator 102, respectively. A first clock signal WCK_0 is provided to the clock input terminal of the first S / A 201, and a second clock signal WCK_90 is provided to the clock input terminal of the second S / A 202. At the same time, the same reference voltage, namely the second reference voltage Ref2, is provided to the reference voltage input terminals of the third comparator 103 and the fourth comparator 104, respectively. A first clock signal WCK_0 is provided to the clock input terminal of the third S / A 203, and a second clock signal WCK_90 is provided to the clock input terminal of the fourth S / A 204. Thus, by providing the same clock signal to the S / A, the number of phase clocks participating in the training is reduced. S / A with the same clock signal can acquire sampling results in parallel at the same time, improving the utilization efficiency of training information, thereby improving training efficiency and convergence speed, and reducing training time.

[0051] For example, the first reference voltage Ref1 can be provided to the first comparator 101 and the second comparator 102 through the first MUX301, and the second reference voltage Ref2 can be provided to the third comparator 103 and the fourth comparator 104; at the same time, the first clock signal WCK_0 can be provided to the first S / A201 and the third S / A203 through the second MUX302, and the second clock signal WCK_90 can be provided to the second S / A202 and the fourth S / A204.

[0052] In one feasible implementation, please refer to Figure 5 The reference voltage input terminal of the first comparator 101 is connected to a first reference voltage, and the clock input terminal of the first S / A201 is connected to a first clock signal. The reference voltage input terminal of the second comparator 102 is connected to the first reference voltage, and the clock input terminal of the second S / A202 is connected to the second clock signal; The reference voltage input terminal of the third comparator 103 is connected to the first reference voltage, and the clock input terminal of the third S / A203 is connected to the third clock signal; The reference voltage input terminal of the fourth comparator 104 is connected to a second reference voltage, and the clock input terminal of the fourth S / A204 is connected to a first clock signal, a second clock signal, or a third clock signal.

[0053] In this embodiment, when the data receiving training circuit of the LPDDR5 memory system enters the training mode, the same reference voltage, namely the first reference voltage Ref1, is provided to the reference voltage input terminals of the first comparator 101, the second comparator 102, and the third comparator 103, respectively. A first clock signal WCK_0 is provided to the clock input terminal of the first S / A201, a second clock signal WCK_90 is provided to the clock input terminal of the second S / A202, and a third clock signal WC is provided to the clock input terminal of the third S / A203. K_180; Simultaneously, a second reference voltage Ref2 is provided to the reference voltage input terminal of the fourth comparator 104, and a first clock signal WCK_0, a second clock signal WCK_90, or a third clock signal WCK_180 is provided to the clock input terminal of the fourth S / A 204; thereby, by providing the same clock signal to the two S / A, the number of phase clocks participating in training is reduced, and the S / A with the same clock signal can acquire the sampling results in parallel at the same time, which improves the utilization efficiency of training information, thereby improving training efficiency and convergence speed, and reducing training time.

[0054] For example, the first reference voltage Ref1 can be provided to the first comparator 101, the second comparator 102 and the third comparator 103 through the first MUX301, and the second reference voltage Ref2 can be provided to the fourth comparator 104; at the same time, the second clock signal WCK_0, the second clock signal WCK_90 and the third clock signal WCK_180 can be provided to the first S / A201, the second S / A202 and the third S / A203 respectively through the second MUX302, and the first clock signal WCK_0, the second clock signal WCK_90 or the third clock signal WCK_180 can be provided to the fourth S / A204.

[0055] In one feasible implementation, please refer to Figure 6The reference voltage input terminal of the first comparator 101 is connected to a first reference voltage, and the clock input terminal of the first S / A201 is connected to a first clock signal. The reference voltage input terminal of the second comparator 102 is connected to the first reference voltage, and the clock input terminal of the second S / A202 is connected to the second clock signal; The reference voltage input terminal of the third comparator 103 is connected to the second reference voltage, and the clock input terminal of the third S / A203 is connected to the first clock signal. The reference voltage input terminal of the fourth comparator 104 is connected to a third reference voltage, and the clock input terminal of the fourth S / A204 is connected to a first clock signal.

[0056] In this embodiment, when the data receiving training circuit of the LPDDR5 memory system enters the training mode, the same reference voltage, namely the first reference voltage Ref1, is provided to the reference voltage input terminals of the first comparator 101 and the second comparator 102, respectively. A first clock signal WCK_0 is provided to the clock input terminal of the first S / A 201, and a second clock signal WCK_90 is provided to the clock input terminal of the second S / A 202. Simultaneously, a second reference voltage Ref2 is provided to the reference voltage input terminal of the third comparator 103, a third reference voltage Ref3 is provided to the reference voltage input terminal of the fourth comparator 104, and a first clock signal WCK_0 is provided to the clock input terminal of the third S / A 203 and the clock input terminal of the fourth S / A 204. By providing the same clock signal to the three S / A, the number of phase clocks participating in the training is reduced. S / A with the same clock signal can acquire sampling results in parallel at the same time, improving the utilization efficiency of training information, thereby improving training efficiency and convergence speed, and reducing training time.

[0057] For example, the first reference voltage Ref1 can be provided to the first comparator 101 and the second comparator 102 through the first MUX301, the second reference voltage Ref2 can be provided to the third comparator 103, and the third reference voltage Ref3 can be provided to the fourth comparator 104; at the same time, the second clock signal WCK_0 can be provided to the first S / A201, the third S / A203 and the fourth S / A204 through the second MUX302, and the second clock signal WCK_90 can be provided to the second S / A202.

[0058] In one feasible implementation, please refer to Figure 7 The reference voltage input terminal of the first comparator 101 is connected to a first reference voltage, and the clock input terminal of the first S / A201 is connected to a first clock signal. The reference voltage input terminal of the second comparator 102 is connected to a second reference voltage, and the clock input terminal of the second S / A202 is connected to a first clock signal; The reference voltage input terminal of the third comparator 103 is connected to a third reference voltage, and the clock input terminal of the third S / A203 is connected to a first clock signal; The reference voltage input terminal of the fourth comparator 104 is connected to a fourth reference voltage, and the clock input terminal of the fourth S / A204 is connected to a first clock signal.

[0059] In this embodiment, when the data receiving training circuit of the LPDDR5 memory system enters the training mode, a first reference voltage Ref1 is provided to the reference voltage input terminal of the first comparator 101, a second reference voltage Ref2 is provided to the reference voltage input terminal of the second comparator 102, a third reference voltage Ref3 is provided to the reference voltage input terminal of the third comparator 103, and a fourth reference voltage Ref4 is provided to the reference voltage input terminal of the fourth comparator 104. Simultaneously, the same phase clock, namely the first clock signal WCK_0, is provided to the clock input terminals of the first S / A201, the second S / A202, the third S / A203, and the fourth S / A204. (See also...) Figure 7 ,Depend on Figure 7 As can be seen, this embodiment can greatly reduce the number of phase clocks involved in training by providing the same clock signal to the four S / A. S / A with the same clock signal can acquire sampling results in parallel at the same time, reducing the dependence on multiple phase clocks during the training phase; improving the utilization efficiency of training information, thereby improving training efficiency and convergence speed, and reducing training time.

[0060] For example, the first reference voltage Ref1 can be provided to the first comparator 101 through the first MUX301, the second reference voltage Ref2 can be provided to the second comparator 102, the third reference voltage Ref3 can be provided to the third comparator 103, and the fourth reference voltage Ref4 can be provided to the fourth comparator 104; at the same time, the first clock signal WCK_0 can be provided to the first S / A201, the second S / A202, the third S / A203 and the fourth S / A204 through the second MUX302.

[0061] It should be noted that, as Figure 8 and Figure 9 As shown, during training on the LPDDR5 storage system, the sampling window positions of D0, D1, D2, D3, D4, D5, D6 and D7 in the data DQ are basically the same. Therefore, the sampling window position can be determined by a certain data in DQ.

[0062] Figure 8In the LPDDR5 memory system, the comparators use the same reference voltage Ref, and the phase clocks of the four S / A are WCK_0, WCK_90, WCK_180 and WCK_270, respectively. Figure 9 In the circuit, the reference voltages of the four comparators are Ref1, Ref2, Ref3 and Ref4, and the phase clock of the four S / A circuits is WCK_0. Figure 8 Each clock cycle samples different data in DQ once, while Figure 9 In each clock cycle, the same data in DQ is sampled four times, achieving four parallel samples of the same data at the same time. Figure 8 and Figure 9 In the training mode, the number of times the same data is sampled is the same, and thus... Figure 9 It can quickly achieve the same number of sampling times as the data. Figure 8 compared to, Figure 9 The corresponding training efficiency can be improved by 75%, which greatly improves training efficiency.

[0063] This embodiment provides a data receiving training circuit for an LPDDR5 memory system. By connecting different reference voltages to the reference voltage input terminals of at least two comparators, and connecting the same clock signal to the clock input terminals of the corresponding S / A converters of the comparators connected to different reference voltages, the number of phase clocks involved in training is reduced, thereby reducing training time. The S / A converters with the same clock signal can acquire sampling results in parallel at the same time, improving the utilization efficiency of training information, thereby improving training efficiency and convergence speed, and reducing training time.

[0064] This also reduces the number of times the phase clock needs to be calibrated one by one, lowers the training complexity, and improves the stability of high-speed data reception.

[0065] Based on this, embodiments of this application provide a circuit control method, referring to... Figure 10 , Figure 10 This is a flowchart illustrating the first embodiment of the circuit control method of this application.

[0066] In this embodiment, the data receiving training circuit of the LPDDR5 memory system in the circuit control method is the data receiving training circuit of the LPDDR5 memory system in the above embodiment; the circuit control method includes steps S110~S130: Step S110: When the LPDDR5 memory system is detected to have entered training mode, control the input data of the four comparators to be input to the data input terminals of the four comparators, and control at least two of the four comparators to be connected to different reference voltages respectively. Step S120: Control the clock input terminals of the comparators connected to different reference voltages to be connected to the same clock signal respectively; Step S130: Obtain the training results through the output terminals of each S / A.

[0067] In this embodiment, when the LPDDR5 memory system is detected to have entered training mode, the LPDDR5 memory system controls the input data DQ to be input to the data input terminals of the four comparators, and controls at least two of the four comparators to be connected to different reference voltages respectively; at the same time, the clock input terminals of the corresponding S / A of the comparators connected to different reference voltages are controlled to be connected to the same clock signal, while the clock input terminals of the other S / A are connected to different clock signals. When the input data DQ is in different voltage ranges, the output results will present different combinations, thereby reflecting the distribution of the input data DQ in the voltage dimension. By analyzing the above sampling results, the effective sampling window position of the input data DQ can be quickly determined.

[0068] In this embodiment, when the data receiving training circuit of the LPDDR5 memory system enters the training mode, different reference voltages are input to the reference voltage input terminals of at least two comparators, and the same clock signal is provided to the S / A connected to the comparators connected to different reference voltages. By providing the same clock signal to the S / A, the number of phase clocks participating in the training is reduced. The S / A with the same clock signal can acquire the sampling results in parallel at the same time, which improves the utilization efficiency of training information, thereby improving the training efficiency and convergence speed, and reducing the training time.

[0069] In one feasible implementation, the circuit control method may further include step S210: Step S210: When the LPDDR5 memory system is detected to have entered normal operating mode, control the four comparators to connect to the same reference voltage, and control the clock input terminals of the four S / A to connect to different clock signals respectively.

[0070] It should be noted that when the LPDDR5 memory system is detected to enter normal operating mode, the four comparators are controlled to connect to the same reference voltage, and the clock input terminals of the four S / A converters are controlled to connect to different clock signals respectively. The system restores the multi-phase clock sampling mode and configures parameters based on the training results obtained from the training mode.

[0071] This embodiment provides a circuit control method. When the LPDDR5 memory system enters training mode, it controls four input data comparators, controlling at least two of the four comparators to be connected to different reference voltages. Then, it controls the clock input terminals of the corresponding S / A of the comparators connected to different reference voltages to be connected to the same clock signal. Then, the training result is obtained through the output terminals of each S / A. By providing the same clock signal to the S / A, the number of phase clocks participating in training is reduced. S / A with the same clock signal can acquire sampling results in parallel at the same time, improving the utilization efficiency of training information, thereby improving training efficiency and convergence speed, and reducing training time.

[0072] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the circuit control method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0073] This application provides a circuit control device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the circuit control method in Embodiment 1 above.

[0074] The following is for reference. Figure 11 The diagram illustrates a structural schematic of a circuit control device suitable for implementing embodiments of this application. The circuit control device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 11 The circuit control device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0075] like Figure 11As shown, the circuit control device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in the read-only memory 1002 or a program loaded from the storage device 1003 into the random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the circuit control device. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the circuit control device to communicate wirelessly or wiredly with other devices to exchange data. Although circuit control devices with various systems are shown in the figures, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0076] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0077] The circuit control device provided in this application, employing the circuit control method in the above embodiments, can solve the technical problem of how to improve the training efficiency of the receiving training circuit and reduce the training time. Compared with the prior art, the beneficial effects of the circuit control device provided in this application are the same as those of the circuit control method provided in the above embodiments, and other technical features in this circuit control device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0078] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0079] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0080] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the circuit control method in the above embodiments.

[0081] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0082] The aforementioned computer-readable storage medium may be included in the circuit control device; or it may exist independently and not assembled into the circuit control device.

[0083] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by a circuit control device, the circuit control device: when it detects that the LPDDR5 memory system has entered the training mode, controls the four comparators to input data to their data input terminals, controls at least two of the four comparators to connect to different reference voltages respectively; controls the clock input terminals of the corresponding S / A converters of the comparators connected to different reference voltages to connect to the same clock signal respectively; and obtains the training result through the output terminals of each S / A converter.

[0084] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0085] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0086] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0087] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described circuit control method. This solves the technical problem of how to improve the training efficiency of the receiving training circuit and reduce training time. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the circuit control method provided in the above embodiments, and will not be repeated here.

[0088] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the circuit control method described above.

[0089] The computer program product provided in this application can solve the technical problem of how to improve the training efficiency of the receiving training circuit and reduce the training time. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the circuit control method provided in the above embodiments, and will not be repeated here.

[0090] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A data receiving and training circuit for an LPDDR5 memory system, characterized in that, The data receiving training circuit of the LPDDR5 memory system includes: a comparator module and an amplifier module; The comparator module includes four comparators, and the amplifier module includes four sense amplifiers S / A connected one-to-one with the four comparators. In training mode, different reference voltages are connected to the reference voltage input terminals of at least two of the four comparators, and the same clock signal is connected to the clock input terminals of the corresponding S / A of the comparators connected to different reference voltages. The data receiving training circuit of the LPDDR5 memory system further includes a first MUX and a second MUX, and the data input terminals of the four comparators are respectively connected to the input data DQ; The input terminals of the first MUX are respectively connected to the first reference voltage, the second reference voltage, the third reference voltage, and the fourth reference voltage; the output terminal of the first MUX is respectively connected to the reference voltage input terminals of the four comparators. The input terminals of the second MUX are respectively connected to the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal; the output terminal of the second MUX is respectively connected to the clock input terminals of the four S / A. When the LPDDR5 memory system is detected to have entered training mode, the first MUX is controlled to provide different reference voltages to the reference voltage input terminals of at least two of the four comparators, and the second MUX is controlled to provide the same clock signal to the clock input terminals of the corresponding S / A terminals of the comparators connected to different reference voltages, so that the corresponding S / A terminals of the comparators connected to different reference voltages sample the data DQ in parallel at the same time.

2. The data receiving and training circuit of the LPDDR5 memory system as described in claim 1, characterized in that, The comparator includes a first comparator, a second comparator, a third comparator, and a fourth comparator; the S / A includes a first S / A, a second S / A, a third S / A, and a fourth S / A; The output of the first comparator is connected to the data input of the first S / A, the output of the second comparator is connected to the data input of the second S / A, the output of the third comparator is connected to the data input of the third S / A, and the output of the fourth comparator is connected to the data input of the fourth S / A.

3. The data receiving and training circuit of the LPDDR5 memory system as described in claim 2, characterized in that, The reference voltage input terminal of the first comparator is connected to a first reference voltage, and the clock input terminal of the first S / A is connected to a first clock signal; The reference voltage input terminal of the second comparator is connected to the first reference voltage, and the clock input terminal of the second S / A is connected to the second clock signal; The reference voltage input terminal of the third comparator is connected to the second reference voltage, and the clock input terminal of the third S / A is connected to the first clock signal; The reference voltage input terminal of the fourth comparator is connected to the second reference voltage, and the clock input terminal of the fourth S / A is connected to the second clock signal.

4. The data receiving and training circuit of the LPDDR5 memory system as described in claim 2, characterized in that, The reference voltage input terminal of the first comparator is connected to a first reference voltage, and the clock input terminal of the first S / A is connected to a first clock signal; The reference voltage input terminal of the second comparator is connected to the first reference voltage, and the clock input terminal of the second S / A is connected to the second clock signal; The reference voltage input terminal of the third comparator is connected to the first reference voltage, and the clock input terminal of the third S / A is connected to the third clock signal; The reference voltage input terminal of the fourth comparator is connected to a second reference voltage, and the clock input terminal of the fourth S / A is connected to a first clock signal, a second clock signal, or a third clock signal.

5. The data receiving and training circuit of the LPDDR5 memory system as described in claim 2, characterized in that, The reference voltage input terminal of the first comparator is connected to a first reference voltage, and the clock input terminal of the first S / A is connected to a first clock signal; The reference voltage input terminal of the second comparator is connected to the first reference voltage, and the clock input terminal of the second S / A is connected to the second clock signal; The reference voltage input terminal of the third comparator is connected to the second reference voltage, and the clock input terminal of the third S / A is connected to the first clock signal; The reference voltage input terminal of the fourth comparator is connected to the third reference voltage, and the clock input terminal of the fourth S / A is connected to the first clock signal.

6. The data receiving and training circuit of the LPDDR5 memory system as described in claim 2, characterized in that, The reference voltage input terminal of the first comparator is connected to a first reference voltage, and the clock input terminal of the first S / A is connected to a first clock signal; The reference voltage input terminal of the second comparator is connected to a second reference voltage, and the clock input terminal of the second S / A is connected to a first clock signal; The reference voltage input terminal of the third comparator is connected to a third reference voltage, and the clock input terminal of the third S / A is connected to a first clock signal; The reference voltage input terminal of the fourth comparator is connected to a fourth reference voltage, and the clock input terminal of the fourth S / A is connected to a first clock signal.

7. The data receiving training circuit of the LPDDR5 memory system as described in any one of claims 1 to 6, characterized in that, When the LPDDR5 memory system is detected to have entered normal operating mode, the first MUX is controlled to provide the same reference voltage to the reference voltage input terminals of the four comparators, and the second MUX is controlled to provide different clock signals to the clock input terminals of the four S / A circuits.

8. An LPDDR5 memory system, characterized in that, The LPDDR5 storage system includes the data receiving and training circuit of the LPDDR5 storage system according to any one of claims 1 to 7.

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