Program-verify techniques in memory devices

Abstract

A memory device includes a memory block having a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings. The memory device also includes circuitry configured to program memory cells of a selected word line of the plurality of word lines to a plurality of data states in a plurality of program loops including program pulses and verify operations. During at least one of the verify operations, the circuitry is configured to not lock out a set of the plurality of NAND strings. The NAND strings in the set include at least some of the memory cells of the selected word line that have completed programming such that power is conducted through the NAND strings in the set during sensing.

Description

Background Technology 1. Technical Field

[0002] This disclosure generally relates to improved programming verification techniques for addressing the CELSRC bounce effect.

[0003] 2. Related Technologies

[0004] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0005] NAND memory devices include chips with multiple memory blocks, each of which includes an array of memory cells arranged in multiple word lines. Programming the memory cells of a word line to retain data typically occurs in multiple programming cycles. Each programming cycle includes the application of a programming pulse to the control gate of the word line and a verification operation that senses a threshold voltage of the memory cell being programmed. Data is sensed during both the programming operation and subsequent read operations. There remains a continuous need for improved sensing techniques to enhance the reliability of sensing operations. Summary of the Invention

[0006] One aspect of this disclosure relates to a method of performing a programming operation in a memory device. The method proceeds to the step of preparing a memory block comprising a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings. The method continues to the step of programming memory cells of selected word lines among the plurality of word lines to a plurality of data states in a plurality of programming cycles. Each programming cycle includes a programming pulse and a verification operation. In at least one programming cycle, during the verification operation, the method continues to the step of not locking a set of a plurality of NAND strings. The NAND strings in the set include at least some memory cells of the selected word lines that have been programmed, such that power is conducted through the NAND strings in the set during sensing.

[0007] According to another aspect of this disclosure, the multiple programming data states include multiple early data states associated with a relatively low threshold voltage range and multiple later data states associated with a relatively high threshold voltage range.

[0008] According to another aspect of this disclosure, the step of not locking the set of NAND strings so that power is conducted through the set of NAND strings during sensing occurs during programming of multiple later data states.

[0009] According to another aspect of this disclosure, the plurality of programming data states includes seven programming data states, and the plurality of later data states includes three of the seven programming data states.

[0010] According to another aspect of this disclosure, the set of NAND strings includes NAND strings coupled to memory cells that have been programmed with all but one programmed data state.

[0011] According to another aspect of this disclosure, the memory device also includes a source line, and during sensing, the source line is set to approximately zero volts (0V).

[0012] According to another aspect of this disclosure, the method further includes the step of applying a verification voltage to a selected word line during a verification operation of at least one programming cycle in the programming cycle.

[0013] Another aspect of this disclosure relates to a memory device comprising a memory block having a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings. The memory device further includes circuitry configured to program memory cells of selected word lines among the plurality of word lines into a plurality of data states during a plurality of programming cycles including programming pulses and verification operations. During at least one verification operation in the verification operations, the circuitry is configured not to lock the set of the plurality of NAND strings. The NAND strings in the set include at least some of the memory cells of the selected word lines that have been programmed, such that power is conducted through the NAND strings in the set during sensing.

[0014] According to another aspect of this disclosure, the multiple programming data states include multiple early data states associated with a relatively low threshold voltage range and multiple later data states associated with a relatively high threshold voltage range.

[0015] According to another aspect of this disclosure, the circuit is configured not to lock the set of multiple NAND strings during programming of multiple later data states.

[0016] According to another aspect of this disclosure, the plurality of programming data states include seven programming data states, and the plurality of later data states include three of the seven programming data states.

[0017] According to another aspect of this disclosure, the set of NAND strings includes NAND strings coupled to memory cells that have been programmed with all but one programmed data state.

[0018] According to another aspect of this disclosure, the memory device also includes a source line, wherein during sensing, the circuit sets the source line to approximately zero volts (0V).

[0019] According to another aspect of this disclosure, during the verification operation of at least one programming cycle in the programming cycle, the circuit applies a verification voltage to the selected word line.

[0020] Another aspect of this disclosure relates to an apparatus comprising a memory block having a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings. The apparatus further includes a programming unit for programming memory cells of selected word lines among the plurality of word lines into a plurality of data states during a plurality of programming cycles including programming pulses and verification operations. During at least one verification operation in the verification operations, the programming unit is configured not to lock a first set of the plurality of NAND strings, the first set of NAND strings including at least some of the memory cells of the selected word lines that have been programmed. The programming unit is also configured to conduct power through the NAND strings of the first set and through the NAND strings of a second set including the memory cells of the selected word lines being programmed.

[0021] According to another aspect of this disclosure, the multiple programming data states include multiple early data states associated with a relatively low threshold voltage range and multiple later data states associated with a relatively high threshold voltage range.

[0022] According to another aspect of this disclosure, the programming component is configured not to lock the set of multiple NAND strings during programming of multiple later data states.

[0023] According to another aspect of this disclosure, the plurality of programming data states includes seven programming data states, and the plurality of later data states includes three of the seven programming data states.

[0024] According to another aspect of this disclosure, the first set of NAND strings includes NAND strings coupled to memory cells that have been programmed with all but one programmed data state.

[0025] According to another aspect of this disclosure, the device also includes a source line, and during sensing, the programming unit sets the source line to approximately zero volts (0V). Attached Figure Description

[0026] A more detailed description is given below with reference to exemplary embodiments depicted in the accompanying drawings. It should be understood that these drawings depict only exemplary embodiments of this disclosure and are therefore not intended to limit its scope. This disclosure is described and explained more specifically and in detail using the accompanying drawings, wherein:

[0027] Figure 1A This is a block diagram of an example memory device;

[0028] Figure 1B This is a block diagram of an example control circuit;

[0029] Figure 1C yes Figure 1A A block diagram of an example circuit for a memory device;

[0030] Figure 2 Depicting Figure 1A A block of memory cells in an example two-dimensional configuration of a memory array;

[0031] Figure 3A and Figure 3B A cross-sectional view of an example floating gate memory cell in a NAND string is depicted;

[0032] Figure 4A and Figure 4B A cross-sectional view of an example charge-trapping memory cell in a NAND string is depicted;

[0033] Figure 5 An example block diagram of the sensing block SB1 in Figure 1 is depicted;

[0034] Figure 6A This is a perspective view of a set of blocks in an example three-dimensional configuration of the memory array in Figure 1;

[0035] Figure 6B Depicting Figure 6A An example cross-sectional view of a portion of one of the blocks;

[0036] Figure 6C Depicting Figure 6B A graph showing the diameter of storage holes in the stack;

[0037] Figure 6D Depicting Figure 6B A close-up view of the stacked area 622;

[0038] Figure 7A Depicting Figure 6B A top view of an example stacked wordline layer WL0;

[0039] Figure 7B Depicting Figure 6B A top view of the top dielectric layer DL116 in an example of stacking;

[0040] Figure 8 The threshold voltage distribution of a page of memory cells programmed as one bit per memory cell (SLC) is depicted;

[0041] Figure 9 The threshold voltage distribution of a page of memory cells programmed as three bits per memory cell (TLC) is depicted;

[0042] Figure 10It is the waveform of the voltage applied to the selected word line during the example programming operation;

[0043] Figure 11 This is a schematic diagram of the selected NAND string during an exemplary sensing operation;

[0044] Figure 12 This is a graph of the sensing node voltage versus time during an exemplary sensing operation;

[0045] Figure 13 This is a schematic diagram of an example memory block that includes multiple NAND strings during a sensing operation;

[0046] Figure 14 This is a schematic diagram illustrating the voltages applied to multiple word lines in a memory block during an exemplary negative sensing operation;

[0047] Figure 15 This is a schematic diagram illustrating the voltages applied to multiple word lines in a memory block during an exemplary positive sensing operation;

[0048] Figure 16 It is a threshold voltage distribution map of two sets of memory cells being programmed into a data state, one set of memory cells being programmed using positive sensing during the verification operation, and the other set being programmed using negative sensing during the verification operation;

[0049] Figure 17A It is a threshold voltage distribution diagram of multiple memory cells being programmed into three bits per memory cell (TLC) during programming in the S6 data state according to a certain type of programming operation;

[0050] Figure 17B It is a threshold voltage distribution diagram of multiple memory cells that have been programmed as TLC during the read operation of S6 data state;

[0051] Figure 18 This is a flowchart of steps including a programmable memory device according to an exemplary embodiment of the present disclosure;

[0052] Figure 19A It is a threshold voltage distribution map of multiple memory cells being programmed into a TLC during programming in the S6 data state according to the exemplary embodiment; and

[0053] Figure 19B This is a threshold voltage distribution diagram of multiple memory cells that have been programmed as TLC during the read operation of S6 data state. Detailed Implementation

[0054] This invention generally relates to a program verification technique whereby certain NAND strings coupled to a programmed memory cell are not locked during sensing. This allows the CELSRC bounce that occurs during positive sensing to exhibit a more consistent pattern during both verification and read operations. This consistency improves the overall reliability of the data programmed into the memory cell. These techniques are discussed in more detail below.

[0055] Figure 1A This is a block diagram of an example memory device 100 configured to program memory cells in word lines of a memory block according to the sensing technology of this disclosure. Memory die 108 includes a memory structure 126 of memory cells (such as a memory cell array), control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable by word lines via row decoder 124 and by bit lines via column decoder 132. Read / write circuitry 128 includes a plurality of sensing blocks SB1, SB2, ... Sbp (sensing circuitry) and allows parallel reading or programming of a page of memory cells. Typically, controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0056] Memory structure 126 can be two-dimensional or three-dimensional. Memory structure 126 may include one or more memory cell arrays comprising a three-dimensional array. Memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory stages are formed on (rather than in) a single substrate (such as a wafer), without intermediate substrates. Memory structure 126 may include any type of non-volatile memory monolithically formed in one or more physical stages of a memory cell array having active regions disposed above a silicon substrate. Memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of memory cells, whether the associated circuitry is above or within the substrate.

[0057] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations.

[0058] Storage region 113 may be provided, for example, for programming parameters. Programming parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact connector thickness parameters, and / or verification voltage, etc. Location parameters may indicate the location of the memory cell within the entire NAND string array, the location of the memory cell within a specific NAND string group, and / or the location of the memory cell on a specific plane, etc. Contact connector thickness parameters may indicate the thickness of the contact connector and / or the substrate or material constituting the contact connector, etc.

[0059] On-chip address decoder 114 provides an address interface between the addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to word lines and bit lines during memory operations. It may include drivers for word lines, SGS and SGD transistors, and source lines. In one approach, the sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0060] In some implementations, some components may be combined. In various designs, one or more of the components other than memory structure 126 (alone or in combination) may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2, ... SBp, read / write circuit 128, controller 122, etc.

[0061] The control circuit 150 may include a programming circuit 151 configured to perform programming and verification operations on a set of memory cells, wherein the set of memory cells includes memory cells assigned to represent one of a plurality of data states and memory cells assigned to represent another of the plurality of data states; the programming and verification operations include multiple programming and verification iterations; and in each programming and verification iteration, the programming circuit performs programming on a selected word line, after which the programming circuit applies a verification signal to the selected word line. The control circuit 150 may also include a counting circuit 152 configured to obtain a count of memory cells that have passed a verification test for a data state. The control circuit 150 may also include a determining circuit 153 configured to determine whether the programming operation is complete based on the amount by which the count exceeds a threshold.

[0062] For example, Figure 1B This is a block diagram of an example control circuit 150, including a programming circuit 151, a counting circuit 152, and a determining circuit 153.

[0063] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, an error correction code (ECC) engine 245, and a locking engine 246. The ECC engine can correct many read errors caused when the upper tail of the Vt distribution becomes too high. However, in some cases, uncorrectable errors may exist. The techniques presented herein reduce the likelihood of uncorrectable errors.

[0064] Storage devices 122a and 122b include code such as an instruction set, and processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, processor 122c may access the code from storage device 126a of memory structure 126 (e.g., a reserved area of ​​memory cells in one or more word lines). For example, the code may be used by controller 122 to access memory structure 126, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., an instruction set). Boot code is software that initializes controller 122 during a boot or startup process and enables controller 122 to access memory structure 126. The code may be used by controller 122 to control one or more memory structures 126. Upon power-up, processor 122c retrieves boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by processor 122c. Control code includes drivers that perform basic tasks, such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0065] Typically, control code may include instructions to perform the functions described herein (including the steps in the flowcharts discussed further below) and provide voltage waveforms, including those discussed further below. For example, as Figure 1C As shown, control circuitry 110, controller 122, control circuitry 150, and / or any other circuitry are configured / programmed to perform programming operations using a unique NAND string locking technique. At step 160, data states S1 to Sn-1 are programmed without using the unique locking technique. At step 161, during the verification of data states Sn to S7, all memory cells Er to Sn-1 are not locked (conductive) except for one of those data states. These techniques are discussed in more detail below.

[0066] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory in communication with the one or more processors, one or more input / output interfaces, and / or one or more input / output devices.

[0067] Other types of non-volatile memory besides NAND flash memory can also be used.

[0068] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) devices or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which is considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0069] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements (such as antifuse or phase-change materials) and optionally manipulation elements (such as diodes or transistors). Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0070] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically comprises memory elements connected in series. A NAND string is an example of a group of transistors connected in series, including memory cells and SG transistors.

[0071] NAND memory arrays can be configured such that the array consists of multiple memory strings, wherein a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0072] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single planar level or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends substantially parallel to the main surface of the substrate supporting the memory element (e.g., in the xy-direction plane). The substrate may be a wafer on which the memory element layer is formed, or the substrate may be a carrier substrate attached to the memory element after the memory element is formed. As a non-limiting example, the substrate may include a semiconductor (such as silicon).

[0073] Memory elements can be arranged in an ordered array (such as by multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines (such as bit lines and word lines).

[0074] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., along the x, y and z directions, where the z direction is generally perpendicular to the main surface of the substrate, and the x and y directions are generally parallel to the main surface of the substrate).

[0075] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., along the y-direction), each column containing multiple memory elements. The columns can be arranged in a two-dimensional configuration (e.g., in the xy-plane) to produce a three-dimensional arrangement of memory elements having multiple vertically stacked elements on the memory plane. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0076] As a non-limiting example, in a three-dimensional NAND string array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0077] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers that are at least partially located within the single substrate. As a non-limiting example, the substrate may include a semiconductor (such as silicon). In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the lower memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or there may be intermediate layers between memory device classes.

[0078] Furthermore, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on individual substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on individual substrates, the resulting memory array is not a monolithic three-dimensional memory array. Alternatively, multiple (monolithic or non-monolithic) two-dimensional or three-dimensional memory arrays can be formed on individual chips and then packaged together to form a stacked chip memory device.

[0079] Figure 2Memory blocks 200, 210 of memory cells in an example two-dimensional configuration of memory array 126 of FIG1 are shown. Memory array 126 may contain a plurality of such blocks 200, 210. Each example block 200, 210 includes multiple NAND strings and respective bit lines, such as BL0, BL1... These bit lines are shared between blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gate of the drain-side select gate is connected via a common SGD line. The NAND string is connected at its other end to a source-side select gate (SGS), which is in turn connected to a common source line 220. One hundred and twelve word lines (e.g., WL0 to WL111) extend between the SGS and the SGD. In some embodiments, a memory block may include more or fewer than one hundred and twelve word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four word lines. In some cases, dummy word lines that do not contain user data may also be used in the memory array adjacent to the select gate transistor or between certain data word lines. This virtual word line can shield edge data word lines from certain edge effects.

[0080] One type of non-volatile memory that can be provided in a memory array is a floating-gate memory, such as... Figure 3A and Figure 3B The type shown is correct. However, other types of non-volatile memory can also be used. As discussed in further detail below, in Figure 4A and Figure 4B In another example shown, the charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric composed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between a conductive control gate and the surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are trapped and stored in a limited area. The stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting a hot hole into the nitride. A similar cell can be provided in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0081] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across a channel between the source and drain. The charge of one data bit is located in the dielectric layer adjacent to the drain, and the charge of the other data bit is located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0082] Figure 3A Cross-sectional views of example floating-gate memory cells 300, 310, and 320 in a NAND string are shown. In this figure, the bit lines or NAND string direction enters the page, and the word lines direction is from left to right. As an example, word line 324 extends across the NAND string including corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell 300, 310, and 320 is located in a different corresponding NAND string. An inter-silicon dielectric (IPD) layer 328 is also shown. Control gates 302, 312, and 322 are portions of the word lines. Figure 3B A cross-sectional view along the contact line connector 329 is provided.

[0083] Control gates 302, 312, and 322 surround floating gates 304, 314, and 321, thereby increasing the surface contact area between control gates 302, 312, and 322 and floating gates 304, 314, and 321. This results in higher IPD capacitance, leading to a higher coupling ratio, which makes programming and erasing easier. However, as NAND memory devices scale down, the spacing between adjacent cells 300, 310, and 320 becomes smaller, resulting in almost no space between two adjacent floating gates 302, 312, and 322 for control gates 302, 312, and 322 and the IPD layer 328.

[0084] As an alternative, such as Figure 4A and Figure 4B As shown, planar or flat memory cells 400, 410, and 420 have been developed, in which the control gates 402, 412, and 422 are planar or flat; that is, they do not surround the floating gate and only contact the charge storage layer 428 from above. In this case, having a high floating gate offers no advantage. Instead, the floating gate is fabricated to be thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the problem of ballistic electron transport, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0085] Figure 4AA cross-sectional view of example charge-trapping memory cells 400, 410, and 420 in a NAND string is depicted. This view is a two-dimensional example of memory cells 400, 410, and 420 in the memory cell array 126 of FIG1, in the word line direction including the flat control gate and charge-trapping region. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator such as a SiN film to store electrons, in contrast to floating-gate MOSFET technology which uses a conductor such as doped polysilicon to store electrons. As an example, word line 424 extends across the NAND string including corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are IPD layer 428, charge trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunneling layers 409, 407, and 408. Each charge trapping layer 404, 414, and 421 extends continuously within its respective NAND string. The flat configuration of the control gate can be made thinner than that of a floating gate. Additionally, memory cells can be placed more closely together.

[0086] Figure 4B It shows Figure 4A The structure is shown in a cross-sectional view along the contact connector 429. The NAND string 430 includes an SGS transistor 431, example memory cells 400, 433, ... 435, and an SGD transistor 436. Channels in the IPD layer 428 of the SGS transistor 431 and SGD transistor 436 allow communication between the control gate layer 402 and the floating gate layer. For example, the control gate 402 and the floating gate layer may be polysilicon, and the tunnel oxide layer may be silicon oxide. The IPD layer 428 may be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0087] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. The channel voltage Vch can be directly applied to the channel region of the substrate.

[0088] Figure 5An example block diagram of the sensing block SB1 of Figure 1 is shown. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, example sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and processed by a corresponding processor in each sensing block. For example, a sensing circuit controller 560 in SB1 can communicate with this group of sensing circuits and latches. The sensing circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sensing circuit for setting a precharge voltage. In one possible approach, the voltage is provided to each sensing circuit independently, for example, via a data bus and a local bus. In another possible approach, a common voltage is provided to each sensing circuit simultaneously. The sensing circuit controller 560 may also include the precharge circuit 561, a memory 562, and a processor 563. Memory 562 may store code that can be executed by a processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, 553b associated with sensing circuits 550a, 551a, 552a, 553a, setting bit values ​​in the latches, and providing voltages for setting precharge levels in the sensing nodes of sensing circuits 550a, 551a, 552a, 553a. Further example details of the sensing circuit controller 560 and sensing circuits 550a, 551a, 552a, 553a are provided below.

[0089] In some implementations, a memory cell may include a flag register comprising a set of latches storing flag bits. In some implementations, the number of flag registers may correspond to the number of data states. In some implementations, one or more flag registers may be used to control the type of verification technique used when verifying a memory cell. In some implementations, the output of the flag bits may modify relevant logic of the device (e.g., address decoding circuitry) such that a specified cell block is selected. Batch operations (e.g., erase operations, etc.) may be performed using flags set in the flag registers or a combination of flag registers and address registers (as in implicit addressing) or alternatively by direct addressing using only address registers.

[0090] Figure 6AThis is a perspective view of a group of blocks 600 in an example three-dimensional configuration of the memory array 126 of Figure 1. On the substrate are example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements) and a peripheral region 604 having circuitry used by blocks BLK0, BLK1, BLK2, and BLK3. For example, this circuitry may include a voltage driver 605, which may be connected to the control gate layer of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, the control gate layers at a common height in blocks BLK0, BLK1, BLK2, and BLK3 are commonly driven. The substrate 601 may also carry circuitry beneath blocks BLK0, BLK1, BLK2, and BLK3, as well as one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in a central region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block BLK0, BLK1, BLK2, BLK3 includes a stacked region of memory cells, where alternating stacked levels represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing layered sides from which vertical contacts extend upwards to the upper metal layer to form connections to the conductive paths. Although four blocks BLK0, BLK1, BLK2, BLK3 are shown as an example, two or more blocks extending in the x and / or y directions can be used.

[0091] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0092] Figure 6B It shows Figure 6A An example cross-sectional view of a portion of one of blocks BLK0, BLK1, BLK2, and BLK3 is shown. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WL0 to WL111, the conductive layers include two SGD layers, two SGS layers, and four virtual word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL116. Furthermore, a region of stack 610 including NAND strings NS1 and NS2 is shown. Each NAND string contains memory vias 618 and 619, which are filled with material forming memory cells adjacent to the word lines. Region 622 of stack 610 is... Figure 6DThe details are shown in more detail below and discussed further. The dielectric layer can have variable thickness, allowing some conductive layers to be closer to or further away from adjacent conductive layers. The thickness of the electrolyte layer affects the "ON pitch," a factor in memory density. Specifically, a smaller ON pitch allows for more memory cells in a given area but may compromise reliability.

[0093] Stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of a source line SL. NS1 has a source end 613 at the bottom 614 of the stack and a drain end 615 at the top 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 may be periodically provided across stack 610 as interconnects extending through stack 610, for example, to connect source lines to specific contact lines above stack 610. Contact line connectors 617, 620 may be used during word line formation and subsequently metal-filled. A portion of bit line BL0 is also shown. A conductive via 621 connects drain end 615 to BL0.

[0094] Figure 6C It shows Figure 6B A graph showing the diameter of storage holes in the stack. The vertical axis is parallel to... Figure 6B The stack alignment is shown, and the width (wMH) of storage holes 618 and 619 is shown, for example, the diameter. Figure 6A Word line layers WL0 to WL111 are repeated as an example and are located at their respective heights z0 to z111 in the stack. In this memory device, the memory vias etched through the stack have very high aspect ratios. For example, a depth-to-diameter ratio of about 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory via can vary along the length of the via. Typically, the diameter gradually decreases from the top to the bottom of the memory via. That is, the memory via is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the via near the select gate, causing the diameter to become slightly wider before gradually narrowing from the top to the bottom of the memory via.

[0095] Figure 6D It shows Figure 6BA close-up view of region 622 of stack 610. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 680, 681 are disposed above virtual memory cells 682, 683 and data memory cells MC. Multiple layers may be deposited along the sidewalls (SW) of memory via 630 and / or within each word line layer, for example using atomic layer deposition. For example, each column (e.g., a pillar formed by material within memory via 630) may include a charge trapping layer or film 663 (such as SiN or other nitrides), a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. Word line layers may include a blocking oxide / blocking high-k material 660, a metal blocking layer 661, and a conductive metal (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are disposed within memory via 630. In other methods, some layers can be formed within the control gate layer. Similarly, additional pillars are formed in different memory vias. These pillars can form the pillared active regions (AA) of the NAND string.

[0096] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and then pass through the tunneling layer. The threshold voltage Vt of the memory cell increases proportionally to the amount of stored charge. During sensing operations, the threshold voltage Vt is detected or measured. During erasing operations, the electrons return to the channel.

[0097] Each of the memory vias 630 may be filled with a plurality of annular layers, including a barrier oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer. The core region of each of the memory vias 630 is filled with a host material, and the plurality of layers are located between the core region and the word line layer in each of the memory vias 630. In some cases, the charge trapping layer 663 and the tunneling layer 664 are annular in shape. In other cases, as discussed in further detail below, these layers are semi-circular in shape.

[0098] NAND strings can be considered to have floating channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked one on top of the other and separated from each other by dielectric layers.

[0099] Figure 7A It shows Figure 6BA top view of an example word line layer WL0 of stack 610. As described above, a three-dimensional memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates for SG transistors and memory cells. The layer for the SG transistors is the SG layer, and the layer for the memory cells is the word line layer. Furthermore, memory vias are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0100] In a three-dimensional memory device, a block BLK can be divided into sub-blocks, each sub-block comprising a group of NAND strings with a common SGD control line. Furthermore, the word line layer within the block can be divided into multiple regions. Each region is within a corresponding sub-block and can extend between contact line connectors (e.g., slots) periodically formed in the stack to process the word line layer during the manufacturing process of the memory device. This processing may include replacing the sacrificial material of the word line layer with metal. Generally, the distance between the contact line connectors should be relatively small to account for the distance limitations on the etchant's ability to travel laterally to remove the sacrificial material, and the distance limitations on the metal's ability to travel to fill the voids created by the removal of the sacrificial material. For example, the distance between the contact line connectors may allow for several rows of memory vias between adjacent contact line connectors. The layout of the memory vias and contact line connectors should also consider limitations on the number of bit lines that can extend across the region, while each bit line is connected to a different memory cell. After processing the word line layer, the contact line connectors may optionally be filled with metal to provide interconnects across the stack.

[0101] In this example, there are four rows of memory holes between adjacent contact line connectors. Here, a row is a set of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are staggered to increase the density of the memory holes. The word line layer or word line is divided into regions WL0a, WL0b, WL0c, and WL0d, each connected by contact line 713. In one method, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. Contact line 713 is in turn connected to a voltage driver for the word line layer. Region WL0a has example memory holes 710, 711 along contact line 712. Region WL0b has example memory holes 714, 715. Region WL0c has example memory holes 716, 717. Region WL0d has example memory holes 718, 719. Memory holes are also... Figure 7B As shown in the diagram. Each storage hole can be part of the corresponding NAND string. For example, storage holes 710, 714, 716, and 718 can be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0102] Each circle represents a cross-section of a memory via at a word line layer or SG layer. Example circles shown in dashed lines represent memory cells provided by the material in the memory via and adjacent word line layers. For example, memory cells 720 and 721 are in WL0a, memory cells 724 and 725 are in WL0b, memory cells 726 and 727 are in WL0c, and memory cells 728 and 729 are in WL0d. These memory cells are at a common height in the stack.

[0103] Contact wire connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 may be located between and adjacent to the edges of regions WL0a to WL0d. Contact wire connectors 701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where this conductive line is connected to a voltage driver in a peripheral region of the memory device.

[0104] Figure 7B It shows Figure 6B The image shows a top view of the top dielectric layer DL116 of the stack. The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to a corresponding voltage driver. This allows a group of memory cells in a region of the word line layer to be programmed simultaneously, with each memory cell located in a corresponding NAND string connected to the corresponding bit line. During each programming, sensing, or erasing operation, a voltage can be set on each bit line.

[0105] Region DL116a has example memory holes 710, 711 along contact line 712 coinciding with bit line BL0. Multiple bit lines extend above and are connected to the memory holes, as indicated by the "X" symbol. BL0 is connected to a set of memory holes including memory holes 711, 715, 717, and 719. Another example bit line BL1 is connected to a set of memory holes including memory holes 710, 714, 716, and 718. Figure 7A Contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 are also shown because they extend vertically through the stack. Bit lines may cross the DL116 layers in the x-direction, numbered sequentially from BL0 to BL23.

[0106] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in the adjacent row of cells adjacent to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in the adjacent row of cells adjacent to the first row at the left edge.

[0107] The memory cells of a memory block can be programmed to store one or more data bits in multiple data states, each of which is associated with a corresponding threshold voltage Vt range and with a corresponding bit or bit series. For example, Figure 8 The threshold voltage Vt distribution of a set of memory cells programmed according to a single-cell-per-memory-bit (SLC) memory scheme is depicted. In the SLC memory scheme, there are a total of two data states, including the erase state (Er) and the single-program data state (S1). Figure 9 The threshold voltage Vt distribution for a three-bit per cell (TLC) memory scheme is shown, which includes a total of eight data states: an erase state (Er) and seven programming data states (S1, S2, S3, S4, S5, S6, and S7). Each programming data state (S1 through S7) is associated with a corresponding verification voltage (Vv1 through Vv7), which is applied during the verification portion of the programming operation. Similarly, each programming data state is associated with a unique read voltage, which may be the same as or different from the corresponding verification voltage. Other memory schemes are also available, such as two-bit per cell (MLC) with four data states, four-bit per cell (QLC) with sixteen data states, or five-bit per cell (PLC) with thirty-two data states. The QLC memory scheme includes an erase state Er and fifteen programming data states (S1 through S15).

[0108] Memory cells are programmed on a string-by-string and word-by-word basis, moving from one side of the memory block (source side or drain side) towards the opposite side. In other words, strings of the first word line (e.g., four strings) are programmed sequentially, one after another, then the operation is repeated for the second word line, and then for the third word line, and so on. Typically, programming the memory cells of the selected word line begins with the memory cell in an erase-data state, reserving multiple bits per cell (e.g., MLC, TLC, or QLC), and includes multiple programming cycles to increase the threshold voltage Vt of those memory cells to the appropriate voltage range associated with their respective expected data states. Each programming cycle includes both a programming pulse and a verification operation. Figure 10 A waveform 1000 depicts the voltage applied to a selected word line during an example programming operation to program a memory cell of a selected word line to a larger number of bits per memory cell (e.g., TLC or QLC). As shown, each programming cycle includes a programming pulse (hereinafter referred to as the VPGM pulse) and one or more verification pulses, depending on which data states are being programmed in a particular programming cycle. For simplicity, a square wave waveform is depicted for each pulse; however, other shapes are also possible, such as multi-stage or ramp shapes.

[0109] This example pulse sequence uses incremental step pulse programming (ISPP), meaning the VPGM pulse voltage gradually increases or rises in each successive programming cycle. More specifically, the pulse sequence includes VPGM pulses whose amplitude gradually increases with each successive programming cycle by a programming voltage step (dVPGM). A new pulse sequence begins with a VPGM pulse at the start voltage VPGMU and ends with a final VPGM pulse at a voltage not exceeding the maximum allowable voltage. Example pulse sequence 1000 includes a series of VPGM pulses 1001 to 1018 applied to the control gate of a selected word line to program the memory cell of the selected word line, with the amplitude increasing by the programming voltage step dVPGM between pulses.

[0110] Based on the target data state being verified in the corresponding programming loop, one or more verification pulses 1020 to 1036 are provided after each VPGM pulse. The verification voltage can be during TLC programming. Figure 9The voltages Vv1 to Vv7 are shown. Simultaneously with the application of the verification voltage, a sensing operation is performed to determine whether a specific memory cell in the selected word line has a threshold voltage Vt higher than the verification voltage Vv associated with its expected data state by sensing the current flowing through the NAND string containing the memory cells. If the memory cell passes verification, programming of that memory cell is completed, and further programming of that memory cell is suppressed (or locked) for all remaining programming cycles by simultaneously applying a suppression voltage to the bit line coupled to the memory cell with the VPGM pulse and by skipping the verification of those memory cells. During the bit scan operation, the memory device determines whether programming of one or more states is complete. Programming continues until all (or a sufficient number) memory cells in the selected word line pass verification for their expected state, in which case programming succeeds, or until a predetermined maximum number of programming cycles is exceeded, in which case programming fails.

[0111] Now for reference Figure 11 and Figure 12 During sensing operations (e.g., programming-verification or reading), the sensing node SEN on the drain side of the memory block is charged to a predetermined charging voltage. The reference voltage VCG (e.g., during verification) is used. Figure 9Vv1 to Vv7 are applied to the control gate of the selected word line WLn. Simultaneously, all memory cells in the NAND string, except those of the selected word line, are "turned on" (conducted) by applying a pass voltage VREAD or VREADK to the unselected word lines. The relatively higher pass voltage VREADK is applied to a pair of adjacent word lines WLn-1 and WLn+1 directly adjacent to the selected word line WLn, and the relatively lower pass voltage VREAD is applied to all other unselected word lines in the memory block. The sensing node SEN is then discharged through the NAND string for a sensing time T_Sense. Since all memory cells except those of the selected word line WLn are turned on by the pass voltages VREAD and VREADK, the discharge current ICELL through the NAND string is primarily determined by the threshold voltage Vt of the sensed selected memory cell. More specifically, the discharge current is determined by whether the threshold voltage Vt is greater than or less than the reference voltage VCG applied to the selected word line WLn during this process. At discharge time T_Sense, the voltage on the sensing node SEN is sensed by the sensing circuit and compared with the sensed voltage V_Sense, which is the threshold voltage Vt of the sensing transistor. If the threshold voltage Vt of the memory cell being sensed is higher than the reference voltage VCG, the selected memory cell is "turned off" and conducts a very small / negligible current, resulting in only a small discharge of the SEN node voltage, thus maintaining a higher voltage on the sensing node compared to V_Sense. If the threshold voltage Vt of the selected memory cell being sensed is lower than the reference voltage VCG, the memory cell is "turned on" and conducts a larger discharge current, resulting in the sensing node biasing below V_Sense. This process determines whether the threshold voltage Vt of the memory cell is higher or lower than the reference voltage VCG. This process can be repeated for each programming data state in the programming data state.

[0112] Figure 13 An overview of the memory device architecture. For example, Figure 13 This depicts multiple memory strings (e.g., NAND strings) connected to a common BSL layer or Cell Source Repository (CELSRC) layer of the memory devices. The source node of the NAND string is connected to the CELSRC. For example... Figure 13The description further illustrates that the node connecting the memory aperture and the sense amplifier SA is a bit line BL, and during sensing (verification or readout), the cell current ICELL flows from the corresponding sense amplifier SA and into the CELSRC layer. CELSRC drivers drive the CELSRC layer from the opposite side of the node. Therefore, during sensing, the voltage at corresponding points around the CELSRC layer can vary as the current ICELL flows through the numerous bit lines into the CELSRC layer. More specifically, during sensing, the CELSRC voltage can be at its lowest near the connection to the CELSRC driver and at its highest at the center location between the CELSRC drivers.

[0113] The variable voltage across the CELSRC layer, caused by the current in the NAND string, affects the magnitude of the ICELL for the same current within the NAND string. If left uncorrected, this adjustment to the ICELL can cause sensing problems by making some memory cells appear to have a different threshold voltage Vt than they actually possess. More specifically, as the CELSRC voltage increases at the junction of the NAND string and its connections, the gate-to-source level Vgs and drain-to-source level Vds of the memory cells within that NAND string decrease. This decrease in Vgs and Vds reduces the ICELL for the current flowing through the NAND string, making the selected memory cell appear as if it is not conducting or has a higher threshold voltage Vt than it actually possesses. This phenomenon occurs in… Figure 13 As shown in the figure, and sometimes this causes CELSRC bounce, which leads to a threshold voltage shift (Vt shift). In this figure, the CELSRC gradient is the IR drop from the center to the edge of the CELSRC layer (in... Figure 13 The voltage across the NAND string is a factor (represented as resistance). CELSRC bounce and gradients cause sensing errors because Vgs and Vds are smaller across the NAND string for cells with higher CELSRC voltages. Because the voltage of the CELSRC layer varies at different locations, memory cells in different NAND strings are sensed inconsistently.

[0114] Now for reference Figure 14A sensing technique sometimes called "negative sensing" can be used to reduce the Vt offset caused by CELSRC bounce. Negative sensing involves applying a positive voltage VCELSRC (e.g., VCELSRC = 1V) to the CELSRC driver during sensing operation and biasing (increasing) the bit line voltage VBL by the same voltage VCELSRC. The reference voltage VCG and the through voltages VREAD and READK are also increased by the same positive voltage VCELSRC. By increasing VCELSRC with all these voltages, the voltage variation at the base of the NAND string across the memory block is reduced. However, negative sensing results in high current ICC usage because all voltages are set high due to bias. Moreover, performance is compromised because additional time is required to drive these components to the increased voltage level.

[0115] Figure 15 An alternative sensing technique known as "positive sensing" is illustrated. In positive sensing, a very low voltage (e.g., 0 or approximately 0 volts, VSS) is applied to the CELSRC layer during sensing, and no additional bias voltage is added to the bit line voltage VBL or the reference voltage VCG (e.g., ...). Figure 9 (The verification voltages shown are any one of Vv1 to Vv7) or through voltages VREAD and VREADK. Therefore, the magnitude of the voltage applied to these components is reduced compared to negative sensing. Consequently, the voltage required for the word lines and bit lines to ramp up is reduced, resulting in reduced peak and average current Icc. Furthermore, positive sensing eliminates the need for ramp-up and ramp-down CELSRC bias, thereby reducing ramp-up and settling times and improving performance compared to negative sensing, which keeps all other variables constant. Therefore, positive sensing generally provides improved performance, reduced current usage, and reduced power consumption compared to negative sensing.

[0116] One problem with positive sensing is the large CELSRC bounce in the early programming cycles for each data state Sn (e.g., any of S1 through S7). This is because most of the memory cells programmed to that data state Sn are conductive, resulting in current flowing through many NAND strings. This leads to a relatively high CELSRC bounce, which can cause some memory cells programmed to data state Sn to pass verification prematurely (i.e., before their threshold voltage Vt exceeds the verification voltage Vvn). This phenomenon occurs in... Figure 16The figure shows the threshold voltage Vt distributions of multiple memory cells programmed to data state Sn using positive sensing, with reference numerals 1600a and 1600b indicating the distributions of threshold voltage Vt of multiple memory cells programmed to the same data state Sn using negative sensing. As shown, the lower tail of the positive sensing distribution 1602b extends below the verification level Vvn because some memory cells erroneously pass verification prematurely. One way to mitigate this problem is to shift the verification level upwards during positive sensing to prevent memory cells from passing verification prematurely.

[0117] However, positive sensing can cause other problems. During programming verification, the number of conductive NAND strings is lower compared to typical read operations. This is especially true for higher data states. This is due to the locking of NAND strings associated with data states that were not programmed during programming verification. For example, in TLC programming, only about one-eighth (1 / 8) of the NAND strings are conductive during any given sensing operation, regardless of which specific data state Sn is being programmed. Conversely, during read operations, the number of locked NAND strings is typically lower for earlier data states (e.g., data states S1, S2, and S3) and higher for later data states (e.g., data states S5, S6, and S7). Figure 17A The threshold voltage Vt distribution of multiple memory cells being programmed into TLC during programming verification in the S6 data state is shown, and Figure 17B The distribution of threshold voltage Vt for multiple programmed memory cells during a read operation in the S6 data state is shown. In both figures, solid lines represent memory cells coupled to the on (unlocked) NAND string, and dashed lines represent memory cells coupled to the off (locked) NAND string. As shown, substantially more memory cells (and their associated NAND strings) conduct power during read operations than during program verification. Therefore, the CELSRC bounce is similar during program verification and read operations in lower data states and varies more significantly during program verification and read operations in higher data states.

[0118] To make the CELSRC bounce more consistent during verification and reading across all programmed data states, according to one aspect of this disclosure, a selective non-locking programming verification technique is employed, such that approximately the same number of NAND strings are turned on during both programming verification and reading, facilitating the CELSRC bounce for positive sensing. This has been found to improve reliability and reduce failure bits during reading.

[0119] Figure 18This includes a flowchart 1800 depicting steps for programming a memory cell of a selected word line according to an exemplary embodiment of this disclosure. These steps may be performed by a controller; a processor or processing device or any other circuitry executing instructions stored in memory; and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0120] The process begins at step 1802, programming the initial data state. Specifically, data states S1 to Sn-1, where the initial data state Sn is a predetermined data state at the start of the selective non-locking verification technique. During the verification operation of the programming loop used to program the data states S1 to Sn-1, a positive sensing scheme is utilized. In an exemplary embodiment, data state Sn is the S5 data state of the TLC storage scheme (e.g., ...). Figure 9 (As shown). In some other implementations, the data state Sn at this step can be data state S4, S6, or S7.

[0121] At step 1804, programming of the Sn data state begins by applying a VPGM pulse to the selected word line. At step 1806, verification of the data state Sn begins. At step 1808, memory cells from data state Sn+1 to the highest data state are locked, and memory cells programmed to a data state one step below the selected data state Sn are also locked. During subsequent sensing operations, current will not flow through the NAND string containing the locked memory cells. Instead, current will flow through the NAND string containing the memory cells that are not locked during subsequent sensing operations. Figure 19A In an exemplary implementation, the data state Sn being programmed is S6, and data states S7 and S2 are locked. Memory cells in other data states Er, S1, S3, S4, and S5 are not locked.

[0122] At step 1810, a sensing operation is performed on the memory cells being programmed to the data state Sn to compare the threshold voltage Vt of these memory cells being programmed with the verification voltage Vvn associated with the Sn data state. The sensing operation is a positive sensing operation, meaning that the source line is set to approximately zero volts (0V) during the discharge of the sensing node. All unlocked NAND strings are conductive during the sensing operation. The number of memory cells that have failed verification is then counted and compared with a predetermined threshold to determine whether the programming of the Sn data state is complete.

[0123] At decision step 1812, it is determined whether the verification of the Sn data state passes. If the answer at decision step 1812 is "no", then at step 1814, the programming voltage VPGM is incrementally increased by a step size dVPGM, i.e., VPGM = VPGM + dVPGM. Then another VPGM pulse is applied to the selected word line, and the process returns to step 1806.

[0124] If the answer at decision step 1812 is "yes", the process proceeds to decision step 1816. At decision step 1816, it is determined whether the data state Sn is the last data state to be programmed, for example, S7 in the case of a TLC. If the answer at decision step 1816 is "no", then at step 1818, the data state Sn being programmed is incremented, i.e., Sn = Sn + 1. At step 1820, the programming voltage VPGM is incremented by a step size dVPGM, i.e., VPGM = VPGM + dVPGM. Then, a VPGM pulse is applied to the selected word line. The process then returns to step 1806.

[0125] If the answer at decision step 1816 is "yes", then the programming operation is completed at step 1822.

[0126] Figure 19A The distribution of threshold voltage Vt of multiple memory cells being programmed during programming in data state S6 is shown, and Figure 19B The distribution of threshold voltage Vt for multiple memory cells being programmed during the read phase of data state S6 is shown. In both figures, solid lines depict memory cells coupled to the NAND string that is on (not locked), and dashed lines depict memory cells coupled to the NAND string that is locked (not on) during sensing. As shown, according to the technique of this disclosure, approximately the same number of memory cells are on during both the programming verification and read phases of data state S6. Specifically, approximately three-quarters (3 / 4) of the NAND string is on during both operations. Therefore, the CELSRC bounce will be similar during programming verification and read phases. According to the technique of this disclosure, the same will occur for other data states in later data states (e.g., data states S5 and S7).

[0127] Similarly, Figure 19A and Figure 19B As shown, the technology of this disclosure also allows the use of approximately the same reference voltage VCG during programming verification and reading of the later data state.

[0128] Various terms are used herein to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this description is not intended to distinguish components with different names but the same function. With regard to the various functional units described in the following disclosure being referred to as “modules,” this characterization is intended not to unduly limit the scope of potential implementation mechanisms. For example, a “module” can be implemented as hardware circuitry comprising custom-designed very large-scale integration (VLSI) circuitry or gate arrays, or as off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components. In another example, a module can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, or programmable logic devices. Furthermore, modules can also be implemented, at least in part, by software executed by various types of processors. For example, a module may include fragments of executable code constituting one or more physical or logical blocks of computer instructions that translate into objects, procedures, or functions. Furthermore, it is not required that the executable portions of such a module be physically located together, but rather that they may include different instructions stored in different locations and, when executed together, constitute the identified module and achieve the module’s stated purpose. Executable code may consist of a single instruction or a set of instructions, and may be distributed across different code segments, different programs, or multiple memory devices. In software or partial software module implementations, the software portion may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, apparatuses, or devices, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may include any tangible and / or non-transitory medium capable of containing and / or storing programs used by or in connection with an instruction execution system, apparatus, processor, or device.

[0129] Similarly, for the purposes of this disclosure, the term "component" can include any tangible, physical, and non-transitory device. For example, a component can be in the form of hardware logic circuitry, including custom VLSI circuitry, gate arrays, or other integrated circuits, or off-the-shelf semiconductors containing logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic equipment. Furthermore, components can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Additionally, a component can include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices configured to communicate electrically with one or more other components via electrical conductors such as printed circuit boards (PCBs). Therefore, modules as defined above can be embodied in or implemented as components in some embodiments, and in some cases, the terms module and component are used interchangeably.

[0130] When the term "circuit" is used herein, it includes one or more electrical and / or electronic components that form one or more conductive paths allowing current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components provide a return path for the current. In contrast, in an open-loop configuration, the circuit components are still considered to form a circuit, although a return path for the current is not included. For example, an integrated circuit is referred to as a circuit regardless of whether it is coupled to ground (as a return path for the current). In some exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuitry, gate arrays, logic circuits, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices, configured to communicate electrically with one or more other components via electrical conductors, such as a printed circuit board (PCB). A circuit may also be implemented as a composite circuit relative to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Therefore, modules as defined above may be embodied in or implemented as circuits in some embodiments.

[0131] It should be understood that the exemplary embodiments disclosed herein may include one or more microprocessors and specifically stored computer program instructions that control one or more microprocessors in combination with certain non-processor circuitry and other elements to implement some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions may be implemented by a state machine without the stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein each function or some combinations of certain functions is implemented as custom logic. Combinations of these methods may also be used. Furthermore, the term "controller" as used below should be defined to include individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs) and / or processors with control software, or combinations thereof.

[0132] Alternatively, the terms “coupled,” “coupled,” or “couples” as used herein are intended to indicate a direct or indirect connection. Thus, if a first device is coupled or coupled to a second device, the connection can be a direct connection or an indirect connection via other devices (or components) and connectors.

[0133] Regarding terms such as “implementation,” “an implementation,” “exemplary implementation,” “specific implementation,” or other similar terms as used herein, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with that implementation is found in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as “in one implementation,” “in an implementation,” “in an exemplary implementation,” etc., may, but not necessarily, refer to the same implementation, but rather means “one or more, but not all, implementations,” unless expressly stated otherwise. Furthermore, the terms “comprising,” “having,” “including,” and variations thereof are used in an open-ended manner and should therefore be construed as meaning “including, but not limited to…,” unless expressly stated otherwise. Moreover, without further constraints, an element prefixed with “comprising…a” does not exclude the presence of additional identical elements in the subject matter process, method, system, article, or apparatus that includes that element.

[0134] The terms “a,” “an,” and “the” also mean “one or more” unless otherwise expressly stated. For example, a “processor” programmed to perform various functions means one processor programmed to perform each function, or more than one processor collectively programmed to perform each of the various functions. Furthermore, the phrase “at least one of A and B” (where A and B are variables indicating a particular object or attribute) that may be used herein and / or in the following claims indicates either A or B, or a choice of both A and B, similar to the phrase “and / or.” When more than two variables are present in such a phrase, the phrase is thus defined to include only one variable, any one variable, any combination (or subcombination) of any variables, and all variables.

[0135] Furthermore, when used herein, the terms “approximately” or “about” apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated value (e.g., having the same function or result). In some cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0136] Furthermore, any list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless otherwise expressly stated. Additionally, the term "set" as used herein should be interpreted as "one or more," and in the case of "set," it should be interpreted as "one or more," "ones or more," and / or "ones or mores" according to set theory, unless otherwise expressly stated.

[0137] For purposes of illustration and description, the foregoing detailed description has been provided. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible based on the above description. The described embodiments have been chosen to best explain the principles of the technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments and to make various modifications suitable for the intended particular use. The scope of this technology is defined by the appended claims.

Claims

1. A method for performing programming operations in a memory device, the method comprising the following steps: Prepare a memory block, the memory block comprising a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings; The memory cell of a selected word line among the plurality of word lines is programmed into a plurality of data states in a plurality of programming cycles, the programming cycle including a programming pulse and a verification operation; as well as In at least one programming cycle of the programming cycle, during the verification operation, the set of the plurality of NAND strings, the NAND strings in the set including at least some memory cells of the selected word lines that have been programmed, is not locked, such that power is conducted through the NAND strings in the set during sensing.

2. The method according to claim 1, wherein, The multiple programmed data states include multiple early data states associated with a relatively low threshold voltage range and multiple later data states associated with a relatively high threshold voltage range.

3. The method according to claim 2, wherein, The step of not locking the set of NAND strings so that power is conducted through the set of NAND strings during sensing occurs during the programming of the plurality of later data states.

4. The method according to claim 3, wherein, The plurality of programming data states includes seven programming data states, and the plurality of later data states includes three of the seven programming data states.

5. The method according to claim 1, wherein, The set of NAND strings includes NAND strings coupled to memory cells that have been programmed with all but one programmed data state.

6. The method of claim 1, further comprising a source line, wherein, During sensing, the source line is set to approximately zero volts (0V).

7. The method of claim 1, further comprising the step of applying a verification voltage to a selected word line during the verification operation of at least one programming cycle of the programming cycle.

8. A memory device, the memory device comprising: A memory block, the memory block comprising a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings; as well as A circuit configured to, during at least one verification operation in a plurality of programming cycles including programming pulses and verification operations, program the memory cell of a selected word line from the plurality of word lines into a plurality of data states, the circuit being configured to: The set of multiple NAND strings is not locked, the NAND strings in the set including at least some memory cells of the memory cells of the selected word lines that have been programmed, such that power is conducted through the NAND strings in the set during sensing.

9. The memory device according to claim 8, wherein, The multiple programmed data states include multiple early data states associated with a relatively low threshold voltage range and multiple later data states associated with a relatively high threshold voltage range.

10. The memory device according to claim 9, wherein, The circuit is configured to not lock the collection of the plurality of NAND strings during programming of the plurality of late data states.

11. The memory device according to claim 9, wherein, The plurality of programming data states includes seven programming data states, and the plurality of later data states includes three of the seven programming data states.

12. The memory device according to claim 8, wherein, The set of NAND strings includes NAND strings coupled to memory cells that have been programmed with all but one programmed data state.

13. The memory device of claim 8, further comprising a source line, and wherein, During sensing, the circuit sets the source line to approximately zero volts (0V).

14. The memory device according to claim 8, wherein, During the verification operation in at least one programming cycle of the programming cycle, the circuit applies a verification voltage to the selected word line.

15. An apparatus comprising: A memory block, the memory block comprising a plurality of memory cells arranged in a plurality of word lines and a plurality of NAND strings; as well as A programming unit, configured to program memory cells of selected word lines among a plurality of word lines into a plurality of data states during at least one verification operation of a plurality of programming cycles including programming pulses and verification operations, the programming unit being configured to: A first set of the plurality of NAND strings is not locked, the first set of NAND strings including at least some memory cells of the memory cells of the selected word lines that have been programmed, and Power is conducted through the first set of NAND strings and through the second set of NAND strings, which includes memory cells of selected word lines being programmed.

16. The apparatus according to claim 15, wherein, The multiple programmed data states include multiple early data states associated with a relatively low threshold voltage range and multiple later data states associated with a relatively high threshold voltage range.

17. The apparatus according to claim 16, wherein, The programming component is configured not to lock the collection of the plurality of NAND strings during programming of the plurality of later data states.

18. The apparatus according to claim 16, wherein, The plurality of programming data states includes seven programming data states, and the plurality of later data states includes three of the seven programming data states.

19. The apparatus according to claim 15, wherein, The first set of NAND strings includes NAND strings coupled to memory cells that have been programmed with all but one programmed data state.

20. The apparatus of claim 15, further comprising a source line, and wherein, During sensing, the programming unit sets the source line to approximately zero volts (0V).

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