Memory testing device with modular temperature control system
By using a modular temperature control system, each memory module is provided with an independent heating system and sealing design, which solves the problems of uneven temperature and low testing efficiency, and achieves high accuracy and high efficiency in memory module testing.
CN122201403APending Publication Date: 2026-06-12SHENZHEN YONGGUANG SHENMU MICROELECTRONICS CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN YONGGUANG SHENMU MICROELECTRONICS CO LTD
- Filing Date
- 2026-03-13
- Publication Date
- 2026-06-12
Smart Images

Figure CN122201403A_ABST
Abstract
The application belongs to the technical field of memory testing, and relates to a memory testing equipment with a module combined temperature control system, which comprises a cabinet. A control panel is arranged on one side wall of the cabinet. Multiple temperature insulation layers are arranged on the lower side of the control panel. Temperature insulation cavities are arranged between two adjacent temperature insulation layers. A drawer box is arranged in the temperature insulation cavities. The drawer box is provided with multiple independent test cavities, and the cavity openings are arranged on the upper side wall of the drawer box. Multiple mainboards are arranged in the drawer box, and the multiple mainboards are arranged on the lower side of the multiple test cavities respectively. The card slots of the mainboards pass through the cavity walls on the lower side of the test cavities and are arranged in the test cavities. The cavity walls of the test cavities are provided with multiple first heating rods. The temperature insulation layers on the upper side of the drawer box are all provided with multiple sealing plates. The sealing plates can be reciprocally displaced in the vertical direction, and when testing, the multiple sealing plates are displaced to abut and fit the circumferential surfaces of the cavity openings of the multiple test cavities respectively.
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