内存的测试方法、装置、电子设备及计算机可读存储介质

By initializing the memory bank address and address value, executing specific instructions, and utilizing the assignment mechanism of loop control coefficients, the stability problem of DRAM chips in scenarios with rapid switching between row and column instructions is solved, and effective stress testing of the row and column multiplexing decoding circuit of memory chips is achieved.

CN122201405BActive Publication Date: 2026-07-17KINGTIGER TESTING TECH (SZ) LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
KINGTIGER TESTING TECH (SZ) LTD
Filing Date
2026-05-14
Publication Date
2026-07-17

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Abstract

本申请提供一种内存的测试方法、装置、电子设备及计算机可读存储介质，属于半导体测试技术领域。该方法包括：初始化存储体地址Z1为1、Z2为2、Z3为3，行地址X为1，列地址Y为1；对第一存储体地址Z1的第1行地址执行行激活指令；对第一存储体地址Z1的第1行地址的第1列地址执行读指令或写指令；对第二存储体地址Z2的第1行地址执行行激活指令；对第一存储体地址Z1的第1行地址执行行预充电指令；对第二存储体地址Z2的第1行地址的第1列地址，执行读指令或写指令；对第三存储体地址Z3的第1行地址执行行激活指令。本申请实现对内存的遍历测试，连续切换行、列指令和地址，实现对内存芯片行列复用解码电路的压力测试。
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