A two parallel converter ripple optimal modulation method for single-phase loop current suppression

Abstract

The application provides a two-parallel-converter ripple optimal modulation method for single-phase loop current suppression, comprising the following steps: based on the equivalent vector plane of two parallel converters, constructing a parallel output current ripple optimal vector time sequence set according to the near three-vector synthesis principle and the non-clamping sequence construction principle; generating a switching time sequence according to the optimal vector time sequence set and the corresponding switching combination, and determining the optimal switching time sequence in each basic sector and sub-sector with the optimization target of minimizing the single-phase loop current peak value; generating a modulation wave and constructing a carrier modulation scheme according to the optimal switching time sequence; and realizing low-frequency single-phase loop current regulation by independently adjusting the duty cycle of each parallel branch, and at the same time, the ripple optimal vector time sequence structure is retained to the greatest extent under the condition of single-phase duty cycle adjustment. The application can not only maintain the output current ripple optimality, but also suppress the low-frequency single-phase loop current introduced by the inductance inconsistency.

Description

Technical Field

[0001] This invention relates to a modulation algorithm that simultaneously optimizes current ripple and single-phase circulating current suppression, specifically to an optimal modulation method for ripple of two parallel converters for single-phase circulating current suppression. Background Technology

[0002] With the continuous growth in demand for high power in industrial applications and new energy power generation, parallel converters have been widely used in high-power motor drives, grid-connected wind power generation, and other scenarios. Current ripple is a core indicator for evaluating the quality of the AC output current of a converter. Deterioration of this indicator exacerbates high-frequency torque pulsation in motors at low speeds, thus shortening the equipment's lifespan. Simultaneously, in practical engineering applications, due to factors such as industrial manufacturing errors, the inductance parameters between parallel branches of each phase are difficult to guarantee completely consistent. This inductance imbalance leads to uneven output power frequency currents between parallel branches, introducing low-frequency circulating currents between the branches. The presence of low-frequency circulating currents can easily lead to inductor core saturation, thereby weakening its ability to suppress high-frequency currents and affecting the reliable operation of the converter. Therefore, how to simultaneously optimize current ripple and effectively suppress low-frequency circulating currents is a core issue for the reliable operation of converters.

[0003] It should be noted that the aforementioned low-frequency circulating current can be divided into single-phase circulating current and zero-sequence circulating current. Among them, single-phase circulating current flows between parallel branches of the same phase in different stations, while zero-sequence circulating current flows between each converter. In essence, zero-sequence circulating current is the superposition value of three-phase single-phase circulating current, and the three-phase single-phase circulating current is decoupled from each other.

[0004] However, existing algorithms for suppressing low-frequency circulating current caused by unbalanced inductors neglect the crucial characteristic of "decoupling between single-phase circulating currents" and often focus only on suppressing zero-sequence circulating current. Essentially, they suppress zero-sequence circulating current by worsening single-phase circulating current, which further saturates single-phase inductors, eventually leading to more phase inductors entering saturation. Although some modulation algorithms (such as [Asiminoaei L, Aeloiza E, Enjeti PN, et al. Shunt Active-Power-Filter Topology Based on Parallel Interleaved Inverters[J]. IEEE Transactions on Industrial Electronics, 2008, 55(3): 1175-1189.]) can regulate low-frequency single-phase circulating current, their current ripple performance is poor and cannot meet the engineering requirements for high-quality output.

[0005] On the other hand, to achieve better current ripple performance, existing modulation algorithms typically select three basic vectors close to the reference vector for synthesis based on the principle of minimizing instantaneous voltage error. These ripple-optimized modulation algorithms (such as those in [Z. Zeng, Z. Li, and S.M. Goetz, “A high-performance interleaved discontinuous PWM strategy for two paralleled three-phase inverter,” IEEE Trans. Power Electron., vol. 35, no. 12, pp. 13042–13052, Dec. 2020, doi: 10.1109 / TPEL. 2020. 2996903.]) usually employ a clamping method (i.e., fixing the switching state of a single phase during the switching cycle). However, this method limits the system's ability to regulate low-frequency single-phase circulating current and makes it difficult to handle various complex unbalanced inductor operating conditions.

[0006] In summary, existing algorithms cannot achieve synergistic optimization between current ripple optimization and low-frequency single-phase circulating current suppression. To address this limitation, this invention proposes a ripple-optimal timing sequence. This timing sequence employs a near-three-vector non-clamping method, which can flexibly handle various unbalanced operating conditions by injecting a duty cycle adjustment signal. While ensuring optimal output current ripple, this algorithm can flexibly suppress the low-frequency single-phase circulating current introduced by the unbalanced phase inductance without worsening the single-phase circulating current in the balanced phase, thereby significantly improving the overall operating performance of the system under non-ideal conditions. Summary of the Invention

[0007] The purpose of this invention is to provide an optimal ripple modulation method for two parallel converters to suppress single-phase circulating current. This method solves the problem that existing methods cannot effectively suppress low-frequency single-phase circulating current while maintaining optimal output current ripple under inductor imbalance conditions. The method constructs a near three-vector non-clamped optimal ripple vector timing sequence. By independently adjusting the duty cycle of each parallel branch, low-frequency single-phase circulating current regulation is achieved. At the same time, under the condition of single-phase duty cycle adjustment, the optimal ripple vector timing sequence structure is preserved to the greatest extent. This method can maintain optimal output current ripple and suppress low-frequency single-phase circulating current introduced by inductor inconsistency.

[0008] The technical solution to achieve the purpose of this invention is as follows:

[0009] An optimal modulation method for ripple in two parallel converters for single-phase circulating current suppression, specifically including:

[0010] Based on the equivalent vector plane of two parallel converters, and following the principle of near three-vector synthesis and the principle of non-clamping sequence construction, an optimal vector timing set for parallel output current ripple is constructed. The optimal vector timing set includes multiple vector timing arrangement methods.

[0011] Based on the optimal vector timing set and its corresponding switch combination, a switching timing sequence is generated, and within each basic sector and its sub-sectors, the optimal switching timing sequence is determined with the optimization objective of minimizing the peak value of the single-phase circulating current.

[0012] Generate a modulation wave and construct a carrier modulation scheme based on the optimal switching timing;

[0013] By flipping the carrier within adjacent carrier cycles, the switching signals of the same bridge arm are made equivalently symmetrical within two carrier cycles. To address the low-frequency single-phase circulating current caused by inconsistent parallel inductor parameters, a duty cycle adjustment is introduced into the unbalanced phase modulation signal to suppress the low-frequency single-phase circulating current caused by inductor inconsistency. Under the condition of single-phase duty cycle adjustment, the optimal vector timing structure of ripple is preserved to the greatest extent.

[0014] Furthermore, the near-three-vector synthesis principle and the non-clamp sequence construction principle are specifically as follows:

[0015] The voltage vector plane is divided into six equal basic sectors, each of which is further divided into four sub-sectors. Each sub-sector is an equilateral triangle with an equal area, and the vertices of each triangle are formed by three basic voltage vectors and their corresponding redundant voltage vectors. Within each sub-sector, a vertex voltage vector of the equilateral triangle or its corresponding redundant voltage vector is selected as the starting voltage vector. A voltage vector sequence is constructed by sequentially increasing or decreasing the total number of conducting devices in the three-phase parallel branches according to phase sequence. After the number of conducting devices in all three phases has changed once, the sequence returns to the starting voltage vector. Another redundant voltage vector corresponding to the initial voltage vector forms a four-segment asymmetric vector sequence containing four voltage vectors; taking the end voltage vector of the four-segment asymmetric vector sequence as the center of symmetry, the four-segment asymmetric vector sequence is mirrored and expanded to obtain a symmetric non-clamped vector timing basic unit containing seven voltage vectors; the symmetric non-clamped vector timing basic unit is repeated twice, and the first and last voltage vectors of adjacent basic units are the same, forming a complete non-clamped vector timing sequence containing 13 voltage vectors, wherein each switching device only turns on once and turns off once within a single carrier cycle.

[0016] Furthermore, the optimal vector timing set for constructing the parallel output current ripple is as follows:

[0017] For the same starting voltage vector, two different non-clamping vector timing sequences are constructed due to the different phase sequences corresponding to the changes in the number of conductions. The voltage vectors at the three vertices of the equilateral triangle are all used as starting voltage vectors. Each basic sector constructs 14 non-clamping vector timing sequences, and the entire voltage vector plane constructs a total of 84 non-clamping vector timing sequences.

[0018] Furthermore, the switching timing is specifically as follows: a switching timing is generated based on the switching combination corresponding to each vector in the optimal vector timing set, wherein one vector timing corresponds to multiple switching timings, each basic sector has 64 switching timings, and there are a total of 384 switching timings in the entire vector plane.

[0019] Furthermore, determining the optimal switching sequence specifically involves: within each sub-sector, comparing the single-phase circulating current peak values ​​corresponding to candidate switching sequences and their redundant sequences based on the position change of the reference voltage vector, and selecting the switching sequence with the smallest single-phase circulating current peak value as the optimal switching sequence for that position; according to the distribution law of the optimal switching sequence with the position of the reference voltage vector, each basic sector is divided into 7 sub-sectors, and each sub-sector corresponds to an optimal switching sequence, so as to achieve the minimum single-phase circulating current peak value in the entire vector plane.

[0020] Furthermore, the carrier modulation scheme specifically includes: the carrier is a sawtooth wave, one type of carrier is an incremental sawtooth carrier, which adopts an incremental counting method, and after reaching a set period value, it is reset to zero and enters the next period; the other type of carrier is a decremental sawtooth carrier, which adopts a decremental counting method, which starts from the set period value, decreases to zero, and then is reassigned to the period value and enters the next period.

[0021] When the switching timing is not symmetrical about 1 / 2 of the carrier period within one carrier period, the corresponding branch compares one carrier with two modulated waves to generate the corresponding switching signal; when the switching timing is symmetrical about 1 / 2 of the carrier period within one carrier period, the corresponding branch compares one modulated wave with two carriers to generate the corresponding switching signal.

[0022] The specific steps for generating the modulation wave based on the optimal switching timing are as follows: based on the conduction state of each parallel branch switching device in the optimal switching timing, the duty cycle of each vector is equivalently converted into the conduction duty cycle of each parallel branch; and combined with the carrier modulation scheme and the corresponding switching operation mode, the modulation wave expression for realizing the optimal switching timing under the corresponding carrier and switching operation mode is derived.

[0023] Furthermore, the switching operation mode specifically includes, when comparing one carrier wave with two modulated waves:

[0024] When the carrier is an incremental sawtooth carrier, if modulation wave 1 is greater than or equal to the incremental sawtooth carrier, or modulation wave 2 is less than or equal to the incremental sawtooth carrier, or modulation wave 1 is less than or equal to the incremental sawtooth carrier and modulation wave 2 is greater than or equal to the incremental sawtooth carrier, then the upper bridge arm switch of the corresponding branch is turned on and the lower bridge arm switch is turned off.

[0025] When the carrier is a decreasing sawtooth carrier, if modulation wave 1 is greater than or equal to the decreasing sawtooth carrier, or modulation wave 2 is less than or equal to the decreasing sawtooth carrier, or modulation wave 1 is less than or equal to the decreasing sawtooth carrier and modulation wave 2 is greater than or equal to the decreasing sawtooth carrier, then the upper bridge arm switch of the corresponding branch is turned on and the lower bridge arm switch is turned off.

[0026] In this context, the modulation wave 2 is greater than the modulation wave 1.

[0027] Furthermore, the switching operation mode of the corresponding branch when comparing a modulated wave with two carriers specifically includes:

[0028] When the modulated wave is simultaneously greater than or equal to the increasing sawtooth carrier and the decreasing sawtooth carrier, the upper bridge arm switch of the corresponding branch is turned on and the lower bridge arm switch is turned off.

[0029] When the modulated wave is simultaneously greater than or equal to both the increasing sawtooth carrier and the decreasing sawtooth carrier, the upper bridge arm switch of the corresponding branch is turned off, and the lower bridge arm switch is turned on.

[0030] Furthermore, the carrier flipping method within adjacent carrier periods is as follows:

[0031] For asymmetric switching timing within a unit carrier period, incremental sawtooth carriers and decremental sawtooth carriers are alternately used in adjacent carrier periods to make the switching timing of two adjacent carrier periods symmetrical about the center of the two carrier periods.

[0032] Furthermore, closed-loop control is implemented to address the low-frequency single-phase circulating current caused by inconsistent parallel inductor parameters. A proportional resonant controller is employed, using the difference between the sampled actual value of the low-frequency single-phase circulating current and the zero reference value as input, and outputting the duty cycle adjustment amount for the two parallel branches of the corresponding phase. The duty cycle adjustment amount is superimposed on the modulation stage. Based on the original duty cycle of the two parallel branches of the three phases, the duty cycle adjustment amount is subtracted from one branch and added to the other branch, thereby achieving low-frequency single-phase circulating current suppression.

[0033] An optimal modulation device for ripple of two parallel converters for single-phase circulating current suppression, comprising:

[0034] The optimal vector timing set construction unit, based on the equivalent vector plane of two parallel converters, constructs the optimal vector timing set for parallel output current ripple according to the principle of near three-vector synthesis and the principle of non-clamping sequence construction. The optimal vector timing set includes multiple vector timing arrangement methods.

[0035] The optimal switching timing determination unit generates a switching timing sequence based on the optimal vector timing sequence set and its corresponding switching combination, and determines the optimal switching timing sequence within each basic sector and its sub-sectors with the optimization objective of minimizing the peak value of the single-phase circulating current.

[0036] The modulation wave generation and carrier modulation scheme determination unit generates a modulation wave and constructs a carrier modulation scheme according to the optimal switching timing.

[0037] The suppression optimization unit achieves equivalent symmetry of the switching signals of the same bridge arm within two carrier cycles by flipping the carrier in adjacent carrier cycles. To address the low-frequency single-phase circulating current caused by inconsistent parallel inductor parameters, a duty cycle adjustment is introduced into the unbalanced phase modulation signal to suppress the low-frequency single-phase circulating current caused by inductor inconsistency. Under the condition of single-phase duty cycle adjustment, the optimal vector timing structure of ripple is preserved to the greatest extent.

[0038] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The present invention proposes an optimal modulation method for ripple of two parallel converters for single-phase circulating current suppression, which solves the problem that existing methods cannot effectively suppress low-frequency single-phase circulating current while maintaining optimal output current ripple under inductor imbalance conditions. (2) It improves the operational reliability and engineering practicality of two parallel converters under non-ideal operating conditions. The duty cycle adjustment method proposed in the present invention does not require changing the main circuit topology or increasing additional hardware costs. It can flexibly cope with various complex inductor imbalance conditions through modulation strategies alone, and has significant engineering application value. Attached Figure Description

[0039] Figure 1 This is a topology diagram of two parallel converters.

[0040] Figure 2 (a) is the equivalent vector plane diagram of two parallel converters. Figure 2 (b) is the equivalent vector plane diagram of two parallel converters based on the unified representation of switch combination.

[0041] Figure 3 This is a vector plane diagram showing the initial sector division within basic sector I of the modulation method proposed in this invention;

[0042] Figure 4 This is a vector plane diagram showing the optimal sector division of the modulation method proposed in this invention within the basic sector I.

[0043] Figure 5 This diagram illustrates six switching operation modes of the modulation method proposed in this invention.

[0044] Figure 6 The diagram shows the switching timing and circulating current waveforms of the modulation method proposed in this invention after using a two-carrier-period symmetrical method for optimal switching timing in sub-sector 1 of basic sector I.

[0045] Figure 7 This is a block diagram for a single-phase circulating current closed-loop control.

[0046] Figure 8 The diagram shows the switching timing and single-phase voltage difference waveforms after applying the proposed single-phase circulating current control method when the A-phase inductance is unbalanced.

[0047] Figure 9 Figures (a) to (c) show the three-phase parallel current, single-phase A-phase circulating current waveform, and zero-sequence circulating current waveform of the modulation method proposed in this invention, respectively.

[0048] Figure 10 Figures (a) to (e) show the dynamic process of the three-phase parallel current waveform, single-phase circulating current of phase A, single-phase circulating current of phase B, single-phase circulating current of phase C, and zero-sequence circulating current waveforms before and after the proposed single-phase circulating current control method is applied when the inductance of phase A is unbalanced.

[0049] Figure 11 Figures (a) to (d) show the circulating current spectra of phase A, phase B, phase C, and zero-sequence circulating current of the two parallel converters at frequencies from 0Hz to 700Hz when the proposed single-phase circulating current control method is not applied due to phase A inductance imbalance. Figure 11 Figures (e) to (h) show the circulating current spectra of phase A, phase B, phase C, and zero-sequence circulating current of the two parallel converters at frequencies of 0Hz to 700Hz after the proposed single-phase circulating current control method is applied when phase A inductance is unbalanced.

[0050] Figure 12 Figures (a) to (e) show the dynamic process of the three-phase parallel current waveform, single-phase circulating current of phase A, single-phase circulating current of phase B, single-phase circulating current of phase C, and zero-sequence circulating current waveform before and after the proposed single-phase circulating current control method is applied when the inductances of phases A and B are unbalanced.

[0051] Figure 13 Figures (a) to (d) show the circulating current spectra of phase A, phase B, phase C, and zero-sequence circulating current of two parallel converters at frequencies from 0Hz to 700Hz when the inductances of phases A and B are unbalanced and the proposed single-phase circulating current control method is not applied. Figure 13Figures (e) to (h) show the circulating current spectra of phase A, phase B, phase C, and zero-sequence circulating current of the two parallel converters after the proposed single-phase circulating current control method is applied when the inductances of phases A and B are unbalanced.

[0052] Figure 14 Figures (a) to (e) show the dynamic process of the three-phase parallel current waveform, single-phase circulating current of phase A, single-phase circulating current of phase B, single-phase circulating current of phase C, and zero-sequence circulating current waveform before and after the proposed single-phase circulating current control method is applied when the three-phase inductors of phases A, B, and C are unbalanced.

[0053] Figure 15 Figures (a) to (d) show the circulating current spectra of phase A, phase B, phase C, and zero-sequence circulating current of two parallel converters at frequencies from 0Hz to 700Hz, when all three phases (A, B, and C) are unbalanced and the proposed single-phase circulating current control method is not applied. Figure 15 Figures (e) to (h) show the circulating current spectra of phase A, phase B, phase C, and zero-sequence circulating current of the two parallel converters after the proposed single-phase circulating current control method is applied when all three phases (A, B, and C) are unbalanced.

[0054] Figure 16 Figures (a) to (c) show the three-phase parallel current spectra of the two parallel converters at frequencies from 0kHz to 20kHz when the proposed single-phase circulating current control method is not applied under the three inductance imbalance conditions mentioned above. Figure 16 Figures (d) to (f) show the three-phase parallel current spectrum of the two parallel converters at frequencies of 0kHz to 20kHz after applying the proposed single-phase circulating current control method under the three inductance imbalance conditions mentioned above. Detailed Implementation

[0055] The technical methods in the embodiments of this aspect will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] In practical engineering applications, due to manufacturing errors and other factors, it is difficult to ensure that the inductance parameters between parallel branches are completely consistent, which can easily lead to an imbalance in the output power frequency current of the two converters. Existing control methods often focus only on suppressing zero-sequence circulating current, but suppressing zero-sequence circulating current cannot guarantee the balance of power frequency current between parallel branches. This control method essentially achieves the suppression of zero-sequence circulating current by sacrificing single-phase circulating current, and the deterioration of single-phase circulating current will further saturate the single-phase inductor, eventually leading to more phase inductors entering a saturated state. Therefore, this invention proposes a method for adjusting single-phase circulating current independently. This method achieves precise control of the single-phase voltage difference of the unbalanced phase by independently adjusting the duty cycle of each parallel branch, thereby suppressing the low-frequency single-phase circulating current introduced by inductance inconsistency.

[0057] Furthermore, current ripple is one of the key indicators for the reliable operation of converters. Existing optimal ripple modulation algorithms typically employ a clamping method, which cannot achieve single-phase circulating current regulation. Therefore, this invention proposes a near-three-vector non-clamping optimal ripple vector timing.

[0058] In summary, this invention can maintain optimal output current ripple while suppressing low-frequency single-phase circulating current introduced by inductance inconsistency. This significantly improves the overall operating performance of the converter under non-ideal conditions.

[0059] This invention proposes an optimal modulation method for ripple in two parallel converters for single-phase circulating current suppression, comprising:

[0060] (1) Based on the equivalent vector plane of two parallel converters, and following the principle of near-three-vector synthesis and the principle of non-clamping sequence construction, an optimal vector timing set for parallel output current ripple is constructed. 84 non-clamping vector timing sequences are constructed across the entire vector plane, specifically including:

[0061] The topology of two parallel converters is as follows: Figure 1 As shown, L and R are parallel inductors and parallel resistors, respectively. L1, R1 and L2, R2 are the bridge-side inductance and parasitic resistance on the first and second converters, respectively. a i b i c Indicates the three-phase parallel current, i a1 i b1 i c1 and i a2 i b2 i c2 These represent the three-phase currents on the first and second converters, respectively. a e b e c This represents the grid-connected three-phase voltage, V. DC This represents the DC bus voltage, where the inductance on the bridge arm side generally satisfies L1=L2 and R1=R2.

[0062] Based on Kirchhoff's laws, the expression for the equivalent output voltage of two parallel converters in a two-phase stationary coordinate system can be derived:

[0063]

[0064] Among them, u α u β These are the components of the equivalent output voltage in the two-phase stationary coordinate system, S. a1 S b1 S c1 S a2 S b2 S c2 These represent the switching states of the switching transistors on the first and second converters, respectively. When the upper transistor of the corresponding phase on each converter is turned on, S... x =1, when the down transistor is on, S x =0.

[0065] Two parallel converters have 64 switching combinations, which can be substituted into the system. Nineteen equivalent voltage output vectors can be obtained. The relationship between the equivalent output voltage vectors of two parallel converters and the switch combination is shown in Table 1. Therefore, the equivalent vector plane diagram can be drawn, as shown below. Figure 2 As shown in (a). Using the stationary coordinate system α-β as the reference plane, the horizontal direction to the right is defined as the positive direction of the α-axis, i.e., the 0° direction, with counter-clockwise rotation being positive. The 19 equivalent voltage output voltage vectors can be divided into 4 groups according to their magnitude: the zero vector with a magnitude of 0, the vector with a magnitude of 1 / 3V... DC The short vector with a magnitude of V DC The mid-vector and magnitude are 2 / 3V DC The long vector is V0. The zero vector V0 is located at the origin; the short vectors are uniformly distributed every 60° along the directions of 0°, 60°, 120°, 180°, 240°, and 300°, and are named V0, ... 13 V 14 V 15 V 16 V 17 V 18 The vectors are uniformly distributed at 60° intervals along the 30°, 90°, 150°, 210°, and 270° directions, and are named V7, V8, V9, and V... 10 V 11 V 12The long vectors are uniformly distributed at 60° intervals along the directions of 0°, 60°, 120°, 180°, 240°, and 300°, with the vectors being V1, V2, V3, V4, V5, and V6 respectively. These zero vectors and the 18 non-zero vectors together constitute a regular hexagonal equivalent vector plane. The equivalent vector plane is divided into 6 basic sectors, with adjacent sectors differing by 60°. Their corresponding angular ranges are as follows: Basic sector I: 0°~60°; Basic sector II: 60°~120°; Basic sector III: 120°~180°; Basic sector IV: 180°~240°; Basic sector V: 240°~300°; Basic sector VI: 300°~360°.

[0066] Table 1. Voltage Vector and Switching State Combinations of Two Parallel Converters

[0067]

[0068] Based on this, following the principle of near three-vector synthesis and the principle of non-clamping sequence construction, the optimal vector timing set for parallel output current ripple is constructed.

[0069] First, the near-three-vector synthesis principle and the non-clamping sequence construction principle are as follows: the basic sector is further subdivided into four sub-sectors, each of which is an equilateral triangle region of equal area. The vertices of each equilateral triangle are composed of three basic voltage vectors and their corresponding redundant voltage vectors. Within each sub-sector, a vertex voltage vector of the equilateral triangle or its corresponding redundant voltage vector is selected as the starting voltage vector. A voltage vector sequence is constructed by sequentially increasing or decreasing the total number of conducting devices in the three-phase parallel branches according to the phase sequence. After the number of conducting devices in all three phases has changed once, the sequence returns to... The starting voltage vector corresponds to another redundant voltage vector, forming a four-segment asymmetric vector sequence containing four voltage vectors. Taking the end voltage vector of the four-segment asymmetric vector sequence as the center of symmetry, the four-segment asymmetric vector sequence is mirrored and expanded to obtain a symmetric non-clamped vector timing basic unit containing seven voltage vectors. The symmetric non-clamped vector timing basic unit is repeated twice, and the first and last voltage vectors of adjacent basic units are the same, forming a complete non-clamped vector timing sequence containing 13 voltage vectors. In a single carrier cycle, each switching device only turns on once and turns off once.

[0070] Next, the vector timing set constructed based on the above non-clamping sequence construction principle is as follows: For the same starting voltage vector, since the phase sequence corresponding to the change in the number of conductions is different, two different non-clamping vector timing sequences can be constructed; the voltage vectors at the three vertices of the equilateral triangle can all be used as starting voltage vectors, and 14 non-clamping vector timing sequences can be constructed in each basic sector, and a total of 84 non-clamping vector timing sequences can be constructed in the entire voltage vector plane.

[0071] Finally, taking basic sector I as an example, the method for constructing vector timing sequences will be explained in detail:

[0072] Define S max S mid and S min Let be the total number of switching devices connected to the positive terminal of the DC bus in each parallel branch belonging to the maximum, intermediate, and minimum value phases, respectively. Each voltage vector on the vector plane can be represented as... For example, the fundamental voltage vector V 13 The switch combination has V 100 / V 111 V 110 / V 101 Wait, within basic sector I, u a >u b >u c Therefore S max =S a S mid =S b S min =S c Then the voltage vector can be uniformly represented as V 211 The vector combinations in Table 1 are then uniformly organized according to the vector representation method described above, as follows: Figure 2 As shown in (b).

[0073] In sub-sector 1 within basic sector I, the three vertex vectors of the equilateral triangle are V0 (V 000 / V 111 / V 222 V 13 (V) 100 / V 211 V 14 (V) 110 / V 221 Selecting one vertex vector V0 as the starting vector, and considering the different phase sequences corresponding to changes in the number of conducting devices, two different non-clamping vector timing sequences can be constructed: one is to increase the total number of conducting devices in the three-phase parallel branch sequentially according to the three phases A, B, and C. After all three phases have changed once, the sequence returns to the other redundant voltage vector corresponding to the starting vector V0, forming a four-segment asymmetric vector sequence containing four voltage vectors: V 000 →V 100 →V 110 →V 111 Next, using the terminal voltage vector of this four-segment asymmetric vector sequence as the center of symmetry, a mirror expansion is performed to obtain a symmetric non-clamped vector timing unit containing seven voltage vectors: V 000 →V 100 →V 110 →V111 →V 110 →V 100 →V 000 Finally, the basic unit of this symmetrical non-clamped vector timing is repeated twice, and the first and last voltage vectors of adjacent basic units are the same, forming a complete non-clamped vector timing sequence containing 13 voltage vectors: V 000 →V 100 →V 110 →V 111 →V 110 →V 100 →V 000 →V 100 →V 110 →V 100 →V 000 Another approach is to decrease the total number of conducting switching devices in the three-phase parallel branch according to the CBA three-phase successive steps, and obtain a complete non-clamping vector timing sequence consisting of 13 vectors in the same manner as above: V 222 →V 221 →V 211 →V 111 →V 211 →V 221 →V 222 →V 221 →V 211 →V 111 →V 211 →V 221 →V 222 .

[0074] Based on the same vector timing construction method described above, using different vertex vectors as starting vectors, all possible near three-vector non-clamped vector timing sequences in basic sector I are listed, as shown in Table 2.

[0075] Table 2. Timing of all possible near-three-vector non-clamping vectors within basic sector I.

[0076]

[0077] As shown in Table 2, there are 14 different vector timing arrangements in basic sector I. Extending this pattern to the entire vector plane, a total of 14 × 6 = 84 vector timing arrangements are constructed, which are summarized below:

[0078] (1) Sector number: Y-1, starting vector V0, path order: large, medium, small, total number of conducting elements trend: increasing, first half cycle vector timing (basic unit of vector timing) is:

[0079]

[0080] (2) Sector number: Y-1, starting vector V0, path order: small, medium, large, total number of conducting elements trend: decreasing, first half cycle vector timing (basic unit of vector timing) is:

[0081]

[0082] (3) Sector number: Y-1, starting vector V 13 / 15 / 17 Path order: small-medium-large; Total conduction count trend: increasing; First half-cycle vector timing (basic vector timing unit):

[0083]

[0084] (4) Sector number: Y-1, starting vector V 13 / 15 / 17 Path order: Medium magnitude; Total conduction count trend: Decreasing; First half-cycle vector timing (basic vector timing unit):

[0085]

[0086] (5) Sector number: Y-1, starting vector V 14 / 16 / 18 Path order: small-large-medium; Total conduction count trend: increasing; First half-cycle vector timing (basic vector timing unit):

[0087]

[0088] (6) Sector number: Y-1, starting vector V 14 / 16 / 18 Path sequence: medium size; total conduction count trend: decreasing; first half-cycle vector timing (basic vector timing unit):

[0089]

[0090] (7) Sector number: Y-2, starting vector V 13 / 15 / 17 Path sequence: medium size; total conduction count trend: increasing; first half-cycle vector timing (basic vector timing unit):

[0091]

[0092] (8) Sector number: Y-2, starting vector V 13 / 15 / 17 Path order: small-large-medium; Total conduction count trend: decreasing; First half-cycle vector timing (basic vector timing unit):

[0093]

[0094] (9) Sector number: Y-2, starting vector V 14 / 16 / 18Path order: Medium magnitude; Total conduction count trend: Increasing; First half-cycle vector timing (basic vector timing unit):

[0095]

[0096] (10) Sector number: Y-2, starting vector V 14 / 16 / 18 Path order: medium-small-large; Total conduction count trend: decreasing; First half-cycle vector timing (basic vector timing unit):

[0097]

[0098] (11) Sector number: Y-3, starting vector V 13 / 15 / 17 Path order: large, medium, small; total conduction count trend: increasing; first half-cycle vector timing (basic vector timing unit):

[0099]

[0100] (12) Sector number: Y-3, starting vector V 13 / 15 / 17 Path order: small, medium, large; total conduction count trend: decreasing; first half-cycle vector timing (basic vector timing unit):

[0101]

[0102] (13) Sector number: Y-4, starting vector V 14 / 16 / 18 Path order: large, medium, small; total conduction count trend: increasing; first half-cycle vector timing (basic vector timing unit):

[0103]

[0104] (14) Sector number: Y-4, starting vector V 14 / 16 / 18 Path order: small, medium, large; total conduction count trend: decreasing; first half-cycle vector timing (basic vector timing unit):

[0105]

[0106] Where Yn represents the sector number, Y represents the basic sector number (I~VI), and n represents the sub-sector number (1~4); the starting vector used varies depending on the basic sector, and V0 can be used as the starting vector for any basic sector. 13 V can be used as the starting vector for basic sector I and basic sector VI. 15 V can be used as the starting vector for basic sector II and basic sector III. 17 It can be used as the starting vector for basic sector IV and basic sector V, V14 V can be used as the starting vector for basic sector I and basic sector II. 16 V can be used as the starting vector for basic sector III and basic sector IV. 18 It can serve as the starting vector for basic sector V and basic sector VI; the path order is arranged according to the magnitude relationship of the three-phase reference voltages in the vector plane. For example, in basic sector I, the largest phase is phase A, the middle phase is phase B, and the smallest phase is phase C. Therefore, S max =S a S mid =S b S min =S c Since the complete vector timing is obtained by repeating the 7-segment vector timing basic unit twice, that is, the complete vector timing is symmetrical about 1 / 2 of the switching cycle, only the vector timing of the first half of the cycle is listed.

[0107] (2) Based on the vector timing set and its corresponding switch combinations, a switching timing sequence is generated, resulting in 384 switching timing sequences across the entire vector plane. One vector timing sequence corresponds to multiple switching timing sequences. Specifically, this includes:

[0108] Based on the vector timing set described in step (1), a switching timing sequence is generated according to the different switch combinations corresponding to each vector. Define s x1-m For the switching state of the upper transistor of phase x of the first converter, s x2-m For the switching state of the upper transistor of phase x of the second converter, s x-m The sum of the number of conducting tubes in the two parallel branches of phase x, where, This indicates three phases, with m=1~13, representing the segment numbers that constitute a complete 13-segment vector timing sequence.

[0109] First, the x-phase vector timing is represented by a 1×13 dimensional row vector matrix [S]. x ] is represented as:

[0110]

[0111] Furthermore, the x-phase switching timing is represented by a 2×13 dimensional matrix. Represented as:

[0112]

[0113] In the formula, S x1 S x2 These are the 1×13-dimensional switching timing row vectors for the x-phase of the first and second converters, respectively.

[0114] The switching timing must satisfy the constraints of vector timing:

[0115]

[0116] Furthermore, the switching timing of the three-phase parallel branches also needs to consider the constraint of the zero-sequence circulating current change rate: since the circulating current change is zero within one carrier cycle, and the vector timing of the second half of the switching cycle is obtained by repeating the vector timing of the first half of the cycle, the change rates of both single-phase circulating current and zero-sequence circulating current must satisfy the following: the change rate of circulating current in the second half of the carrier cycle is equal in value and opposite in sign to the change rate of circulating current in the first half of the cycle. The expressions for the change rates of single-phase circulating current and zero-sequence circulating current are as follows:

[0117]

[0118] From the formula The rate of change of single-phase / zero-sequence circulating current is related to the combination of switching states. The rate of change of single-phase / zero-sequence circulating current is expressed as V... DC Using / (2L1) as the base value, the per-unit processing is performed. The possible values ​​of the single-phase circulating rate of change are 0, 1 and -1, and the possible values ​​of the zero-sequence circulating rate of change are 0, ±1, ±2 and ±3.

[0119] The following uses one of the vector timings V of sub-sector 3 in basic sector I. 211 →V 210 →V 200 →V 100 →V 200 →V 210 →V 211 →V 210 →V 200 →V 100 →V 200 →V 210 →V 211 For example, let's explain in detail how to construct the switching timing sequence:

[0120] The sum of the number of conducting tubes in the two parallel branches of phase A must satisfy the vector timing constraint:

[0121]

[0122] Therefore, there are multiple timing sequences for A-phase parallel branch switches that satisfy the above constraints, including but not limited to:

[0123]

[0124] Mode The rate of change of the single-phase circulating current in phase A is 0→0→0→1→0→0→0→0→0→-1→0→0→0 or 0→0→0→-1→0→0→0→0→0→1→0→0→0. The rate of change of the single-phase circulating current in both phases satisfies that the total change is zero. At the same time, the rate of change of the circulating current in the second half-carrier period is equal in value and opposite in sign to the rate of change of the circulating current in the first half-cycle.

[0125] The sum of the number of conducting tubes in the two parallel branches of phase B must satisfy the vector timing constraint:

[0126]

[0127] Therefore, there are multiple timing sequences for the B-phase parallel branch switches that satisfy the above constraints, including but not limited to:

[0128]

[0129] Mode The rate of change of the single-phase circulating current in phase B is 1→1→0→0→0→-1→-1→-1→0→0→0→1→1 or -1→-1→0→0→0→1→1→1→0→0→0→1→1. The rate of change of the single-phase circulating current in both phases satisfies that the total change is zero. At the same time, the rate of change of the circulating current in the second half-carrier period is equal in value and opposite in sign to the rate of change of the circulating current in the first half-cycle.

[0130] The sum of the number of conducting tubes in the two parallel branches of phase C must satisfy the vector timing constraint:

[0131]

[0132] Therefore, there are multiple timing sequences for C-phase parallel branch switches that satisfy the above constraints, including but not limited to:

[0133]

[0134] Mode The rate of change of the single-phase circulating current in phase C is -1→0→0→0→0→0→1→0→0→0→0→0→-1 or 1→0→0→0→0→0→-1→0→0→0→0→0→1. The rate of change of the single-phase circulating current in both phases satisfies that the total change is zero. At the same time, the rate of change of the circulating current in the second half-carrier period is equal in value and opposite in sign to the rate of change of the circulating current in the first half-cycle.

[0135] Finally, by arbitrarily combining the switching timings of the above phases, we can obtain the switching timing of one of the three-phase parallel branches that satisfies the constraints:

[0136]

[0137] Mode The rate of change of the zero-sequence circulating current is 0→1→0→1→0→-1→0→-1→0→-1→0→1→0, and the total change of the zero-sequence circulating current is zero. At the same time, the rate of change of the circulating current in the second half-carrier period is equal in value and opposite in sign to the rate of change of the circulating current in the first half-carrier period, which meets the above constraints.

[0138] In summary, the switching timing construction method is as follows: the switching timing of each parallel branch must not only follow the constraints of the corresponding phase vector timing, but also satisfy the requirement that the circulating current change rate in the second half of a carrier cycle is equal in value and opposite in sign to the circulating current change rate in the first half of a carrier cycle. After listing them one by one, each basic sector has 64 switching timing sequences, therefore, there are a total of 64 × 6 = 384 switching timing sequences in the entire vector plane.

[0139] (3) Based on the aforementioned switching timing, and considering that each sub-sector has a redundant sequence, the switching timing and its redundant single-phase circulating current peak values ​​are compared and analyzed. The optimal switching timing is then determined within each sub-sector. Ultimately, each basic sector is divided into 7 sub-sectors, such as... Figure 4 Specifically, this includes:

[0140] First, based on the switching sequence listed above, combined with the formula The defined expression for the rate of change of a single-phase circulation can be used to calculate the time-domain expression for the single-phase circulation of each phase. (Equation follows) Taking the listed switching sequence as an example, the time-domain expression of the single-phase circulating current in each phase is as follows:

[0141]

[0142] Among them, t1, t7, t 13 Corresponding voltage vectors V1, V7, V 13 In the synthesized reference voltage vector V ref (like Figure 3 The time each occupies.

[0143] Secondly, the duration of each voltage vector can be calculated based on the volt-second balance principle:

[0144]

[0145] Among them, V 1α and V 1β This represents the components of the basic voltage vector V1 in a two-phase stationary coordinate system; V 7α and V 7β This represents the component of the basic voltage vector V7 in a two-phase stationary coordinate system; V 13αand V 13β Represents the basic voltage vector V 13 Components in a two-phase stationary coordinate system; V rα and V rβ Represents the reference voltage vector V ref Components in a two-phase stationary coordinate system.

[0146] Furthermore, for the reference voltage vector V in the two-phase stationary coordinate system rα and V rβ It can be represented by the modulation index M and the reference voltage in the equivalent vector plane diagram as vector angle θ:

[0147]

[0148] Where the modulation index M=2|V ref | / V DC ,|V ref | represents the magnitude of the reference voltage vector.

[0149] Finally, the combined form ~style The expression for the peak value of the single-phase circulating current in the above switching sequence can be obtained as follows:

[0150]

[0151] Similarly, the peak values ​​of other switching sequences and redundancies of single-phase circulating current can be calculated. By comparing the peak values ​​of each switching sequence and its redundancy, the optimal modulation region within the basic sector I that maximizes the peak value of the single-phase circulating current can be obtained, such as... Figure 4 As shown.

[0152] Figure 4 In this model, basic sector I is further divided into 7 sub-sectors. The range expression for each sub-sector is as follows:

[0153]

[0154] Based on the derived expressions for the range of each sub-sector within the basic sector I, extending these expressions to the entire vector plane yields the following expressions for the range of each sub-sector:

[0155]

[0156] in, . These are the per-unit values ​​of the three-phase reference voltage vectors, with a per-unit reference value of V. DC .

[0157] The optimal switching timing selected for each sub-sector is shown in Table 3. In the table, the values ​​in parentheses represent the zero-sequence circulating current rate of change in V. DC / (2L1) is the value after normalization based on the base value. It should be noted that swapping the switching sequences between the two converters in the table can also yield the optimal switching sequence. The only difference between these two optimal switching sequences is the sign of the circulating current rate of change; the output current ripple performance and circulating current peak value remain unchanged. Therefore, it is sufficient to select one of the optimal switching sequences.

[0158] Table 4 Optimal Switching Timing within Basic Sector I

[0159]

[0160] (4) Generate a modulation wave and construct a carrier modulation scheme based on the optimal switching timing, specifically including:

[0161] First, to generate the optimal switching timing, a comparison method between the modulation wave and the carrier wave needs to be designed, i.e., a switching action mode. The carrier wave is a sawtooth wave, with one type being an incrementing sawtooth carrier that uses an incrementing count, resetting to zero after reaching a set period value and entering the next period; the other type is a decrementing sawtooth carrier that uses a decrementing count, decreasing from the set period value to zero, then resetting to the set period value and entering the next period. Based on the optimal switching timing, this invention proposes six switching action modes, defined as ActionA to ActionF, as follows: Figure 5 As shown.

[0162] When the switching timing is not symmetrical about half the carrier period within one carrier period, the corresponding branch compares one carrier wave with two modulation waves, where modulation wave 2 is greater than modulation wave 1. There are four operating modes:

[0163] Action A: When the carrier is an incremental sawtooth carrier, if modulation wave 1 is greater than or equal to the incremental sawtooth carrier, or modulation wave 2 is less than or equal to the incremental sawtooth carrier, then the upper arm switch of the corresponding branch is turned on and the lower arm switch is turned off.

[0164] Action B: When the carrier is a decreasing sawtooth carrier, if modulation wave 1 is greater than or equal to the decreasing sawtooth carrier, or modulation wave 2 is less than or equal to the decreasing sawtooth carrier, then the upper arm switch of the corresponding branch is turned on and the lower arm switch is turned off.

[0165] ActionC: When the carrier is an incremental sawtooth carrier, if modulation wave 1 is less than or equal to the incremental sawtooth carrier and modulation wave 2 is greater than or equal to the incremental sawtooth carrier, then the upper arm switch of the corresponding branch is turned on and the lower arm switch is turned off.

[0166] ActionD: When the carrier is a decreasing sawtooth carrier, if modulation wave 1 is less than the decreasing sawtooth carrier and modulation wave 2 is greater than the decreasing sawtooth carrier, then the upper arm switch of the corresponding branch is turned on and the lower arm switch is turned off.

[0167] When the switching timing is symmetrical about half of the carrier period within one carrier period, the corresponding branch uses a modulated wave to compare with two carriers, and its operation mode is twofold:

[0168] ActionE: When the modulated wave is greater than both the increasing sawtooth carrier and the decreasing sawtooth carrier, the upper arm switch of the corresponding branch is turned on and the lower arm switch is turned off.

[0169] ActionF: When the modulated wave is greater than both the increasing sawtooth carrier and the decreasing sawtooth carrier, the upper arm switch of the corresponding branch is turned off and the lower arm switch is turned on.

[0170] Secondly, the corresponding modulation wave expression is calculated based on the optimal switching timing. Taking the optimal switching timing SQ1 of sub-sector 1 within basic sector I as an example, based on the volt-second balance principle, the expressions for the duty cycles of each vector used in this switching timing can be obtained as follows:

[0171]

[0172] Finally, based on the calculated vector duty cycle expressions, the modulation wave expression and corresponding operating modes are derived. The modulation wave expression and corresponding operating modes of the optimal switching timing SQ1 are as follows:

[0173]

[0174] Among them, u m-a1 and u m-a2 Corresponding to the two modulated waves on phase A, u m-b1 and u m-b2 The two modulated waves correspond to phase B; u m-c1 and u m-c2 The two modulated waves corresponding to phase C; u* a u* b and u* c They represent V respectively DC The three-phase voltage per unit value is used as the reference. ActionC and ActionD indicate the switching operation mode.

[0175] Based on the same method described above, the modulation wave expressions and corresponding action modes of other sub-sectors within basic sector I and each sub-sector within the remaining basic sectors can be derived. Finally, the results can be extended to the entire vector plane, and their modulation wave expressions and corresponding action modes are summarized as follows:

[0176]

[0177]

[0178]

[0179]

[0180] Among them, u m-max1 and u m-max2 This represents the two modulating waves of the maximum phase of the three-phase voltage; u m-mid1 and u m-mid2 This represents the two modulation waves of the intermediate phase of a three-phase voltage; u m-min1 and u m-min2 This represents the two modulating waves of the least phase of a three-phase voltage; u* max u* mid and u* min They represent V respectively DC The per-unit values ​​of the three-phase voltages, including the maximum, intermediate, and minimum phases, are used as the reference. ActionA to ActionF represent the switching operation modes. Numbers 1 to 7 correspond to the sub-sector numbers, respectively.

[0181] (5) Based on the designed optimal switching timing, the carrier is flipped within two adjacent carrier cycles, so that the switching signals of the same bridge arm form equivalent symmetry within two carrier cycles. Specifically, this includes:

[0182] Normally, the switching timing is symmetrical about half the period within a single carrier cycle, and its average circulating current is zero. However, the switching timing constructed in this invention is asymmetrical within a single carrier cycle. Therefore, this invention proposes a method to achieve equivalent timing symmetry over two carrier cycles: alternating between increasing and decreasing sawtooth carriers in adjacent carrier cycles, so that the switching timing of two adjacent carrier cycles is symmetrical about the two carrier cycles.

[0183] Taking the optimal switching timing of sub-sector 1 within basic sector I as an example, Figure 6The switching timing waveforms and their A-phase single-phase circulating current and zero-sequence circulating current waveforms are listed. As shown in the figure, the three-phase switching signals are not symmetrical about half the carrier period, the positive and negative areas of the circulating current cannot cancel each other out, and their average value is not zero. The specific implementation of the method is as follows:

[0184] like Figure 6 As shown, the original timing V0 (V) is used in the k-th carrier period. 000 / V 000 -V 13 (V) 100 / V 000 -V 14 (V) 100 / V 010 -V0(V 100 / V 011 -V 14 (V) 100 / V 010 -V 13 (V) 100 / V 000 -V0(V 000 / V 000 -V 13 (V) 000 / V 100 -V 14 (V) 010 / V 100 -V0(V 011 / V 100 -V 14 (V) 010 / V 100 -V 13 (V) 000 / V 100 -V0(V 000 / V 000 The first converter uses an increasing sawtooth carrier, and the second converter uses a decreasing sawtooth carrier. The switching operation mode of phases A, B, and C of the first converter is ActionC, and the switching operation mode of phases A, B, and C of the second converter is ActionD. In the (k+1)th carrier cycle, after the carrier is flipped, the first converter uses a decreasing sawtooth carrier, and the second converter uses an increasing sawtooth carrier, reversing the original sequence to V0 (V 000 / V 000 -V 13 (V) 000 / V 100 -V 14 (V) 010 / V 100 -V0(V 011 / V 100 -V14 (V) 010 / V 100 -V 13 (V) 000 / V 100 -V0(V 000 / V 000 -V 13 (V) 100 / V 000 -V 14 (V) 100 / V 010 -V0(V 100 / V 011 -V 14 (V) 100 / V 010 -V 13 (V) 100 / V 000 -V0(V 000 / V 000 The switching operation mode of phases A, B, and C of the first converter is changed to ActionD, and the switching operation mode of phases A, B, and C of the second converter is changed to ActionC. This method achieves equivalent symmetry of the switching signals of each phase within two carrier cycles by flipping the carrier wave, allowing the positive and negative areas of the circulating current to cancel each other out, ultimately making the average value of the circulating current approximately zero.

[0185] The same method is used to suppress low-frequency circulating current in the switching timing of other sectors. The method is summarized as follows: taking two adjacent carrier cycles as an adjustment period, in the k-th carrier cycle, the first converter uses an increasing sawtooth carrier and the second converter uses a decreasing sawtooth carrier, generating a switching signal based on a preset switching operation mode; in the k+1-th carrier cycle, the corresponding carriers used by the two converters are flipped, that is, the first converter uses a decreasing sawtooth carrier and the second converter uses an increasing sawtooth carrier, exchanging the operation modes of the corresponding phases of the two converters, realizing the equivalent symmetry of the switching signal of the same bridge arm, and finally achieving that the average circulating current of the proposed timing is approximately zero in two carrier cycles.

[0186] (6) To address the low-frequency single-phase circulating current caused by inconsistent parallel inductor parameters, a duty cycle adjustment is introduced into the unbalanced phase modulation signal to suppress the low-frequency single-phase circulating current introduced by inductor inconsistency. Specifically, this includes:

[0187] In practical engineering applications, inconsistencies in inductor parameters are unavoidable due to manufacturing errors, leading to the introduction of low-frequency circulating currents. As analyzed above, these low-frequency circulating currents can be categorized into low-frequency single-phase circulating currents and low-frequency zero-sequence circulating currents. Existing methods for suppressing low-frequency zero-sequence circulating currents rely on introducing a compensating voltage difference with an amplitude equal to but opposite phase to the common-mode voltage difference caused by the unbalanced inductance, thereby suppressing the low-frequency zero-sequence circulating current. However, to avoid sacrificing the characteristics of single-phase circulating currents, this invention proposes further suppressing low-frequency circulating currents by individually controlling the single-phase circulating current. Therefore, precise control of the single-phase voltage difference becomes crucial for suppressing low-frequency single-phase circulating currents.

[0188] Based on Kirchhoff's laws, the expression for the voltage difference between each phase arm of two parallel converters, i.e., the single-phase voltage difference, is derived as follows:

[0189]

[0190] In the formula, Δu ipccx (x=a,b,c) represents the single-phase pressure difference; L dev-x (x=a,b,c) represents the deviation of each phase inductance from the nominal inductance L1; L diff-x (x=a,b,c) represents the inductance difference between each phase; i ipccx This indicates a single-phase circulating current.

[0191] Furthermore, since the single-phase voltage difference can also be expressed as the difference in duty cycles of each phase and the DC bus voltage V, dc Expressed as a product, controlling the single-phase pressure difference can be further simplified to controlling the duty cycle difference between each phase. Substituting the above relationship into the equation... A mathematical model can be obtained between the single-phase duty cycle adjustment of the two parallel converters and the low-frequency single-phase circulating current:

[0192]

[0193] In the formula, u forward-x (x=a,b,c) are feedforward compensation terms that satisfy:

[0194]

[0195] At the same time, the formula The single-phase voltage difference caused by inductor imbalance can be compensated by feedforward control. Therefore, according to the formula... The transfer function between the duty cycle adjustment and the low-frequency single-phase circulating current can be derived as follows:

[0196]

[0197] According to the formula The present invention further proposes a control block diagram for suppressing low-frequency single-phase circulating current, such as... Figure 7 As shown: First, a proportional resonant controller is used, with the difference between the actual value of the low-frequency single-phase circulating current obtained by sampling and the zero reference value as input. The duty cycle adjustment of the two parallel branches of the corresponding phase is output using the feedforward compensation method. Then, the duty cycle adjustment is superimposed on the modulation stage. Based on the original duty cycle of the two parallel branches of the three phases, the duty cycle adjustment is subtracted from one branch and added to the other branch, thus finally realizing the suppression of low-frequency single-phase circulating current.

[0198] Furthermore, since there is a certain correspondence between the modulation wave and the duty cycle, the adjustment of the original duty cycle of the two parallel branches of the three-phase system can be equivalently transformed into the adjustment of the original modulation wave of the two parallel branches of the three-phase system, that is, injecting a single-phase duty cycle adjustment signal on the basis of the original modulation wave. At the same time, since there are two comparison methods between the carrier wave and the modulation wave, the injection method needs to be divided into two types:

[0199] For a method that compares one carrier wave with two modulated waves, it is necessary to inject one modulated wave into each of the two converters:

[0200]

[0201] For a method that compares two carrier waves and a modulated wave, the modulated waves of both converters need to be injected separately:

[0202]

[0203] Finally, taking the optimal switching timing SQ1 of sub-sector 1 within basic sector I as an example, assuming that the A-phase inductor is in an unbalanced operating condition, the control method for suppressing the low-frequency circulating current introduced by the unbalanced inductor is adopted, and its specific implementation is as follows: Figure 8 As shown. Since only phase A has inductive imbalance, only the duty cycle adjustment needs to be injected into the modulation signal of that phase. Simultaneously, the switching signal of that phase is generated by comparing a carrier wave with two modulation waves. Therefore, the injection method for the modulation wave of phase A is as shown in the equation. As shown. The specific injection method is as follows: the modulation wave u of the first converter m-ma1 The modulated wave u remains unchanged. m-ma2 Injection duty cycle adjustment amount + Δd a The modulation wave of the second converter u m-ma1 The modulated wave u remains unchanged. m-ma2 Injection duty cycle adjustment amount - Δd a It should be noted that the injection methods for two adjacent carrier cycles are exactly the same. Figure 8 The proposed method injects a duty cycle adjustment into the modulation wave of phase A, thereby generating a low-frequency single-phase voltage difference in phase A. This single-phase voltage difference can cancel out the low-frequency single-phase voltage difference introduced by the unbalanced inductance, ultimately suppressing the low-frequency single-phase circulating current caused by the unbalanced inductance in this phase. Meanwhile, the modulation waves of phases B and C are not adjusted; therefore, the single-phase circulating current in the balanced phase is not worsened.

[0204] In summary, the proposed duty cycle injection method generates a low-frequency single-phase voltage difference in the unbalanced phase, thereby suppressing the low-frequency single-phase circulating current without disrupting the single-phase circulating current in the balanced phase. Furthermore, it should be noted that the duty cycle adjustment Δd is extremely small and does not disrupt the original switching sequence. Therefore, this injection method preserves the original ripple-optimal vector timing structure to the greatest extent possible. Applying this method to the entire vector plane yields the following specific injection method:

[0205]

[0206] Among them, u m-max The modulation wave corresponding to the maximum phase of the three-phase reference voltage, u m-mid The modulation wave corresponding to the intermediate phase of the three-phase reference voltage, u m-min The modulation wave corresponds to the minimum phase of the three-phase reference voltage; #1 corresponds to the first converter, #2 corresponds to the second converter, and numbers 1 to 7 correspond to the sub-sector numbers respectively; Δd max , Δd max and Δd min These correspond to the duty cycle adjustments required for the maximum phase, intermediate phase, and minimum phase, respectively.

[0207] Finally, simulations were used to verify the effectiveness of the modulation algorithm proposed in this invention and the effectiveness of the method for suppressing low-frequency circulating current introduced by inductor imbalance. The simulation parameters are shown in the table below.

[0208] Table 4 Simulation parameters under equilibrium conditions

[0209]

[0210] The simulation primarily demonstrates the simulation results of the optimal ripple modulation method for single-phase circulating current suppression in a two-parallel converter proposed in this invention. The simulation mainly considers three typical inductor imbalances: single-phase inductor imbalance, two-phase inductor imbalance, and three-phase inductor imbalance, where both inductors in each phase deviate from their nominal values. Simultaneously, to verify that the proposed method can handle severely unbalanced operating conditions, a ±50% imbalance case, i.e., L... x1 (=2.5mH) is up to 50% lower than the nominal inductance L1 (=5mH), L x2 (=7.5mH) is up to 50% higher than the nominal inductance L1 (=5mH). Figure 9The waveforms are simulation results obtained by the optimal ripple modulation method proposed in this invention under inductor balance conditions at a modulation depth of 0.8. Figure 9 In the middle (a)~(c), the three-phase parallel current, the single-phase circulating current waveform of phase A, and the zero-sequence circulating current waveform are respectively obtained by the proposed optimal ripple modulation method; Figures 10-16 The waveforms are simulation results obtained by the proposed optimal ripple modulation method under the above three inductor imbalance conditions at a modulation depth of 0.8. Figure 10 (a) to (e) show the dynamic processes of the three-phase parallel current waveform, single-phase circulating current in phase A, single-phase circulating current in phase B, single-phase circulating current in phase C, and zero-sequence circulating current waveform before and after the proposed single-phase circulating current control method is switched on when the inductance of phase A is unbalanced. Figure 11 In the middle (a) to (d), the circulating current spectra of phase A, phase B, phase C, and zero-sequence circulating current of the two parallel converters are respectively, when the proposed single-phase circulating current control method is not applied and phase A inductance is unbalanced. Figure 11 In the middle (e)~(h), the circulating current spectra of the two parallel converters at frequencies of 0Hz~700Hz are respectively the circulating current spectra of phase A, phase B, phase C and zero sequence circulating current spectra of phase A, after the proposed single-phase circulating current control method is applied when the inductance of phase A is unbalanced. Figure 12 (a) to (e) show the dynamic processes of the three-phase parallel current waveform, single-phase circulating current of phase A, single-phase circulating current of phase B, single-phase circulating current of phase C, and zero-sequence circulating current waveform before and after the proposed single-phase circulating current control method is switched on when the inductances of phases A and B are unbalanced. Figure 13 In the middle (a) to (d), the circulating current spectra of phase A, phase B, phase C, and zero-sequence circulating current of the two parallel converters at frequencies of 0Hz to 700Hz are respectively, when the inductances of phases A and B are unbalanced and the proposed single-phase circulating current control method is not applied. Figure 13 In the middle (e) to (h), the A-phase circulating current spectrum, B-phase circulating current spectrum, C-phase circulating current spectrum and zero-sequence circulating current spectrum of the two parallel converters after switching on the proposed single-phase circulating current control method when the inductance of the A and B phases is unbalanced are respectively. Figure 14 (a) to (e) show the dynamic processes of the three-phase parallel current waveform, single-phase circulating current of phase A, single-phase circulating current of phase B, single-phase circulating current of phase C, and zero-sequence circulating current waveform before and after the proposed single-phase circulating current control method is applied when the three-phase inductors of phases A, B, and C are all unbalanced. Figure 15 In the middle (a) to (d), the circulating current spectra of phase A, phase B, phase C, and zero-sequence circulating current of the two parallel converters are respectively, when the three-phase inductors of phases A, B, and C are unbalanced and the proposed single-phase circulating current control method is not applied. Figure 15In the middle (e) to (h), the A-phase circulating current spectrum, B-phase circulating current spectrum, C-phase circulating current spectrum and zero-sequence circulating current spectrum of the two parallel converters after the proposed single-phase circulating current control method is applied when the inductors of the three phases ABC are unbalanced. Figure 16 In the figures (a) to (c), the three-phase parallel current spectra of the two parallel converters at frequencies from 0Hz to 20kHz are respectively, when the proposed single-phase circulating current control method is not applied under the three inductance imbalance conditions mentioned above. Figure 16 In the middle (d) to (f), the three-phase parallel current spectra of the two parallel converters at frequencies of 0Hz to 20kHz are respectively after switching to the proposed single-phase circulating current control method under the above three inductance imbalance conditions.

[0211] As can be seen from the simulation results, the modulation algorithm proposed in this invention achieves optimal output current ripple on the one hand, and on the other hand, effectively suppresses the low-frequency components of single-phase / zero-sequence circulating current to near zero in response to the low-frequency circulating current problem introduced by inductor imbalance. At the same time, the original optimal ripple vector timing structure is preserved, which proves that the proposed modulation method maintains its original optimal ripple performance while suppressing low-frequency circulating current.

[0212] This embodiment also provides an optimal modulation device for ripple of two parallel converters for single-phase circulating current suppression, comprising:

[0213] The optimal vector timing set construction unit, based on the equivalent vector plane of two parallel converters, constructs the optimal vector timing set for parallel output current ripple according to the principle of near three-vector synthesis and the principle of non-clamping sequence construction. The optimal vector timing set includes multiple vector timing arrangement methods.

[0214] The optimal switching timing determination unit generates a switching timing sequence based on the optimal vector timing sequence set and its corresponding switching combination, and determines the optimal switching timing sequence within each basic sector and its sub-sectors with the optimization objective of minimizing the peak value of the single-phase circulating current.

[0215] The modulation wave generation and carrier modulation scheme determination unit generates a modulation wave and constructs a carrier modulation scheme according to the optimal switching timing.

[0216] The suppression optimization unit achieves equivalent symmetry of the switching signals of the same bridge arm within two carrier cycles by flipping the carrier in adjacent carrier cycles. To address the low-frequency single-phase circulating current caused by inconsistent parallel inductor parameters, a duty cycle adjustment is introduced into the unbalanced phase modulation signal to suppress the low-frequency single-phase circulating current caused by inductor inconsistency. Under the condition of single-phase duty cycle adjustment, the optimal vector timing structure of ripple is preserved to the greatest extent.

[0217] This embodiment also provides a device for optimal modulation of ripple in two parallel converters, including: a memory, a processor, and a computer program stored in the memory. When the processor executes the computer program, it implements the steps of the optimal modulation method for ripple in two parallel converters.

[0218] This embodiment also provides a computer storage medium storing an executable program, which is executed by a processor to implement the steps of the optimal modulation method for ripple of two parallel converters.

[0219] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A method for optimal modulation of ripple in two parallel converters for single-phase circulating current suppression, characterized in that, include: Based on the equivalent vector plane of two parallel converters, and following the principle of near three-vector synthesis and the principle of non-clamping sequence construction, an optimal vector timing set for parallel output current ripple is constructed. The optimal vector timing set includes multiple vector timing arrangement methods. Based on the optimal vector timing set and its corresponding switch combination, a switching timing sequence is generated, and within each basic sector and its sub-sectors, the optimal switching timing sequence is determined with the optimization objective of minimizing the peak value of the single-phase circulating current. Generate a modulation wave and construct a carrier modulation scheme based on the optimal switching timing; By flipping the carrier within adjacent carrier cycles, the switching signals of the same bridge arm are made equivalently symmetrical within two carrier cycles. To address the low-frequency single-phase circulating current caused by inconsistent parallel inductor parameters, a duty cycle adjustment is introduced into the unbalanced phase modulation signal to suppress the low-frequency single-phase circulating current caused by inductor inconsistency. Under the condition of single-phase duty cycle adjustment, the optimal vector timing structure of ripple is preserved to the greatest extent. The principles of near-three-vector synthesis and non-clamp sequence construction are as follows: The voltage vector plane is divided into six equal basic sectors, each of which is further divided into four sub-sectors. Each sub-sector is an equilateral triangle with an equal area, and the vertices of each triangle are formed by three basic voltage vectors and their corresponding redundant voltage vectors. Within each sub-sector, a vertex voltage vector of the equilateral triangle or its corresponding redundant voltage vector is selected as the starting voltage vector. A voltage vector sequence is constructed by sequentially increasing or decreasing the total number of conducting devices in the three-phase parallel branches according to phase sequence. After the number of conducting devices in all three phases has changed once, the sequence returns to the starting voltage vector. Another redundant voltage vector corresponding to the initial voltage vector forms a four-segment asymmetric vector sequence containing four voltage vectors; taking the end voltage vector of the four-segment asymmetric vector sequence as the center of symmetry, the four-segment asymmetric vector sequence is mirrored and expanded to obtain a symmetric non-clamped vector timing basic unit containing seven voltage vectors; the symmetric non-clamped vector timing basic unit is repeated twice, and the first and last voltage vectors of adjacent basic units are the same, forming a complete non-clamped vector timing sequence containing 13 voltage vectors, wherein each switching device only turns on once and turns off once within a single carrier cycle; The optimal vector timing set for constructing parallel output current ripple is as follows: For the same starting voltage vector, two different non-clamping vector timing sequences are constructed due to the different phase sequences corresponding to the changes in the number of conductions. The voltage vectors at the three vertices of the equilateral triangle are all used as starting voltage vectors. Each basic sector constructs 14 non-clamping vector timing sequences, and the entire voltage vector plane constructs a total of 84 non-clamping vector timing sequences.

2. The optimal modulation method for ripple of two parallel converters for single-phase circulating current suppression according to claim 1, characterized in that, The switching timing is specifically generated by generating a switching timing based on the switching combination corresponding to each vector in the optimal vector timing set. Among them, one vector timing corresponds to multiple switching timings, each basic sector has 64 switching timings, and there are a total of 384 switching timings in the entire vector plane.

3. The optimal modulation method for ripple of two parallel converters for single-phase circulating current suppression according to claim 1, characterized in that, The determination of the optimal switching sequence specifically involves: within each sub-sector, comparing the single-phase circulating current peak values ​​corresponding to candidate switching sequences and their redundant sequences based on the position change of the reference voltage vector, and selecting the switching sequence with the smallest single-phase circulating current peak value as the optimal switching sequence for that position; according to the distribution law of the optimal switching sequence with the position of the reference voltage vector, each basic sector is divided into 7 sub-sectors, and each sub-sector corresponds to an optimal switching sequence, so as to achieve the minimum single-phase circulating current peak value in the entire vector plane.

4. The optimal modulation method for ripple of two parallel converters for single-phase circulating current suppression according to claim 1, characterized in that, The carrier modulation scheme specifically includes: the carrier is a sawtooth wave, one type of carrier is an incremental sawtooth carrier, which uses an incremental counting method, and after reaching a set period value, it is cleared to zero and enters the next period; the other type of carrier is a decremental sawtooth carrier, which uses a decremental counting method, which starts from the set period value, decreases to zero, and after being reassigned to the period value, it enters the next period. When the switching timing is not symmetrical about 1 / 2 of the carrier period within one carrier period, the corresponding branch compares one carrier with two modulated waves to generate the corresponding switching signal; when the switching timing is symmetrical about 1 / 2 of the carrier period within one carrier period, the corresponding branch compares one modulated wave with two carriers to generate the corresponding switching signal. The specific steps for generating the modulation wave based on the optimal switching timing are as follows: based on the conduction state of each parallel branch switching device in the optimal switching timing, the duty cycle of each vector is equivalently converted into the conduction duty cycle of each parallel branch; and combined with the carrier modulation scheme and the corresponding switching operation mode, the modulation wave expression for realizing the optimal switching timing under the corresponding carrier and switching operation mode is derived.

5. The optimal modulation method for ripple of two parallel converters for single-phase circulating current suppression according to claim 4, characterized in that: The switching operation mode specifically includes the following: when comparing one carrier wave with two modulated waves: When the carrier is an incremental sawtooth carrier, if modulation wave 1 is greater than or equal to the incremental sawtooth carrier, or modulation wave 2 is less than or equal to the incremental sawtooth carrier, or modulation wave 1 is less than or equal to the incremental sawtooth carrier and modulation wave 2 is greater than or equal to the incremental sawtooth carrier, then the upper bridge arm switch of the corresponding branch is turned on and the lower bridge arm switch is turned off. When the carrier is a decreasing sawtooth carrier, if modulation wave 1 is greater than or equal to the decreasing sawtooth carrier, or modulation wave 2 is less than or equal to the decreasing sawtooth carrier, or modulation wave 1 is less than or equal to the decreasing sawtooth carrier and modulation wave 2 is greater than or equal to the decreasing sawtooth carrier, then the upper bridge arm switch of the corresponding branch is turned on and the lower bridge arm switch is turned off. In this context, the modulation wave 2 is greater than the modulation wave 1.

6. The optimal modulation method for ripple of two parallel converters for single-phase circulating current suppression according to claim 4, characterized in that: The specific switching operation modes of the corresponding branch when comparing a modulated wave with two carrier waves include: When the modulated wave is simultaneously greater than or equal to the increasing sawtooth carrier and the decreasing sawtooth carrier, the upper bridge arm switch of the corresponding branch is turned on and the lower bridge arm switch is turned off. When the modulated wave is simultaneously greater than or equal to both the increasing sawtooth carrier and the decreasing sawtooth carrier, the upper arm switch of the corresponding branch is turned off, and the lower arm switch is turned on.

7. The optimal modulation method for ripple of two parallel converters for single-phase circulating current suppression according to claim 4, characterized in that, The carrier flipping method within adjacent carrier periods is as follows: For asymmetric switching timing within a unit carrier period, incremental sawtooth carriers and decremental sawtooth carriers are alternately used in adjacent carrier periods to make the switching timing of two adjacent carrier periods symmetrical about the center of the two carrier periods.

8. The optimal modulation method for ripple of two parallel converters for single-phase circulating current suppression according to claim 1, characterized in that, To address the low-frequency single-phase circulating current caused by inconsistent parallel inductor parameters, a closed-loop control is implemented using a proportional resonant controller. The difference between the sampled actual value of the low-frequency single-phase circulating current and the zero reference value is used as input, and the output is the duty cycle adjustment for the two parallel branches of the corresponding phase. This duty cycle adjustment is superimposed on the modulation stage. Based on the original duty cycles of the two parallel branches of the three phases, one branch has the duty cycle adjustment subtracted, and the other branch has the duty cycle adjustment added, thereby achieving low-frequency single-phase circulating current suppression.

9. A device for optimal modulation of ripple in two parallel converters for single-phase circulating current suppression, characterized in that, The optimal modulation method for ripple of two parallel converters according to any one of claims 1-8 includes: The optimal vector timing set construction unit, based on the equivalent vector plane of two parallel converters, constructs the optimal vector timing set for parallel output current ripple according to the principle of near three-vector synthesis and the principle of non-clamping sequence construction. The optimal vector timing set includes multiple vector timing arrangement methods. The optimal switching timing determination unit generates a switching timing sequence based on the optimal vector timing sequence set and its corresponding switching combination, and determines the optimal switching timing sequence within each basic sector and its sub-sectors with the optimization objective of minimizing the peak value of the single-phase circulating current. The modulation wave generation and carrier modulation scheme determination unit generates a modulation wave and constructs a carrier modulation scheme according to the optimal switching timing. The suppression optimization unit achieves equivalent symmetry of the switching signals of the same bridge arm within two carrier cycles by flipping the carrier in adjacent carrier cycles. To address the low-frequency single-phase circulating current caused by inconsistent parallel inductor parameters, a duty cycle adjustment is introduced into the unbalanced phase modulation signal to suppress the low-frequency single-phase circulating current caused by inductor inconsistency. Under the condition of single-phase duty cycle adjustment, the optimal vector timing structure of ripple is preserved to the greatest extent.

10. A device for optimal modulation of ripple in two parallel converters, characterized in that, include: A memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the optimal modulation method for ripple of two parallel converters as described in any one of claims 1-8.

11. A computer storage medium, characterized in that, The computer storage medium stores an executable program, which is executed by a processor to implement the steps of the optimal modulation method for ripple of two parallel converters as described in any one of claims 1-8.

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