Amplifier circuits, adaptive compensation methods and electronic devices

Abstract

This invention provides an amplifier circuit, an adaptive compensation method, and an electronic device. The amplifier circuit includes: a current-mode logic amplifier module that switches the current branch based on the differential input signal to amplify the signal; a negative resistive load module for increasing the voltage gain of the current-mode logic amplifier module; and a bias current generation module that provides a compensated bias current to the negative resistive load module. The compensated bias current is used to compensate for gain fluctuations in the negative resistive load module caused by process variations and / or temperature changes. The amplifier circuit, adaptive compensation method, and electronic device of this invention fundamentally suppress the gain sensitivity of the current-mode logic amplifier to temperature and process variations; they enable real-time, adaptive, and low-overhead compensation technology at the analog domain front end, stabilizing receiver link performance and reducing bit error rate, ensuring stable and reliable performance of the high-speed receiver under various operating conditions.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an amplifier circuit, an adaptive compensation method, and an electronic device. Background Technology

[0002] In modern high-speed wired and wireless communication systems, such as data center interconnects (400G / 800G Ethernet), 5G fronthaul / backhaul, and RF microwave links, receiver sensitivity and signal integrity are crucial to overall system performance. As a core gain module in the receiver link front-end, current-mode logic (CML) amplifiers are widely used in signal amplification and clock / data recovery circuits in these scenarios due to their inherent high bandwidth, low noise, and excellent differential interference immunity.

[0003] However, the performance of CML amplifiers, especially their voltage gain, faces significant challenges in deep submicron and nanometer-scale integrated circuit processes. These challenges primarily stem from two uncontrollable physical variables: operating temperature variations and semiconductor manufacturing process deviations. Regarding operating temperature, chip ambient temperatures can fluctuate within an industrial range of -40°C to +125°C, or even wider. Temperature variations directly alter key parameters such as transistor carrier mobility and threshold voltage, leading to changes in the transconductance and load impedance of the CML differential pair, resulting in significant gain drift. In terms of manufacturing processes, despite the use of advanced process design kits (PDKs), unavoidable microscopic deviations in processes such as photolithography, etching, and ion implantation cause fluctuations in parameters such as transistor size and oxide layer thickness both within and between wafers. This shift in process corner can cause unpredictable deviations between the actual gain of different batches or even different CML core units on the same chip and their design specifications. Gain instability can trigger a series of system-level performance degradations. In receiver architectures employing Continuous-Time Linear Equalizers (CTLEs) or Variable Gain Amplifiers (VGAs), the CML amplifier is typically the first or critical stage in the equalization link. Unexpected gain drift in the CML amplifier directly alters the amplitude response of the entire equalizer, causing a significant change in the preset equalization capability. This change makes it impossible for the receiver to stably cancel inter-symbol interference (ISI) introduced by the channel, manifesting as eye diagram closure in high-speed data transmission, ultimately leading to an increase in the bit error rate (BER), and in severe cases, even causing link training failure or communication interruption.

[0004] Currently, common solutions in the industry include: performing periodic parameter recalibration at the system level, or using digital-assisted analog circuits with high power consumption and area overhead (such as gain compensation based on lookup tables). While these methods have some effectiveness, they suffer from drawbacks such as slow response speed, increased system complexity, consumption of digital resources, or introduction of additional power consumption.

[0005] Therefore, there is an urgent need for a compensation technique that can achieve real-time, adaptive, and low-overhead performance at the analog domain front end, fundamentally suppressing the sensitivity of CML amplifier gain to temperature and process, thereby ensuring that high-speed receivers can maintain stable and reliable performance under various operating conditions.

[0006] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an amplifier circuit, an adaptive compensation method, and an electronic device to solve the problems of slow response speed, increased system complexity, occupation of digital resources, or introduction of additional power consumption when compensating for the gain drift and unstable equalization capability of CML amplifiers caused by temperature changes and process deviations.

[0008] To achieve the above and other related objectives, the present invention provides an amplifier circuit, the amplifier circuit comprising at least:

[0009] Current-mode logic amplifier module, negative resistance load module and bias current generation module;

[0010] The current-mode logic amplifier module receives a differential input signal and switches the current branch based on the differential input signal to amplify the signal.

[0011] The negative resistance load module is connected to the current-mode logic amplifier module and is used to increase the voltage gain of the current-mode logic amplifier module.

[0012] The bias current generating module is connected to the negative resistance load module and provides a compensated bias current to the negative resistance load module. The compensated bias current is used to compensate for the gain fluctuations of the negative resistance load module caused by process changes and / or temperature changes.

[0013] Optionally, the bias current generation module includes a first voltage generation circuit, a second voltage generation circuit, and a compensation circuit;

[0014] The first voltage generating circuit generates a first voltage, which varies with process and / or temperature.

[0015] The second voltage generating circuit generates a second voltage, which is a fixed value under certain design conditions;

[0016] The compensation circuit is connected to the output terminals of the first voltage generating circuit and the second voltage generating circuit, and receives the bias current. The compensation circuit generates a compensation current based on the difference between the first voltage and the second voltage, and compensates the bias current based on the compensation current to obtain the compensated bias current.

[0017] Alternatively, the first voltage generating circuit includes a first bandgap reference current and a detection unit, wherein the detection unit senses process and / or temperature changes;

[0018] The first end of the detection unit is connected to the first bandgap reference current, and the second end is grounded; the first end of the detection unit outputs the first voltage.

[0019] Alternatively, the detection unit includes N NMOS transistors connected in a diode configuration, where N is a natural number greater than or equal to 1; when N is greater than or equal to 2, the NMOS transistors connected in a diode configuration are connected in series.

[0020] Alternatively, the second voltage generating circuit includes a second bandgap reference current and a first resistor;

[0021] The first end of the first resistor is connected to the second bandgap reference current, and the second end is grounded; the first end of the first resistor outputs the second voltage.

[0022] Alternatively, the compensation circuit includes a bias current, a first current mirror, a second current mirror, a first transistor, a second transistor, a third transistor, and a second resistor;

[0023] The input terminal of the first current mirror receives the bias current, and the first output terminal and the second output terminal respectively output the corresponding proportion of the output current.

[0024] The first terminal of the first transistor is connected to the first output terminal of the first current mirror, the control terminal receives the first voltage, and the second terminal is connected to the second terminal of the third transistor and the control terminal; the first terminal of the third transistor is connected to the power supply voltage.

[0025] The first terminal of the second transistor is connected to the second output terminal of the first current mirror, the control terminal receives the second voltage, and the second terminal is connected to the input terminal of the second current mirror.

[0026] One end of the second resistor is connected to the first terminal of the first transistor, and the other end is connected to the first terminal of the second transistor;

[0027] The output terminal of the second current mirror outputs the compensated bias current.

[0028] Alternatively, the bias current may be a positive temperature coefficient current, a negative temperature coefficient current, or a bandgap reference current.

[0029] Alternatively, the first transistor and the second transistor are NMOS transistors, and the third transistor is a PMOS transistor.

[0030] Alternatively, the negative resistance load module includes a third current mirror, a fourth transistor, and a fifth transistor;

[0031] The input terminal of the third current mirror receives the compensated bias current, and the output terminal is connected to the first terminal of the fourth transistor and the fifth transistor.

[0032] The fourth transistor is cross-coupled with the fifth transistor, the second end of the fourth transistor is connected to the first output terminal of the current-mode logic amplifier module, and the second end of the fifth transistor is connected to the second output terminal of the current-mode logic amplifier module.

[0033] Alternatively, the fourth transistor and the fifth transistor are NMOS transistors.

[0034] Alternatively, the current-mode logic amplifier module includes a fourth current mirror, a first input transistor, a second input transistor, a first load, and a second load;

[0035] The input terminal of the fourth current mirror is connected to the third bandgap reference current, and the output terminal is connected to the first terminal of the first input transistor and the second input transistor.

[0036] The input terminals of the first input transistor and the second input transistor receive the differential input signal, and the second terminals are connected to the power supply voltage via the first load and the second load, respectively.

[0037] Alternatively, the first input transistor and the second input transistor are NMOS transistors.

[0038] To achieve the above and other related objectives, the present invention also provides an adaptive compensation method, which includes at least:

[0039] Provide a compensation current related to the process and / or temperature, and compensate the bias current based on the compensation current to obtain a compensated bias current;

[0040] The negative resistor is driven by the compensated bias current to generate a corresponding resistance value. The voltage gain of the current-mode logic amplifier module is increased based on the obtained negative resistance value to suppress gain fluctuations caused by process offset and / or temperature changes.

[0041] Optionally, the method for generating the compensation current includes:

[0042] A first voltage is provided, the first voltage varying with process and / or temperature;

[0043] A second voltage is provided, which is a fixed value under defined design conditions;

[0044] The voltage difference between the first voltage and the second voltage is converted into a compensation current.

[0045] Alternatively, the compensated bias current satisfies:

[0046] Iout = Ib + (Vref - Vdio) / R;

[0047] Where Iout is the compensated bias current, Ib is the bias current, Vdio is the first voltage, Vref is the second voltage, and R is the resistance value of the resistor through which the compensated current flows.

[0048] Alternatively, the bias current may be a positive temperature coefficient current, a negative temperature coefficient current, or a bandgap reference current.

[0049] To achieve the above and other related objectives, the present invention also provides an electronic device, which includes at least the amplifier circuit described above.

[0050] As described above, the amplifier circuit, adaptive compensation method, and electronic device of the present invention have the following beneficial effects:

[0051] 1. The amplifier circuit, adaptive compensation method, and electronic equipment of the present invention fundamentally suppress the sensitivity of the gain of current-mode logic amplifiers to temperature and process.

[0052] 2. The amplifier circuit, adaptive compensation method, and electronic equipment of the present invention can realize real-time, adaptive, and low-overhead compensation technology at the analog domain front end, which can stabilize the performance of the receiving link and reduce the bit error rate, ensuring that the high-speed receiver can maintain stable and reliable performance under various operating conditions. Attached Figure Description

[0053] Figure 1 The diagram shown is a schematic block diagram of the amplifier circuit of the present invention.

[0054] Figure 2 The diagram shown is a schematic representation of the amplifier circuit of this invention.

[0055] Figure 3 The diagram shown is a flowchart of the adaptive compensation method of the present invention.

[0056] Component designation explanation:

[0057] 1-Amplifier circuit; 11-Current-mode logic amplifier module; 111-Fourth current mirror; 112-First input transistor; 113-Second input transistor; 114-First load; 115-Second load; 12-Negative resistance load module; 121-Third current mirror; 122-Fourth transistor; 123-Fifth transistor; 13-Bias current generation module; 131-First voltage generation circuit; 132-Second voltage generation circuit; 133-Compensation circuit; 13a-Detection unit; 13b-First current mirror; 13c-First transistor; 13d-Second transistor; 13e-Third transistor; 13f-Second current mirror. Detailed Implementation

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] Please see Figures 1-3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be flexibly changed according to the design, and the layout of the components may also be more complex.

[0060] like Figure 1 As shown, the present invention provides an amplifier circuit 1, which includes:

[0061] The current-mode logic amplifier module 11, the negative resistance load module 12, and the bias current generation module 13 are included.

[0062] like Figure 1 As shown, the current-mode logic amplifier module 11 receives differential input signals VIP and VIN, switches the current branch based on the differential input signals VIP and VIN to amplify the signal, and outputs differential output signals VOP and VON.

[0063] Specifically, the current-mode logic amplifier module 11 includes a differential pair driven by a constant current source. Signal amplification and transmission are achieved by switching the current between the two branches of the differential pair. The current distribution between the two current branches is determined by the magnitude relationship between the differential input signals (first input signal VIP and second input signal VIN). Any circuit structure that can achieve the above function is applicable to the current-mode logic amplifier module of the present invention.

[0064] Specifically, such as Figure 2As shown, in this embodiment, the current-mode logic amplifier module 11 includes a fourth current mirror 111, a first input transistor 112, a second input transistor 113, a first load 114, and a second load 115. The first input transistor 112 and the second input transistor 113 form a differential pair. The input terminal of the fourth current mirror 111 is connected to a third bandgap reference current Ibg3, and the output terminal is connected to the first terminals of the first input transistor 112 and the second input transistor 113; the fourth current mirror 111 provides a constant current source for the differential pair. In this example, the fourth current mirror 111 includes a first NMOS transistor N1 and a second NMOS transistor N2. The drain and gate of the first NMOS transistor N1 serve as the input terminals of the fourth current mirror 111, the sources of the first NMOS transistor N1 and the second NMOS transistor N2 are grounded, the gate of the second NMOS transistor N2 is connected to the gate of the first NMOS transistor N1, and the drain of the second NMOS transistor N2 serves as the output terminal of the fourth current mirror 111. In practical applications, the current mirror structure can be configured as needed. The first input transistor 112 receives the first input signal VIP at its input terminal, and its second terminal is connected to the power supply voltage via the first load 114. The second terminal of the first input transistor 112 serves as the first output terminal of the current-mode logic amplifier module 11 (outputting the first output signal VON). The second input transistor 113 receives the second input signal VIN at its input terminal, and its second terminal is connected to the power supply voltage via the second load 115. The second terminal of the second input transistor 113 serves as the second output terminal of the current-mode logic amplifier module 11 (outputting the second output signal VOP). As an example, if the first input transistor 112 and the second input transistor 113 are implemented using NMOS transistors, then the first terminal of the first input transistor 112 and the second input transistor 113 are the source, the second terminal is the drain, and the input terminal is the gate. In actual use, the device type (including but not limited to CMOS transistors and BJTs) can be selected as needed, and the connection relationship of each port can be adapted accordingly, which will not be elaborated here. In this embodiment, when the first input signal VIP is high and the second input signal VIN is low, the first input transistor 112 is turned on and the second input transistor 113 is turned off, and current flows through the branch where the first input transistor 112 is located; when the first input signal VIP is low and the second input signal VIN is high, the first input transistor 112 is turned off and the second input transistor 113 is turned on, and current flows through the branch where the second input transistor 113 is located; when the branch where the first input transistor 112 is located and the branch where the second input transistor 113 is located are both turned on, the larger the input signal, the larger the current in the corresponding branch.

[0065] like Figure 1 As shown, the negative resistance load module 12 is connected to the current-mode logic amplifier module 11 to increase the voltage gain of the current-mode logic amplifier module 11.

[0066] Specifically, in this embodiment, the negative resistance load module 12 is connected to the output terminal of the current-mode logic amplifier module 11, providing negative resistance. This negative resistance significantly improves the circuit's gain and speed without increasing power consumption. Any circuit structure that can improve the voltage gain of the current-mode logic amplifier module 11 based on negative resistance is applicable to the negative resistance load module of this invention.

[0067] Specifically, such as Figure 2 As shown, in this embodiment, the negative resistive load module 12 includes a third current mirror 121, a fourth transistor 122, and a fifth transistor 123. The fourth transistor 122 and the fifth transistor 123 are cross-coupled. The input terminal of the third current mirror 121 receives the compensated bias current Iout, and its output terminal is connected to the first terminals of the fourth transistor 122 and the fifth transistor 123. The third current mirror 121 provides a current source for the cross-coupled structure based on the compensated bias current Iout. In this example, the third current mirror 121 includes a third NMOS transistor N3 and a fourth NMOS transistor N4, with the same structure as the fourth current mirror 111, which will not be described in detail here; the current mirror structure can be configured as needed in actual use. The second terminal of the fourth transistor 122 is connected to the first output terminal of the current-mode logic amplifier module 11, and the second terminal of the fifth transistor 123 is connected to the second output terminal of the current-mode logic amplifier module 11. As an example, if the fourth transistor 122 and the fifth transistor 123 are implemented using NMOS transistors, then the first terminal of the fourth transistor 122 and the fifth transistor 123 is the source, the second terminal is the drain, and the control terminal is the gate; the gate of the fourth transistor 122 and the drain of the fifth transistor 123 are connected, and the gate of the fifth transistor 123 and the drain of the fourth transistor 122 are connected, thus obtaining a cross-coupled structure.

[0068] It should be noted that the resistance value of the negative resistive load module 12 is highly dependent on the transconductance of the transistor (a MOSFET in this example) that constitutes its cross-coupling structure. The transconductance itself is extremely sensitive to manufacturing process variations (such as fluctuations in threshold voltage and carrier mobility) and operating temperature changes. Therefore, when the process angle shifts or the ambient temperature changes, the actual resistance value of the negative resistive load module 12 will fluctuate significantly, leading to instability in the total equivalent load impedance of this stage of the circuit. Ultimately, this instability directly manifests as a significant change in the voltage gain of amplifier circuit 1 (which severely affects the equalization capability and signal integrity of the entire receiving link when amplifier circuit 1 is used in a receiver), becoming a key technical bottleneck limiting the system's performance consistency across a wide temperature range and different process batches.

[0069] like Figure 1As shown, the bias current generation module 13 is connected to the negative resistance load module 12 and provides a compensated bias current Iout to the negative resistance load module 12. The compensated bias current Iout is used to compensate for the gain fluctuations of the negative resistance load module 12 caused by process changes and / or temperature changes.

[0070] Specifically, such as Figure 2 As shown, the bias current generation module 13 includes a first voltage generation circuit 131, a second voltage generation circuit 132, and a compensation circuit 133. The first voltage generation circuit 131 generates a first voltage Vdio, which varies with process and / or temperature. The second voltage generation circuit 132 generates a second voltage Vref, which is a fixed value under defined design conditions (i.e., unaffected by process and / or temperature). The compensation circuit 133 is connected to the outputs of the first voltage generation circuit 131 and the second voltage generation circuit 132, and receives the bias current Ib. The compensation circuit 133 generates a compensation current Idelta based on the difference between the first voltage Vdio and the second voltage Vref, and compensates the bias current Ib based on the compensation current Idelta to obtain the compensated bias current Iout.

[0071] More specifically, the first voltage generation circuit 131 includes a first bandgap reference current Ibg1 and a detection unit 13a. The detection unit 13a senses process and / or temperature changes. The first terminal of the detection unit 13a is connected to the first bandgap reference current Ibg1, and the second terminal is grounded. The first terminal of the detection unit 13a outputs a first voltage Vdio. The first bandgap reference current Ibg1 is theoretically unaffected by power supply, ambient temperature, and process deviations. However, the detection unit 13a is affected by process and / or temperature changes, generating a first voltage Vdio that varies with the process and / or temperature under the action of the first bandgap reference current Ibg1. In this embodiment, the detection unit 13a includes N NMOS transistors connected in a diode configuration, where N is a natural number greater than or equal to 1. When N is greater than or equal to 2, the diode-connected NMOS transistors are connected in series. As an example, N is set to 2. In practical use, the structure of the first voltage generation circuit 131 can be set as needed. Any circuit structure that can sense the influence of process and / or temperature and generate a corresponding voltage signal is applicable to the first voltage generation circuit 131 of the present invention. The first voltage generation circuit 131 includes, but is not limited to, a MOS transistor (with the same process as the cross-coupled transistor in the negative resistance load module 12), and the trend of being affected by process and / or temperature is the same as or opposite to the trend of being affected by the negative resistance load module 12.

[0072] More specifically, the second voltage generation circuit 132 includes a second bandgap reference current Ibg2 and a first resistor R1. The first terminal of the first resistor R1 is connected to the second bandgap reference current Ibg2, and the second terminal is grounded; the first terminal of the first resistor R1 outputs a second voltage Vref. The second bandgap reference current Ibg2 acts on the first resistor R1, generating a second voltage Vref that is unaffected by process and / or temperature. In practical applications, any circuit structure capable of generating a second voltage unaffected by process and / or temperature is applicable to this invention and is not limited to this embodiment.

[0073] More specifically, the compensation circuit 133 includes a bias current Ib, a first current mirror 13b, a first transistor 13c, a second transistor 13d, a third transistor 13e, a second current mirror 13f, and a second resistor R2. The bias current Ib can be set to a positive temperature coefficient current, a negative temperature coefficient current, or a bandgap reference current according to the circuit requirements using the compensated bias current Iout, which will not be elaborated here. The input terminal of the first current mirror 13b receives the bias current Ib, and the first and second output terminals output corresponding proportional output currents, respectively. In this example, the first current mirror 13b includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7. The drain and gate of the fifth NMOS transistor N5 are connected together as the input terminal of the first current mirror 13b. The sources of the fifth NMOS transistor N5, the sixth NMOS transistor N6, and the seventh NMOS transistor N7 are grounded. The gates of the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are connected to the gate of the fifth NMOS transistor N5. The drain of the sixth NMOS transistor N6 serves as the first output terminal of the first current mirror 13b, and the drain of the seventh NMOS transistor N7 serves as the second output terminal of the first current mirror 13b. In actual use, the current mirror structure can be configured as needed. The first terminal of the first transistor 13c is connected to the first output terminal of the first current mirror 13b, and its control terminal receives the first voltage Vdio. Its second terminal is connected to the second terminal of the third transistor 13e and the control terminal. The first terminal of the third transistor 13e is connected to the power supply voltage. The first terminal of the second transistor 13d is connected to the second output terminal of the first current mirror 13b, and its control terminal receives the second voltage Vref. Its second terminal is connected to the input terminal of the second current mirror 13f. One end of the second resistor R2 is connected to the first terminal of the first transistor 13c, and the other end is connected to the first terminal of the second transistor 13d. As an example, if the first transistor 13c and the second transistor 13d are implemented using NMOS transistors, and the third transistor 13e is implemented using a PMOS transistor, then the first terminals of the first transistor 13c, the second transistor 13d, and the third transistor 13e are the sources, the second terminals are the drains, and the control terminal is the gate. The output terminal of the second current mirror 13f outputs the compensated bias current Iout. In this example, the second current mirror 13f includes a first PMOS transistor P1 and a second PMOS transistor P2. The drain and gate of the first PMOS transistor P1 are connected together as the input terminal of the second current mirror 13f. The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the power supply voltage. The gate of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1. The drain of the second PMOS transistor P2 serves as the output terminal of the second current mirror 13f. In actual use, the current mirror structure can be configured as needed.

[0074] It should be noted that the bias current generation module 13 can adaptively compensate for temperature and process drift, thereby achieving dynamic and stable control of the resistance value of the negative resistance load module 12.

[0075] like Figure 3 As shown, the present invention also provides an adaptive compensation method, which includes:

[0076] A compensation current Idelta, which is related to the process and / or temperature, is provided. The bias current Ib is compensated based on the compensation current Idelta to obtain the compensated bias current Iout.

[0077] The compensated bias current Iout drives the negative resistor and generates a corresponding resistance value. Based on the obtained negative resistance value, the voltage gain of the current-mode logic amplifier module is increased to suppress gain fluctuations caused by process offset and / or temperature changes.

[0078] Specifically, as an example, a method for generating the compensation current Idelta includes: providing a first voltage Vdio, which varies with process and / or temperature; providing a second voltage Vref, which is a fixed value under defined design conditions; and converting the voltage difference between the first voltage Vdio and the second voltage Vref into a compensation current. The first voltage Vdio can be generated using a MOSFET connected to a diode, and its value varies with process parameters such as the threshold voltage of the MOSFET. The methods for generating the first voltage Vdio are not detailed here. The compensated bias current Iout satisfies:

[0079] Iout = Ib + (Vref - Vdio) / R;

[0080] Where R is the resistance through which the compensation current Idelta flows (in this example, the second resistor R2). The bias current Ib can be set as a positive temperature coefficient current, a negative temperature coefficient current, or a bandgap reference current as needed, which will not be elaborated here.

[0081] The following describes the working principle of the adaptive compensation method of the present invention using the amplifier circuit 1 provided by the present invention as an example. In actual use, any circuit structure that can implement this method is applicable.

[0082] like Figure 2As shown, when the temperature is constant (e.g., at normal temperature), the amplifier circuit 1 is designed such that Vdio=Vref at the standard process corner (MOS_TT). Assuming a positive process drift occurs (e.g., MOS_FF, where the threshold voltage decreases), then Vdio<Vref, and the obtained compensation voltage Vdelta is recorded as Vdelta=Vref-Vdio, (Vdelta<0); conversely, assuming a negative process drift occurs (e.g., MOS_SS, where the threshold voltage increases), then Vdio>Vref, which is recorded as Vdelta=Vref-Vdio, (Vdelta>0). The compensation voltage Vdelta is directly applied across the second resistor R2, thereby generating a compensation current Idelta related to process deviation on the second resistor R2, where Idelta=Vdelta / R (R is the resistance value of the second resistor R2 at this time). Finally, the compensated bias current Iout loaded on the negative resistance load module 12 is formed by superposition of two parts: one part is the bias current Ib, and the other part is the above-mentioned process compensation current Idelta, that is: Iout=Ib+(Vref-Vdio) / R. The compensated bias current Iout can be automatically adjusted with the change of process corners: for example, additional current is injected at MOS_FF to increase the overdrive voltage of the negative resistance MOS transistors (the fourth transistor 122 and the fifth transistor 123) in the negative resistance load module 12; at MOS_SS, the current of the negative resistance load module 12 is reduced, thereby reversely compensating the transconductance change of the negative resistance cross-coupled transistors caused by process variation; this keeps the equivalent resistance value of the negative resistance cross-coupled transistors relatively stable under different process corners. Therefore, the present invention introduces a feedback compensation path based on voltage comparison, realizes process adaptive adjustment of the current source of the negative resistance, and effectively suppresses gain fluctuation caused by process drift in conventional structures.

[0083] As Figure 2 shown, when the process corner is constant (e.g., under MOS_TT), the bias current generation module 13 can also effectively resist temperature changes. The design is such that Vdio=Vref at normal temperature; due to the temperature characteristics of semiconductor carrier mobility and threshold voltage, when the temperature decreases, Vdio>Vref, and a reverse compensation current Idelta is formed on the second resistor R2; conversely, when the temperature increases, Vdio<Vref, and a forward compensation current Idelta is formed on the second resistor R2; therefore, the compensated bias current Iout=Ib+Idelta, and Idelta can be automatically adjusted with temperature changes, correcting the bias point of the negative resistance cross-coupled transistors in real time, so that the variation trend of their transconductance characteristics with temperature is compensated, thereby effectively suppressing fluctuations in the negative resistance value and the overall gain of the circuit caused by temperature changes in conventional structures.

[0084] The present invention also provides an electronic device including the amplifier circuit 1 of the present invention. As an example, the amplifier circuit 1 is applied in the receiver of a wireless communication system to stabilize the gain of the receiving link in the communication system, thereby reducing the bit error rate.

[0085] In summary, this invention provides an amplifier circuit, an adaptive compensation method, and an electronic device. The amplifier circuit includes a current-mode logic amplifier module, a negative resistive load module, and a bias current generation module. The current-mode logic amplifier module receives a differential input signal and switches the current branch based on the differential input signal to amplify the signal. The negative resistive load module is connected to the current-mode logic amplifier module and is used to increase the voltage gain of the current-mode logic amplifier module. The bias current generation module is connected to the negative resistive load module and provides a compensated bias current to the negative resistive load module. The compensated bias current is used to compensate for gain fluctuations in the negative resistive load module caused by process variations and / or temperature variations. The amplifier circuit, adaptive compensation method, and electronic device of this invention fundamentally suppress the gain sensitivity of the current-mode logic amplifier to temperature and process variations. They enable real-time, adaptive, and low-overhead compensation technology at the analog domain front end, stabilizing receiver link performance and reducing bit error rate, ensuring stable and reliable performance of the high-speed receiver under various operating conditions. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0086] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An amplifier circuit, characterized in that, The amplifier circuit includes at least: Current-mode logic amplifier module, negative resistance load module and bias current generation module; The current-mode logic amplifier module receives a differential input signal and switches the current branch based on the differential input signal to amplify the signal. The negative resistance load module is connected to the output terminal of the current-mode logic amplifier module and is used to increase the voltage gain of the current-mode logic amplifier module. The bias current generating module is connected to the negative resistance load module and provides a compensated bias current to the negative resistance load module. The compensated bias current is used to compensate for the gain fluctuations of the negative resistance load module caused by process changes and / or temperature changes. The bias current generation module includes a first voltage generation circuit, a second voltage generation circuit, and a compensation circuit. The first voltage generating circuit generates a first voltage, which varies with process and / or temperature. The second voltage generating circuit generates a second voltage, which is a fixed value under certain design conditions and is not affected by process and / or temperature. The compensation circuit is connected to the output terminals of the first voltage generating circuit and the second voltage generating circuit, and receives the bias current. The compensation circuit generates a compensation current based on the difference between the first voltage and the second voltage, and compensates the bias current based on the compensation current to obtain the compensated bias current.

2. The amplifier circuit according to claim 1, characterized in that: The first voltage generation circuit includes a first bandgap reference current and a detection unit, wherein the detection unit senses process and / or temperature changes; The first end of the detection unit is connected to the first bandgap reference current, and the second end is grounded; the first end of the detection unit outputs the first voltage.

3. The amplifier circuit according to claim 2, characterized in that: The detection unit includes N NMOS transistors connected in a diode configuration, where N is a natural number greater than or equal to 1; when N is greater than or equal to 2, the NMOS transistors connected in a diode configuration are connected in series.

4. The amplifier circuit according to claim 1, characterized in that: The second voltage generating circuit includes a second bandgap reference current and a first resistor; The first end of the first resistor is connected to the second bandgap reference current, and the second end is grounded; the first end of the first resistor outputs the second voltage.

5. The amplifier circuit according to claim 1, characterized in that: The compensation circuit includes a bias current, a first current mirror, a second current mirror, a first transistor, a second transistor, a third transistor, and a second resistor; The input terminal of the first current mirror receives the bias current, and the first output terminal and the second output terminal respectively output the corresponding proportion of the output current. The first terminal of the first transistor is connected to the first output terminal of the first current mirror, the control terminal receives the first voltage, and the second terminal is connected to the second terminal of the third transistor and the control terminal; the first terminal of the third transistor is connected to the power supply voltage. The first terminal of the second transistor is connected to the second output terminal of the first current mirror, the control terminal receives the second voltage, and the second terminal is connected to the input terminal of the second current mirror. One end of the second resistor is connected to the first terminal of the first transistor, and the other end is connected to the first terminal of the second transistor; The output terminal of the second current mirror outputs the compensated bias current.

6. The amplifier circuit according to claim 5, characterized in that: The bias current is a positive temperature coefficient current, a negative temperature coefficient current, or a bandgap reference current.

7. The amplifier circuit according to claim 5, characterized in that: The first transistor and the second transistor are NMOS transistors, and the third transistor is a PMOS transistor.

8. The amplifier circuit according to any one of claims 1-7, characterized in that: The negative resistance load module includes a third current mirror, a fourth transistor, and a fifth transistor; The input terminal of the third current mirror receives the compensated bias current, and the output terminal is connected to the first terminal of the fourth transistor and the fifth transistor. The control terminal of the fifth transistor and the second terminal of the fourth transistor are connected to the first output terminal of the current-mode logic amplifier module, and the control terminal of the fourth transistor and the second terminal of the fifth transistor are connected to the second output terminal of the current-mode logic amplifier module.

9. The amplifier circuit according to claim 8, characterized in that: The fourth and fifth transistors are NMOS transistors.

10. The amplifier circuit according to any one of claims 1-7, characterized in that: The current-mode logic amplifier module includes a fourth current mirror, a first input transistor, a second input transistor, a first load, and a second load; The input terminal of the fourth current mirror is connected to the third bandgap reference current, and the output terminal is connected to the first terminal of the first input transistor and the second input transistor. The input terminals of the first input transistor and the second input transistor receive the differential input signal, and the second terminals are connected to the power supply voltage via the first load and the second load, respectively.

11. The amplifier circuit according to claim 10, characterized in that: The first input transistor and the second input transistor are NMOS transistors.

12. An adaptive compensation method, implemented based on the amplifier circuit as described in any one of claims 1-11, characterized in that, The adaptive compensation method includes at least: Provide a compensation current related to the process and / or temperature, and compensate the bias current based on the compensation current to obtain a compensated bias current; The negative resistor is driven by the compensated bias current to generate a corresponding resistance value. The voltage gain of the current-mode logic amplifier module is increased based on the obtained negative resistance value to suppress gain fluctuations caused by process offset and / or temperature changes.

13. The adaptive compensation method according to claim 12, characterized in that: The method for generating the compensation current includes: A first voltage is provided, the first voltage varying with process and / or temperature; A second voltage is provided, which is a fixed value under defined design conditions; The voltage difference between the first voltage and the second voltage is converted into a compensation current.

14. The adaptive compensation method according to claim 12 or 13, characterized in that: The compensated bias current satisfies: Iout = Ib + (Vref - Vdio) / R; Where Iout is the compensated bias current, Ib is the bias current, Vdio is the first voltage, Vref is the second voltage, and R is the resistance value of the resistor through which the compensated current flows.

15. The adaptive compensation method according to claim 14, characterized in that: The bias current is a positive temperature coefficient current, a negative temperature coefficient current, or a bandgap reference current.

16. An electronic device, characterized in that, The electronic device includes at least the amplifier circuit as described in any one of claims 1-11.

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