A multi-voltage adaptive control system and method for SiC MOSFETs based on programmable drive.

Abstract

This invention relates to the field of wide-bandgap semiconductor power device driving technology, specifically to a SiC MOSFET multi-voltage adaptive control system and method based on programmable drive, solving problems such as rigid hardware, system complexity, and inability to dynamically optimize performance in existing drive solutions. The system consists of a control board, a drive board, and a three-phase full-bridge SiC MOSFET module. It uses the Infineon TC275 as the control core and the NXP GD3160 chip to achieve programmable configuration of positive and negative drive voltages. Dynamic adaptive voltage switching is achieved by combining junction temperature and phase current thresholds. A daisy-chain communication and hierarchical fault protection design are employed. The control method includes steps such as power-on initialization, operating condition acquisition, mode switching, fault handling, and command response. This invention enables a single hardware platform to adapt to multiple gate voltage requirements, significantly reducing costs and testing cycles, improving SiC MOSFET operating performance and system reliability, and is suitable for electric drive fields such as new energy commercial vehicles.

Description

Technical Field

[0001] This invention relates to the field of wide bandgap semiconductor power device driving technology, specifically to a SiC MOSFET multi-voltage adaptive control system and method based on programmable drive. Background Technology

[0002] Silicon carbide (SiC) MOSFETs, as third-generation wide-bandgap semiconductor power devices, have gradually replaced traditional silicon-based power devices and become the core switching devices in the main drive inverters of new energy vehicles due to their excellent characteristics of high frequency, high efficiency, and high temperature resistance. New energy commercial vehicles have extremely high requirements for the power density, efficiency, and reliability of electric drive systems. The performance of SiC MOSFETs is highly dependent on the precise matching of the gate drive voltage. In order to fully utilize their electrical performance and ensure reliable turn-off to prevent false turn-on, the drive circuit needs to provide them with precise positive and negative gate voltages. At present, the mainstream drive voltage combinations in the industry are mainly -4V / +15V, -5V / +18V, etc. The requirements for gate drive voltage of SiC MOSFETs from different suppliers and different batches vary, which places higher demands on the adaptability of the drive circuit.

[0003] Existing SiC MOSFET driving solutions are mainly divided into two categories. The first category is the fixed output driving solution, which usually uses a dedicated driver chip (such as TIUCC21750) or discrete components to build the driving circuit. Its output positive and negative voltage values ​​are fixed in hardware design, and a single circuit board can only support one specific voltage combination output, which cannot be adjusted according to actual needs. The second category is the multi-chip parallel solution. In order to adapt to multiple SiC MOSFETs with different gate voltage requirements, the system design needs to use multiple fixed output driver chips in parallel, and configure corresponding isolation power supplies and peripheral circuits for each chip to achieve driving adaptation for different SiC MOSFETs.

[0004] However, existing technical solutions have many defects and shortcomings, and can no longer meet the development needs of electric drive systems for new energy commercial vehicles. Firstly, the hardware is rigid and lacks flexible adaptability. Fixed-voltage output solutions cannot adapt to SiC MOSFETs with different gate voltage requirements at the hardware level. In the R&D and production of new energy commercial vehicles, if power modules need to be replaced due to supply chain adjustments, cost control, or performance optimization, the driver board must be redesigned, which not only significantly extends the development cycle but also significantly increases hardware R&D and manufacturing costs. Secondly, the system is complex and costs remain high. While multi-chip parallel solutions can solve compatibility issues to some extent, they lead to a significant increase in PCB area and a multiplied increase in the number of isolation power supplies. Simultaneously, the types and management complexity of the BOM (Bill of Materials) increase dramatically, violating the core design requirements of high integration, low cost, and high reliability in the automotive electronics field. Thirdly, performance is difficult to dynamically optimize. Fixed-gate voltage solutions cannot be fine-tuned in real time according to the actual operating state of the SiC MOSFET. Under high temperature or high load conditions, SiC… MOSFETs often require higher positive voltages to reduce conduction losses or deeper negative voltages to enhance turn-off margins. However, existing static drive solutions cannot achieve such online performance tuning, resulting in the device's performance not being fully utilized under certain operating conditions, and even posing reliability risks. Fourth, the testing and verification process is cumbersome. During the R&D and testing phase of SiC MOSFET drive systems, multiple hardware platforms need to be built to evaluate the impact of different drive voltages on switching losses, electromagnetic interference (EMI), and short-circuit withstand capability. Moreover, the drive voltage requirements of different module manufacturers vary, which greatly increases the verification cost and time during the development phase and reduces R&D efficiency.

[0005] Furthermore, existing drive solutions often employ simplistic protection mechanisms, resulting in slow fault response and an inability to coordinate protection with drive voltage adjustments. When dynamically adjusting the drive voltage to optimize performance, these mechanisms are prone to damage due to overcurrent or overtemperature issues. Additionally, existing solutions typically use star connections for communication, requiring separate isolation circuits for each drive chip, further increasing system complexity and cost. Therefore, developing a SiC MOSFET drive solution that offers strong hardware adaptability, low cost, dynamic performance optimization, and high reliability has become an urgent need in the field of electric drive systems for new energy commercial vehicles. Summary of the Invention

[0006] To address the problems of rigid hardware, complex systems, high costs, inability to dynamically optimize performance, and cumbersome testing and verification in existing SiC MOSFET driving solutions, this invention provides a SiC MOSFET multi-voltage adaptive control system and method based on programmable drivers. Through co-design of hardware and software, it achieves dynamic and adaptive output of a single driver chip for multiple gate drive voltage combinations. A single hardware platform adapts to the mainstream SiC MOSFET drive voltage requirements in the market. At the same time, it realizes real-time optimization of drive voltage based on the device's operating conditions, reducing development and material management costs, and improving the switching performance and system reliability of SiC MOSFETs under different operating conditions.

[0007] The technical solution adopted by this invention to solve its technical problem is: a SiC MOSFET multi-voltage adaptive control system based on programmable drive, including a control board, a driver board, and a SiC MOSFET three-phase full-bridge module. The core of the control board is an Infineon TC275 microcontroller, whose input terminal is connected to the vehicle's +24V power supply and stepped down to 15V for transmission to the driver board. The control board communicates with the vehicle controller via a CAN bus and is connected to the driver board via SPI. The driver board includes a flyback switching power supply, a negative voltage adjustable LDO, and six NXP GD3160 isolated driver chips. The flyback switching power supply uses a center-tapped transformer to convert the 15V to a positive and negative isolated power supply. Its positive voltage output terminal is connected to the VCC pin of the GD3160, and its negative voltage output terminal is connected to the input terminal of the negative voltage adjustable LDO. The output terminal of the negative voltage adjustable LDO is connected to the VEE pin of the GD3160. The MOSFET three-phase full-bridge consists of three half-bridge modules composed of six SiC MOSFETs, each corresponding to one of the six GD3160 chips. The GD3160 is configured via SPI to output a positive voltage of 15-18V through the VCCREG pin, and via the TSENSEA pin to configure a current source to adjust the negative voltage output of the adjustable LDO to -4V or -5V. The control board collects the temperature and phase current of the power module and realizes dynamic adaptive switching of the drive voltage based on a preset threshold. The six GD3160 chips are connected in a daisy-chain communication manner, and fault signals are grouped and connected in parallel before being transmitted to the control board to achieve hierarchical protection.

[0008] Specifically, the negative voltage adjustable LDO achieves voltage regulation by adjusting the feedback voltage through adjusting the current source magnitude. When the current source is off, it outputs -5V; when the 1mA current source is on, it outputs -4V. Its voltage calculation satisfies the formula: and .

[0009] Specifically, the control board samples the phase current at a frequency of 100µs and the power module temperature at a frequency of 10ms. The junction temperature is estimated using the formula: junction temperature = (module temperature - water temperature) / 30% + water temperature.

[0010] Specifically, the dynamic switching threshold of the driving voltage is as follows: when the junction temperature T > 145℃, it is forced to enter the +15V / -5V protection mode, and the current adjustment path is blocked. When the junction temperature drops back to T < 135℃, it is unlocked. When T < 135℃, Irms > 550A triggers the +18V / -5V heavy load mode, Irms < 450A triggers the +15V / -4V standard mode, and 450A ≤ Irms ≤ 550A maintains the current mode.

[0011] Specifically, the daisy-chain communication data transmission sequence of the six GD3160 chips is as follows: U phase up bridge → U phase down bridge → V phase up bridge → V phase down bridge → W phase up bridge → W phase down bridge. The SPI communication baud rate is 2MHz and the data frame is 24 bits.

[0012] Specifically, the fault signals of the GD3160 include INTA and INTB. The INTA terminals of the three GD3160 chips on the three-phase upper bridge are connected in parallel to form INTAH, the INTA terminals of the three GD3160 chips on the three-phase lower bridge are connected in parallel to form INTAL, and the INTB terminals of the six GD3160 chips are connected in parallel. The total fault response and delay time is less than 8µs.

[0013] Specifically, the GD3160 integrates desaturation protection, active Miller clamping, and soft shutdown functions. The desaturation protection voltage threshold is 6V, the protection time is less than 2µs, and the overcurrent protection current threshold is 900A.

[0014] Specifically, the primary winding of the transformer in the flyback switching power supply is 17Ts, the secondary winding with the center tap is 28Ts and 18Ts, the feedback winding is 18Ts, the full-wave rectifier diode is ES1D, and the output voltage ripple value does not exceed ±3%.

[0015] Specifically, after the system is powered on and initialized, it reads the default -4V / +15V configuration, completes the positive and negative voltage circuit configuration, enters the drive ready state, and can achieve smooth switching of output voltage after receiving the CAN bus voltage configuration command.

[0016] The SiC MOSFET multi-voltage adaptive control method of the system includes the following steps: 1) Upon power-on initialization, the control board completes the default drive voltage configuration, the drive board outputs the corresponding voltage, and the system enters the ready state; 2) The control board collects the power module temperature and phase current in real time, estimates the junction temperature, and determines whether it exceeds the threshold. 3) Based on the junction temperature and current threshold, send configuration commands to the GD3160 via SPI to adjust the positive and negative voltage outputs to achieve mode switching; 4) The GD3160 monitors fault signals in real time and transmits them to the control board in groups. The control board then performs an emergency shutdown or log alert based on the fault type. 5) When receiving the CAN command from the vehicle controller, repeat step 3 to achieve the manually configured voltage switching, or the dual-pulse test verification can be completed by sending a command from the host computer.

[0017] The beneficial effects of this invention are: 1. High Hardware Compatibility: A single hardware platform can adapt to most mainstream and potential future SiC MOSFET drive voltage requirements, such as -4 / +15V, -5 / +18V, and -4 / +18V. This achieves the design goal of a unified hardware platform and software configuration-defined functions, significantly enhancing supply chain flexibility. When replacing power modules, there is no need to redesign the driver board, improving maintainability throughout the product lifecycle. Through a specific connection and communication architecture between the digital control module and the programmable driver chip, independent, real-time, and matched switching between positive and negative voltages is achieved, with adaptability far superior to existing fixed-output and multi-chip parallel solutions.

[0018] 2. Significantly Reduced Direct and Indirect Costs: In terms of direct costs, this invention eliminates the need for redundant driver chips, isolation power supplies, and their peripheral circuits designed for compatibility with different voltages, greatly simplifying the types and quantities of materials and reducing BOM costs. At the same time, the design of the center-tapped flyback switching power supply and daisy-chain communication reduces the use of magnetic components and isolation circuits, further reducing hardware costs. In terms of indirect costs, it significantly shortens the hardware redesign, board manufacturing, and testing cycle caused by component replacement, simplifies inventory management processes, and allows a single testing device to complete the verification of all voltage combinations, significantly reducing development and testing verification costs.

[0019] 3. Possesses dynamic performance optimization potential: This invention provides hardware support for driving voltage optimization based on operating conditions. By collecting the junction temperature and phase current of the power module in real time, it realizes dynamic adaptive switching of the driving voltage. Under light load, it uses -4 / +15V to reduce power consumption, under heavy load, it switches to +18V / -5V to reduce conduction losses, and under high temperature, it switches to +15V / -5V to enhance turn-off reliability. It achieves active performance management that cannot be achieved by fixed voltage schemes, and fully utilizes the electrical performance of SiC MOSFET under different operating conditions.

[0020] 4. High System Reliability: This invention adopts a mature and reliable drive control scheme, paired with a stable and low-noise adjustable negative voltage LDO. The drive voltage output is stable and highly accurate, reaching ±1%. The switching process of the drive voltage is controlled by digital logic, ensuring smooth and orderly operation and avoiding the risks of manual operation and contact reliability issues caused by manual jumpers or component replacement. Simultaneously, the hierarchical fault protection mechanism enables rapid fault response, with a fault response time of less than 8µs. This allows for timely avoidance of risks such as overcurrent and overtemperature during dynamic performance optimization, providing dual protection for stable system operation. Furthermore, the nearby parallel connection of fault signals reduces PCB trace length and loop area, lowers the risk of interference from power loops, and improves signal integrity. Attached Figure Description

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] Figure 1 The diagram shows the three-phase full-bridge topology of the controller described in this invention. It illustrates the topology of three half-bridge SiC modules formed by combining six SiC MOSFET switches (SW1~SW6) in pairs. The diagram also shows the PWM drive signal interface corresponding to each switch and the three-phase output terminals U, V, and W of the motor corresponding to the three half-bridge modules, clearly presenting the core circuit topology of the SiC MOSFET three-phase full-bridge.

[0023] Figure 2 This is a system block diagram of the present invention, showing the components and connections of the SiCMOSFET multi-voltage adaptive control system based on programmable driver. It marks the on-board +24V power input, the 15V power transmission path after step-down from the control board, and the core modules such as flyback switching power supply, center-tapped transformer, negative voltage adjustable LDO, SiCMOSFET, and driver IC. It also shows the CAN bus communication between the control board and the vehicle controller, the SPI communication between the control board and the driver IC, and the connection between the transformer output winding and the power supply pins VCC and VEE of the driver IC.

[0024] Figure 3 The pin definition diagram of the NXPGD3160 isolated driver IC used in this invention fully labels all the pin names of the driver chip, including power supply pins VCC and VEE, communication pins MOSI, MISO, and SCLK, drive pins GH and GL, function configuration pins TSENSEA and VCCREG, fault output pins INTA and INTB, and protection function pins DESAT and AMC, etc., clearly indicating the location and label of each pin.

[0025] Figure 4This is a schematic diagram of the voltage regulation of the negative voltage adjustable LDO of the present invention. It shows the connection structure of the negative voltage adjustable LDO with the external resistor network (R3, R4, R5) and capacitor C6. The power input terminal Vin, voltage output terminal VEE, adjustment pin ADJ and the connection relationship with the driver ICTSENSEA pin are marked. The ground terminal GDNISO is also shown, clearly presenting the hardware connection principle of negative voltage regulation.

[0026] Figure 5 This is a schematic diagram of the SiC module double pulse test verification process of the present invention. The flowchart shows the complete steps of double pulse test for SiC modules from different manufacturers. The steps are as follows: power-on initialization and completion of default configuration, driver enters ready state, host computer sends drive voltage configuration command through CAN bus, chip reconfigures drive voltage, driver becomes ready again, and double pulse test is executed. This reflects the process logic of voltage configuration and test verification.

[0027] Figure 6 This is a schematic diagram of the adaptive drive voltage workflow of the present invention. The control steps of the dynamic adaptive drive voltage are shown in the form of a flowchart, including power-on initialization, receiving instructions from the vehicle controller (VCU), power module temperature sampling, phase current sampling, MCU control decision making, drive voltage configuration, drive readiness, and final drive output. It presents the entire process of adaptive voltage configuration based on operating condition data acquisition.

[0028] Figure 7 This is a schematic diagram of the drive voltage switching decision logic of the present invention. It shows the drive voltage mode switching judgment logic based on the junction temperature and effective value of the phase current of the power module. It clarifies the judgment priority of junction temperature threshold and current threshold, the drive voltage combination mode corresponding to different threshold ranges, and the logical relationship between mode holding and protection mode triggering. It is the core logic demonstration of dynamic adaptive control.

[0029] Figure 8 This is a schematic diagram of the hardware connection of the control system of the present invention, showing the actual physical connection relationship of each hardware module of the system, including the connection of the three-phase SiC MOSFET module, 6 GD3160 driver chips, isolation power supply (Iso Power1~3), and MCU control board. The connection paths of PWM drive signal, SPI communication signal (SCLK, MOSI, MISO), fault signal (INTAH, INTAL, INTB), temperature sampling signal (TEMP_U± / V± / W±), current sampling signal (IU, IV, IW) and power supply terminal (VSUP, VCC, VEE) are marked.

[0030] Figure 9This is a schematic diagram of the circuit connection between the control board and the driver board of the present invention. It focuses on showing the core circuit connection relationship between the control board and the driver board, and marks the path from the 15V power input of the control board to the flyback switching power supply of the driver board, the connection of the positive voltage output of the flyback switching power supply to VCC, the negative voltage output through the negative voltage adjustable LDO to VEE, as well as the SPI communication between the MCU and the programmable gate driver, the PWM signal transmission, the FAULT fault signal feedback, and the connection relationship of the SiC MOSFET gate driver terminals Gon and Goff.

[0031] Figure 10 This diagram illustrates the daisy-chain communication connection of six GD3160 driver chips according to the present invention. It shows the serial daisy-chain connection between the six GD3160 chips, corresponding to the upper and lower bridges of the U / V / W phases respectively, and the MCU. The data transmission sequence is clearly defined as U-phase upper bridge → U-phase lower bridge → V-phase upper bridge → V-phase lower bridge → W-phase upper bridge → W-phase lower bridge. The serial connection relationship between the MCU's MOSI, MISO, CS, and SCLK pins and the corresponding pins of each driver chip is marked, demonstrating the unidirectional serial transmission structure of the daisy-chain communication.

[0032] Figure 11 This is the SPI transmission timing diagram of the present invention, which shows the timing characteristics of each signal in the SPI communication between GD3160 and MCU. The timing parameters (txferdelay, tlag, tlead, etc.) of the four signals CSB, SCLK, MOSI, and MISO are marked, as well as the voltage threshold (0.3VDD, 0.7VDD, etc.), bit width and transmission format of each signal, including the 24-bit data frame of MOSI and the feedback data format of MISO, thus clarifying the timing specifications of SPI communication.

[0033] Figure 12 This diagram illustrates the parallel connection of fault signals in the GD3160 of this invention, showing the parallel connection of the fault output pins INTA and INTB of six GD3160 driver chips. The INTA pins of the three chips on the upper three-phase bridge are connected in parallel to form the INTAH signal, the INTA pins of the three chips on the lower three-phase bridge are connected in parallel to form the INTAAL signal, and the INTB pins of all six chips are connected in parallel to form the INTB signal. All fault signals are ultimately connected to the MCU, clearly demonstrating the hardware signal connection logic of the graded fault protection. Detailed Implementation

[0034] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0035] like Figures 1-12As shown, the SiC MOSFET multi-voltage adaptive control system and method based on programmable drive described in this invention, through a combination of hardware and software, achieves independent, precise, and programmable setting of the positive and negative gate drive voltages of the SiC MOSFET. Simultaneously, it achieves dynamic adaptive switching of the drive voltage based on the junction temperature and phase current of the power module, and designs a highly integrated communication and hierarchical fault protection mechanism, including: System Overall Architecture: The control system of this invention mainly consists of a control board, a driver board, and SiC MOSFET three-phase full-bridge modules. The controller topology adopts a three-phase full-bridge topology, with six SiC MOSFETs combined in pairs to form three half-bridge SiC modules, corresponding to the three-phase outputs U, V, and W of the motor, respectively. The system uses a stable +24V vehicle power supply as input. The control board steps it down to 15V and transmits it to the driver board via connectors. The core of the control board is an Infineon TC275 microcontroller, responsible for executing digital control and configuration functions. It can receive voltage configuration commands from the upper-level vehicle controller via the CAN bus and can also autonomously decide on the switching of drive voltage according to preset strategies. The driver board provides precise programmable drive voltages for the SiC MOSFETs and realizes the acquisition and transmission of fault signals.

[0036] Power Conversion Module: The driver board's power conversion module uses a flyback switching power supply with a center-tapped transformer. It requires only one secondary winding with a center tap, paired with a simple full-wave rectifier circuit, to synchronously convert the 15V input from the control board into two isolated positive and negative power supplies. This significantly simplifies the circuit structure and reduces the number of magnetic components. The positive output of the flyback switching power supply is directly connected to the VCC pin of the driver chip, while the negative output is connected to the input of a negative voltage adjustable LDO, allowing for programmable adjustment of the negative voltage.

[0037] Programmable drive voltage: The driver board uses six NXP GD3160 isolated driver chips, each corresponding to one of the six SiC MOSFETs. Their power supply pins VCC and VEE are connected to the positive voltage output of the flyback switching power supply and the output of the adjustable negative voltage LDO, respectively. The GD3160 can be configured via SPI to output a voltage range of 15-18V in 1V increments via the VCCREG pin, enabling programmable adjustment of the positive voltage. Its TSENSEA pin supports configuring different output currents of the current source. By adjusting the current source, the feedback voltage of the adjustable negative voltage LDO is changed, achieving configurable outputs of -4V and -5V. The voltage adjustment of the adjustable negative voltage LDO follows a specific calculation formula: -5V when the current source is off, and -4V when the 1mA current source is on, with a voltage output accuracy of ±1%.

[0038] Dynamic adaptive control: The control board collects the power module temperature and phase current in real time. In order to accurately capture switching transients and overcurrents, the sampling frequency of the phase current is set to 100us. The junction temperature of SiC MOSFET changes slowly, so the sampling frequency of the power module temperature is set to 10ms. The primary junction temperature is estimated by the formula junction temperature = (module temperature - water temperature) / 30% + water temperature. The system is configured with graded voltage switching thresholds. When the junction temperature T > 145℃, the system is forced into a +15V / -5V protection mode to ensure more reliable shutdown and immediately disable all current-based regulation paths. This protection strategy has the highest priority and will only unlock when the junction temperature drops to T < 135℃. The 10℃ hysteresis design prevents frequent mode oscillations near the critical temperature. Only when T < 135℃ does the system determine the appropriate mode based on the effective value of the phase current. When Irms > 550A, a +18V / -5V heavy-load high-efficiency mode is triggered to reduce conduction losses under high current. When Irms < 450A, a +15V / -4V standard mode is triggered to reduce gate stress under low to medium current. When 450A ≤ Irms ≤ 550A, the current mode is maintained, and a dead time is introduced to avoid frequent switching caused by current fluctuations.

[0039] Communication and Fault Protection: The six GD3160 chips are connected to the control board via a daisy-chain communication system. The data transmission sequence is: U-phase upper bridge → U-phase lower bridge → V-phase upper bridge → V-phase lower bridge → W-phase upper bridge → W-phase lower bridge. The SPI communication baud rate is 2MHz, and the data frame is 24-bit. In daisy-chain mode, communication between subsequent drivers within the chain is isolated internally by the chip, which significantly reduces cost and complexity compared to star connection. Furthermore, it closely matches the linear arrangement of the three-phase full-bridge on the PCB, reducing parasitic parameters. The GD3160 supports two fault interrupt signals, INTA and INTB. The INTA terminals of the three GD3160 chips on the three-phase upper bridge are connected in parallel to form INTAH, and the INTA terminals of the three GD3160 chips on the three-phase lower bridge are connected in parallel to form INTAL. The INTB terminals of the six GD3160 chips are connected in parallel to achieve fast and hierarchical fault protection. The total fault response and delay time is less than 8µs. Severe faults trigger immediate shutdown protection, while non-immediate fatal faults are queried and logged by the MCU via SPI, providing a safety guarantee for dynamic optimization algorithms.

[0040] Dual-pulse test verification process: The system supports dual-pulse test verification of SiC modules from different manufacturers. After power-on initialization, the digital control module reads the default -4V / +15V drive voltage configuration, then configures the positive and negative voltage circuits and completes the corresponding voltage output, and the drive chip enters the ready state. The host computer can communicate with the MCU via CAN to send drive voltage configuration commands. After the chip completes the output voltage configuration, it enters the ready state again, which can realize the smooth switching of drive voltage and meet the test verification requirements of different SiC MOSFETs.

[0041] Example 1: Hardware Implementation of a Multi-Voltage Programmable Control System: This example details the hardware selection, connection relationships, and working principle of a SiC MOSFET multi-voltage adaptive control system based on programmable drivers, ensuring that those skilled in the art can implement the hardware system according to this example.

[0042] The control system in this embodiment includes a control board, a driver board, and a SiC MOSFET three-phase full-bridge module. The control board uses the Infineon TC275 microcontroller as the core control chip. This chip has high computing speed and rich peripheral interfaces, which can meet the real-time control requirements of the electric drive system of new energy commercial vehicles. The power input terminal of the control board is connected to the vehicle's +24V DC power supply. The +24V is converted to a stable +15V through the onboard DC-DC step-down module. Power and signal transmission are realized through the Tyco 2.54mm connector. The control board is equipped with a CAN bus interface to communicate with the vehicle controller (VCU), and an SPI interface to communicate with the GD3160 driver chip of the driver board. It is also equipped with an analog signal acquisition interface to collect the power module temperature and phase current signals through temperature and current sensors.

[0043] The driver board is the core execution unit of the system, mainly consisting of a flyback switching power supply, a negative voltage adjustable LDO, six NXPGD3160 isolated driver chips, and peripheral circuitry. The flyback switching power supply uses a ferrite core transformer with a 17Ts primary winding, a 28Ts and 18Ts secondary winding with a center tap, and an 18Ts feedback winding. The full-wave rectifier diode is an ES1D (200V / 1A), which features fast recovery characteristics to meet high-frequency switching requirements. The flyback switching power supply converts the +15V input from the control board into a dual-path isolated power supply with a positive and negative voltage ripple of no more than ±3%. The positive output is directly connected to the VCC pin of the GD3160 to provide positive power to the driver chip, while the negative output is connected to the Vin input of the negative voltage adjustable LDO.

[0044] The negative voltage adjustable LDO uses a low dropout linear regulator. Its ADJ pin is connected to the TSENSEA pin of the GD3160 and ground via a resistor network R3, R4, and R5, where R3 = 1000Ω, R4 = 1850Ω, and R5 = 1000Ω. The current source output from the TSENSEA pin can adjust the feedback voltage of the LDO, thereby achieving a programmable negative voltage output. When the current source is turned off, the output voltage of the LDO satisfies the formula... The calculated output voltage is 5V, meaning a -5V negative voltage is supplied to the GD3160; when the current source is turned on and set to 1mA, the output voltage satisfies the formula. The calculated output voltage is 4V, which means that a -4V negative voltage is supplied to the GD3160. The LDO's output terminal VEE is directly connected to the VEE pin of the GD3160, and the voltage output accuracy can reach ±1%.

[0045] The GD3160 is an isolated driver chip that integrates standard protection functions such as desaturation protection, active Miller clamping (AMC), and soft shutdown. This embodiment uses six chips, corresponding one-to-one with six SiC MOSFETs. The GH and GL pins of the driver chip are connected to the gate and source of the SiC MOSFETs, respectively, providing gate drive signals. The PWM pin is connected to the TC275 microcontroller on the control board to receive PWM drive commands. The GD3160's desaturation protection voltage threshold is configured to 6V via an external resistor, with a protection time of less than 2µs. The overcurrent protection current threshold is configured to 900A, effectively preventing damage to the SiC MOSFETs due to overcurrent. Its VCCREG pin is configured via SPI to output a voltage range of 15-18V in 1V steps, enabling programmable positive voltage adjustment. Combined with a negative voltage adjustable LDO, it can achieve various voltage combinations such as -4V / +15V, -4V / +18V, -5V / +15V, and -5V / +18V.

[0046] The SiC MOSFET three-phase full-bridge module uses automotive-grade SiC MOSFETs. Six devices are connected in series in pairs to form three half-bridge modules, corresponding to the U, V, and W phase outputs of the motor. Each SiC MOSFET has a freewheeling diode connected in parallel to its drain and source. The gate is connected to the GH pin of the GD3160 after being connected in series with a current-limiting resistor, and the source is connected to the GL pin of the GD3160, realizing the on / off control of the SiC MOSFET by the driver chip.

[0047] The signal connection between the control board and the driver board uses shielded wires, the CAN bus uses twisted-pair cables, and the SPI communication uses differential signal lines, which effectively reduces electromagnetic interference and improves the reliability of signal transmission. The PCB layout of the driver board adopts a design that separates the power circuit and the signal circuit. The daisy-chain communication traces are arranged close to the power circuit, which reduces parasitic inductance and capacitance and improves the high-frequency performance of the system.

[0048] The hardware system of this embodiment achieves programmable adjustment of the driving voltage through the above design. One hardware platform can adapt to the driving voltage requirements of various SiC MOSFETs. Compared with the existing fixed output driving scheme, there is no need to redesign the driving board. Compared with the multi-chip parallel scheme, it significantly reduces the number of driving chips and isolation power supplies used, thereby reducing hardware costs and PCB area. The BOM cost of the hardware system of this embodiment is reduced by more than 40% and the PCB area is reduced by more than 50% compared with the multi-chip parallel scheme.

[0049] Example 2: Implementation of Dynamic Adaptive Control Method Based on Junction Temperature and Current: This example is based on the hardware system of Example 1 and elaborates on the multi-voltage adaptive control method of SiC MOSFET, including sampling strategy, junction temperature estimation, voltage switching logic, power-on initialization and double-pulse test process, to ensure that those skilled in the art can implement the control method through software programming.

[0050] The control method in this embodiment is based on the Infineon TC275 microcontroller and is programmed in the TriCore development environment using C language. The control program mainly includes modules such as main program, sampling interrupt service routine, CAN communication interrupt service routine, SPI communication subroutine, and fault handling subroutine. The main program is responsible for the system's power-on initialization and main loop scheduling, the interrupt service routine is responsible for real-time signal acquisition and instruction reception, and the subroutines are responsible for the specific function implementation.

[0051] The sampling strategy implements a control board that acquires the power module's temperature signal via an NTC temperature sensor and the three-phase current signal via a Hall effect current sensor. The output signals from the temperature and current sensors are converted into 0-5V analog voltage signals after signal conditioning circuitry and input to the TC275's ADC acquisition interface. The system is configured with the ADC in continuous sampling mode. The phase current sampling frequency is set to 100µs, implemented via a timer interrupt, triggering ADC sampling every 100µs to acquire the instantaneous values ​​of the three-phase currents. The effective value (Irms) of the phase current is calculated by software. The power module temperature sampling frequency is set to 10ms, implemented via another timer interrupt, triggering ADC sampling every 10ms to acquire the power module temperature and cooling water temperature, avoiding excessive processor load due to high-frequency sampling.

[0052] Junction temperature estimation is implemented in the temperature sampling interrupt service routine. Based on the collected power module temperature and water temperature, the primary junction temperature of the SiC MOSFET is estimated using the formula: Junction Temperature = (Module Temperature - Water Temperature) / 30% + Water Temperature. This formula is a classic formula for estimating the junction temperature of automotive SiC MOSFETs and can accurately reflect the actual junction temperature of the device. A junction temperature storage variable is set in the program, and each estimated junction temperature value overwrites the previous value, providing data support for the voltage switching logic.

[0053] The dynamic voltage switching logic reads the junction temperature and phase current RMS values ​​in real time during the main loop and executes the voltage switching logic. The program sets the junction temperature thresholds T1=145℃ and T2=135℃, and the current thresholds I1=550A and I2=450A. The specific logic is as follows: (1) When the junction temperature T > T1, the program immediately sends a voltage configuration command of +15V / -5V to the SPI communication subroutine. The system is forced to enter the protection mode. At the same time, the flag bit is set to shield all current-based adjustment paths. The junction temperature is continuously monitored in the main loop until T < T2. Then the shielding flag bit is cleared and the current adjustment path is unlocked again. (2) When T < T2, the program judges the effective value of the phase current Irms. If Irms > I1, it sends a voltage configuration command of +18V / -5V and the system enters the heavy load high efficiency mode. If Irms < I2, a voltage configuration command of +15V / -4V is sent, and the system enters standard mode. If I2 ≤ Irms ≤ I1, the program does not send any voltage configuration command, maintaining the current drive voltage mode to avoid frequent switching caused by current fluctuations. A sending delay is set for the voltage configuration command in the program, with a 10ms delay after each command is sent before the next judgment is executed, ensuring smooth voltage switching and avoiding system oscillations caused by frequent switching.

[0054] The SPI communication subroutine is responsible for transmitting voltage configuration commands to six GD3160 driver chips. The program configures the SPI communication baud rate to 2MHz, with a 24-bit data frame. Data is sent in a daisy-chain order (U-phase upper bridge → U-phase lower bridge → V-phase upper bridge → V-phase lower bridge → W-phase upper bridge → W-phase lower bridge). Each data frame contains the chip address, voltage configuration command, and parity bit. After receiving the data, the GD3160 configures the positive voltage output of the VCCREG pin and the current source of the TSENSEA pin according to the command, achieving synchronous adjustment of the positive and negative voltages. The subroutine includes a data transmission confirmation mechanism; if no acknowledgment signal is received from the GD3160, the data is retransmitted to ensure reliable command transmission.

[0055] After the system is powered on, the main program first executes the power-on initialization process, which initializes the MCU's peripheral interfaces (ADC, SPI, CAN, timers, etc.), the driver chip GD3160, sensors, etc. in sequence. After initialization, the program reads the default voltage configuration parameters (-4V / +15V) and sends them to GD3160 through the SPI communication subroutine. After GD3160 completes the positive and negative voltage circuit configuration, it sends a ready signal to the control board. After receiving the ready signal, the control board sets the driver ready flag, and the system enters the normal working state, waiting to receive CAN bus commands or execute dynamic voltage switching logic.

[0056] The CAN communication and dual-pulse test implementation CAN communication interrupt service program is responsible for receiving voltage configuration commands issued by the vehicle controller or host computer. The CAN bus baud rate is set to 500kbps and the CAN2.0B protocol is used. The command contains information such as the target voltage combination and check bit. After receiving the command, the program performs verification. After the verification is successful, the command is transmitted to the SPI communication subroutine to realize the manually configured voltage switching.

[0057] The system supports dual-pulse testing and verification of SiC modules from different manufacturers. During testing, the host computer is connected to the control board via a CAN bus. The host computer sends a dual-pulse test command. After receiving the command, the control board first configures the drive voltage. Once the drive chip enters the ready state, it sends a dual-pulse PWM signal to the SiC MOSFET and collects parameters such as switching losses and short-circuit withstand capability. After the test is completed, the host computer can send a new voltage configuration command, and the control board can smoothly switch the drive voltage to continue testing without changing the hardware platform, which greatly simplifies the testing process.

[0058] The fault handling subroutine is responsible for receiving fault signals from the GD3160. The program configures the TC275's GPIO port to interrupt input mode, connecting it to the GD3160's fault signal outputs INTAH, INTAL, and INTB. When a fault signal is detected, a GPIO interrupt is immediately triggered, entering the fault handling subroutine. The subroutine executes corresponding protection actions based on the fault type: if the fault is triggered by an INTAH or INTAL signal, it is determined to be a serious fault, immediately blocking all PWM outputs to prevent SiC MOSFET shoot-through damage and controlling system shutdown; if the fault is triggered by an INTB signal, it is determined to be a non-immediately fatal fault. The program queries the fault driver and fault type via the SPI communication subroutine, records the fault log, and sends a warning message to the host computer via the CAN bus, without triggering an emergency stop.

[0059] The control method in this embodiment achieves dynamic adaptive switching of the driving voltage through the above design. It can optimize the driving voltage in real time according to the actual operating conditions of the SiC MOSFET. Compared with the existing fixed voltage driving method, the conduction loss of SiC MOSFET is reduced by more than 15%, the switching loss is reduced by more than 10%, and the system efficiency is improved by 3%-5%. At the same time, the implementation of the dual-pulse test process greatly simplifies the testing and verification of different SiC MOSFETs and shortens the test time by more than 60%.

[0060] Example 3: Implementation of Daisy-Chain Communication and Hierarchical Fault Protection: This example, based on the hardware system of Example 1 and the control method of Example 2, elaborates on the daisy-chain communication design and hierarchical fault protection mechanism of 6 GD3160 driver chips, including the hardware connection of the daisy chain, SPI communication timing, grouping and parallel connection of fault signals, and coordinated control of fault protection, highlighting the advantages of this design in reducing costs and improving fault response speed.

[0061] The hardware connection for daisy-chain communication uses six GD3160 driver chips to connect to the TC275 microcontroller on the control board. Specifically, the SPI_MOSI pin of the TC275 is connected to the MOSI pin of the first GD3160 (U-phase upper bridge); the MISO pin of the first GD3160 is connected to the MOSI pin of the second GD3160 (U-phase lower bridge); the MISO pin of the second GD3160 is connected to the MOSI pin of the third GD3160 (V-phase upper bridge); and the MISO pin of the third GD3160 is connected to the MOSI pin of the fourth GD3160 (U-phase lower bridge). The MOSI pin of the (V-phase lower bridge) is connected to the MOSI pin of the fifth chip (W-phase upper bridge), the MISO pin of the fifth chip is connected to the MOSI pin of the sixth chip (W-phase lower bridge), and the MISO pin of the sixth GD3160 (W-phase lower bridge) is connected back to the SPI_MISO pin of the TC275. The SPI_SCLK pin and SPI_CSB pin of the TC275 are connected to the SCLK pin and CSB pin of all GD3160 chips respectively to realize the synchronous transmission of clock signal and chip select signal.

[0062] This daisy-chain connection uses unidirectional series routing, which perfectly matches the linear arrangement of a three-phase full-bridge circuit on the PCB. It allows for close placement within the power loop, significantly shortening trace length, reducing parasitic parameters, and improving the system's high-frequency performance. Compared to a star connection, the daisy-chain connection eliminates the need for a separate SPI isolation circuit for each driver chip; isolation is implemented internally by the GD3160 chip, significantly reducing system hardware cost and complexity. In this embodiment, the isolation circuit cost is more than 70% lower than that of a star connection.

[0063] The SPI communication timing is implemented using synchronous serial communication. The program is configured with the TC275 SPI controller in master mode and the GD3160 in slave mode. The communication baud rate is 2MHz, and the data frame is 24-bit. The SPI transmission timing strictly follows the requirements of the GD3160 chip datasheet. CSB is the chip select signal, which is active low. SCLK is the clock signal, which samples data on the rising edge and transmits data on the falling edge. MOSI is the instruction data sent by the control board to the driver chip, and MISO is the status data returned by the driver chip to the control board.

[0064] The data frame format is as follows: the first 3 bits are the chip address, used to identify the six GD3160 chips; the middle 16 bits are the valid instruction data (including positive voltage configuration, negative voltage configuration, protection function configuration, etc.); and the last 5 bits are the check bits, using CRC5 verification to ensure the accuracy of data transmission. During communication, the control board first pulls the CSB pin low and sends the clock signal and instruction data. The six GD3160 chips identify their own instructions based on the chip address, execute the corresponding configuration actions, and send the chip status data back to the control board through the MISO pin. After receiving the status data, the control board pulls the CSB pin high, completing one SPI communication. The time for a single communication is less than 12µs, meeting the requirements of real-time control.

[0065] The fault signals are grouped and connected in parallel. The GD3160 driver chip integrates two fault interrupt signal outputs, INTA and INTB. INTA is a critical fault signal (such as desaturation fault, short circuit fault, etc.), and INTB is a general fault signal (driver chip over-temperature alarm, module over-temperature alarm). In this embodiment, the fault signals of 6 GD3160 chips are grouped and connected in parallel. Specifically, the INTA terminals of the 3 GD3160 chips corresponding to the UVW three-phase upper bridge driver are connected in parallel through current-limiting resistors to form an INTAH signal, which is connected to one GPIO interrupt pin of the TC275; the INTA terminals of the 3 GD3160 chips corresponding to the UVW three-phase lower bridge driver are connected in parallel through current-limiting resistors to form an INTAL signal, which is connected to another GPIO interrupt pin of the TC275; the INTB terminals of all 6 GD3160 chips in the UVW three-phase upper and lower bridges are connected in parallel through current-limiting resistors to form a unified INTB signal, which is connected to the third GPIO interrupt pin of the TC275.

[0066] The parallel connection of fault signals reduces PCB trace length and loop area, lowers the risk of interference from power loops, and improves signal integrity. At the same time, the design of the current-limiting resistor can prevent current sinking damage when fault signals are connected in parallel, thus improving the reliability of the circuit.

[0067] The graded fault protection mechanism is implemented through the coordinated control of hardware circuits and software programs. The total fault response and delay time is less than 8µs, which is much faster than the speed at which the MCU reads the status registers one by one via SPI daisy chain, thus meeting the requirements of real-time protection. The specific protection logic is as follows: (1) Severe fault protection: When a GD3160 detects a severe fault such as overcurrent or overtemperature, its INTA pin outputs a low level. If it is an upper bridge chip, it triggers an INTAH signal interrupt; if it is a lower bridge chip, it triggers an INTAL signal interrupt. After receiving the interrupt signal, the TC275 immediately enters the fault handling subroutine and blocks all PWM outputs within 8us to prevent SiCMOSFETs from being damaged due to bridge arm shoot-through. At the same time, it controls the flyback switching power supply to stop output, realizing the emergency shutdown protection of the system. After shutdown, the program queries the specific fault driver and fault type through the SPI communication subroutine and records the fault log.

[0068] (2) General fault protection: When a GD3160 detects a general fault such as module temperature alarm or driver chip temperature alarm, its INTB pin outputs a low level, triggering an INTB signal interrupt. After receiving the interrupt signal, the TC275 enters the fault handling subroutine, queries the fault driver and fault type through the SPI communication subroutine, records the fault log, and sends a warning message to the host computer and vehicle controller through the CAN bus. It does not trigger an emergency stop and the system continues to run. If the fault persists, the program will gradually reduce the system output power until the fault is eliminated.

[0069] (3) Coordinated protection with dynamic voltage regulation: When the system executes the dynamic voltage regulation strategy and increases the driving voltage of a certain bridge arm to reduce conduction loss, the overcurrent risk of the SiC MOSFET of that bridge arm increases. At this time, the corresponding fault signal group (INTAH or INTAL) is in real-time monitoring. Once an overcurrent fault is detected, the protection action can be triggered within 8us, which provides a key safety guarantee for the dynamic optimization algorithm and realizes the coordination of performance optimization and fault protection.

[0070] The daisy-chain communication and hierarchical fault protection design in this embodiment not only significantly reduces the hardware cost and complexity of the system, but also enables rapid fault response and hierarchical processing, improving the reliability and maintainability of the system. Compared with existing driver solutions, the fault response speed is improved by more than 80%, and the mean time between failures (MTBF) of the system is improved by more than 50%.

[0071] Comparative Examples: To verify the beneficial effects of the present invention, two sets of comparative examples were set up, namely a fixed output driving scheme and a multi-chip parallel driving scheme in the prior art. These were compared with the technical solution of the present invention in terms of hardware adaptability, cost, PCB area, system efficiency, and testing time. The comparison results are as follows: Compared to Example 1, the fixed output drive solution uses the TIUCC21750 dedicated driver chip to build the drive circuit, outputting a fixed -4V / +15V drive voltage. The hardware is a specialized design, only compatible with a single type of SiC MOSFET. While this solution has low hardware cost, its compatibility is extremely poor. Replacing the SiC MOSFET requires a redesigned driver board, with a development cycle of approximately two months. Testing and verification require a dedicated hardware platform, taking about ten days. Furthermore, dynamic voltage optimization is not possible, and the SiC MOSFET exhibits high conduction losses under heavy load conditions, resulting in a system efficiency of approximately 94%.

[0072] Compared to Example 2, the multi-chip parallel driving scheme uses the TIUCC21750 (-4V / +15V) and another fixed-output driver chip (-5V / +18V) in parallel, along with two sets of isolated power supplies, to adapt to two different SiC MOSFETs. This scheme offers improved compatibility compared to Example 1, but it suffers from higher system complexity. Six SiC MOSFETs require 12 driver chips and six sets of isolated power supplies, resulting in a BOM cost 2.5 times that of this invention, a PCB area twice that of this invention, higher inventory management complexity, a development cycle of approximately 1.5 months, and testing and verification requiring the construction of two hardware platforms with a testing time of approximately 7 days. Dynamic voltage optimization is also not achievable, and the system efficiency is approximately 94.5%.

[0073] This invention provides a hardware platform that adapts to SiC MOSFETs with various voltage combinations such as -4V / +15V and -5V / +18V, eliminating the need for redesigning the driver board and shortening the development cycle to within one week. Testing and verification require only one hardware platform, reducing testing time to three days. The BOM cost is reduced by more than 40% compared to Comparative Example 2, and the PCB area is reduced by more than 50%. Through dynamic voltage optimization, the system efficiency is improved to 98%-99%, the conduction loss of SiC MOSFETs is reduced by more than 15%, and the switching loss is reduced by more than 10%. The graded fault protection mechanism enables rapid fault response with a fault response time of less than 8µs, and the system MTBF is improved by more than 50% compared to Comparative Example 2.

[0074] As can be seen from the above comparison, the technical solution of the present invention is significantly superior to the existing technical solutions in terms of hardware adaptability, cost control, system efficiency, testing and verification efficiency, and reliability, and has extremely high engineering application value.

[0075] The SiC MOSFET multi-voltage adaptive control system and method based on programmable drive of the present invention are applicable to electric drive systems of new energy commercial vehicles, and can also be extended to SiC MOSFET drives in new energy passenger vehicles, rail transit, energy storage systems and other fields. A single hardware platform can adapt to the drive voltage requirements of various SiC MOSFETs, significantly reducing development and material costs, improving system efficiency and reliability, and has good market prospects and industrial applicability.

[0076] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A SiC MOSFET multi-voltage adaptive control system based on programmable drive, characterized in that, It includes a control board, a driver board, and a SiC MOSFET three-phase full-bridge module. The core of the control board is an Infineon TC275 microcontroller. Its input terminal is connected to the vehicle's +24V power supply and stepped down to 15V before being transmitted to the driver board. The control board communicates with the vehicle controller via a CAN bus and is connected to the driver board via SPI. The driver board includes a flyback switching power supply, a negative voltage adjustable LDO, and six NXP GD3160 isolated driver chips. The flyback switching power supply uses a center-tapped transformer to convert 15V into positive and negative isolated power supplies. Its positive voltage output is connected to the VCC pin of the GD3160, and its negative voltage output is connected to the input of the negative voltage adjustable LDO. The output of the negative voltage adjustable LDO is connected to the VEE pin of the GD3160. The SiC MOSFET three-phase full bridge consists of three half-bridge modules composed of six SiC MOSFETs, which are driven one-to-one with six GD3160 chips respectively; The GD3160 can be configured via SPI to output a 15-18V positive voltage through the VCCREG pin, and can be configured via the TSENSEA pin to adjust the negative voltage of the adjustable LDO outputting -4V or -5V. The control board collects the temperature and phase current of the power module, and realizes dynamic adaptive switching of the drive voltage based on a preset threshold. The six GD3160 chips are connected by daisy chain communication. Fault signals are transmitted to the control board after being grouped and connected in parallel to realize hierarchical protection. The dynamic switching threshold of the driving voltage is as follows: when the junction temperature T > 145℃, it is forced to enter the +15V / -5V protection mode, and the current adjustment path is blocked. When the junction temperature drops back to T < 135℃, it is unlocked. When T < 135℃, Irms > 550A triggers the +18V / -5V heavy load mode, Irms < 450A triggers the +15V / -4V standard mode, and 450A ≤ Irms ≤ 550A maintains the current mode. The fault signals of the GD3160 include INTA and INTB. The INTA terminals of the three GD3160s on the three-phase upper bridge are connected in parallel to form INTAH, the INTA terminals of the three GD3160s on the three-phase lower bridge are connected in parallel to form INTAL, and the INTB terminals of the six GD3160s are connected in parallel.

2. The SiC MOSFET multi-voltage adaptive control system based on programmable drive according to claim 1, characterized in that: The adjustable negative voltage LDO achieves voltage regulation by adjusting the feedback voltage through adjusting the current source. When the current source is off, it outputs -5V; when the 1mA current source is on, it outputs -4V. Its voltage calculation satisfies the following formula: and ； Among them, the LDO output Vo is the driving negative voltage, and R3, R4, and R5 are fixed resistors for the feedback network.

3. The SiC MOSFET multi-voltage adaptive control system based on programmable drive according to claim 1, characterized in that: The control board samples the phase current at a frequency of 100µs and the power module temperature at a frequency of 10ms. The junction temperature is estimated using the formula: Junction temperature = (Module temperature - Water temperature) / 30% + Water temperature.

4. The SiC MOSFET multi-voltage adaptive control system based on programmable drive according to claim 1, characterized in that: The daisy-chain communication data transmission sequence of the 6 GD3160 chips is as follows: U phase up bridge → U phase down bridge → V phase up bridge → V phase down bridge → W phase up bridge → W phase down bridge. The SPI communication baud rate is 2MHz and the data frame is 24 bits.

5. The SiC MOSFET multi-voltage adaptive control system based on programmable drive according to claim 1, characterized in that: The GD3160 integrates desaturation protection, active Miller clamping, and soft shutdown functions. The desaturation protection voltage threshold is 6V, the protection time is less than 2µs, and the overcurrent protection current threshold is 900A.

6. The SiC MOSFET multi-voltage adaptive control system based on programmable drive according to claim 1, characterized in that: The primary winding of the flyback switching power supply transformer is 17Ts, the secondary winding with the center tap is 28Ts and 18Ts, the feedback winding is 18Ts, and the full-wave rectifier diode is ES1D.

7. The SiC MOSFET multi-voltage adaptive control system based on programmable drive according to claim 1, characterized in that: After the system is powered on and initialized, it reads the default -4V / +15V configuration, completes the positive and negative voltage circuit configuration, and enters the drive ready state. After receiving the CAN bus voltage configuration command, it can achieve smooth switching of the output voltage.

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