Pulse control hold circuit architecture and method for a spaceborne computer

Abstract

The application relates to a pulse control holding circuit structure and method for a satellite computer, and the circuit structure comprises a turn-on trigger unit, an off trigger unit, a state holding unit and a power switch unit; the turn-on trigger unit comprises a first tri-state buffer gate, the off trigger unit comprises a second tri-state buffer gate, the state holding unit comprises an N-channel MOS tube and a holding capacitor, and the power switch unit comprises a P-channel MOS tube. The application can realize the state self-holding of the power MOS tube by only pulse triggering without relying on the continuous output level of a single-chip microcomputer, and improves the reliability and safety of the power supply control of the satellite computer.

Description

Technical Field

[0001] This application relates to the field of electronic communication technology, and in particular to a pulse control and holding circuit structure and method for a spaceborne computer. Background Technology

[0002] In spaceborne computers and industrial electronics applications, the power-on and power-off control of external devices is usually achieved by using the GPIO of a microcontroller to directly output a continuous high / low level to drive the MOSFET.

[0003] However, this continuous level driving method is highly dependent on the working state of the microcontroller: when the microcontroller is reset, crashes, or restarts abnormally, the level state of the GPIO pin is uncertain (it may become a high impedance state, random high / low level), which may cause the power MOSFET to be falsely turned on or falsely turned off, thereby causing the back-end device to be powered on or off unexpectedly, resulting in system failure or even safety accident.

[0004] Especially in space environments, microcontrollers are susceptible to anomalies such as single-event upsets due to space radiation, increasing the probability of GPIO state malfunction. Furthermore, the microcontroller needs to continuously output voltage levels to maintain the MOSFET state, increasing the system's static power consumption. Also, the GPIO's prolonged connection to the power MOSFET gate makes it vulnerable to electromagnetic interference from the power circuit, leading to voltage level jumps and further exacerbating the risk of MOSFET malfunction.

[0005] Therefore, how to solve the technical problem of the risks brought about by the direct driving of MOSFETs by the GPIO of a microcontroller is a problem that urgently needs to be solved in this field. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the prior art, this application provides a pulse control holding circuit structure and method for spaceborne computers. It does not rely on the continuous output level of the microcontroller, but only requires pulse triggering to realize the state self-holding of the power MOSFET, thereby improving the reliability and safety of the power supply control of the spaceborne computer.

[0007] The embodiments of this application adopt the following technical solutions: In a first aspect, this application provides a pulse control holding circuit structure for a spaceborne computer, including a turn-on trigger unit, a turn-off trigger unit, a state holding unit, and a power switch unit; The conduction triggering unit includes a first tri-state buffer gate. The input terminal of the first tri-state buffer gate is connected to a first power supply voltage. The output enable terminal of the first tri-state buffer gate is connected to the first power supply voltage through a first pull-up resistor and is used to receive a conduction low-level pulse signal. The shutdown trigger unit includes a second tri-state buffer gate. The input terminal of the second tri-state buffer gate is grounded, and the output enable terminal of the second tri-state buffer gate is connected to the first power supply voltage through a second pull-up resistor and is used to receive a shutdown low-level pulse signal. The state holding unit includes an N-channel MOSFET and a holding capacitor; the output terminals of the first tri-state buffer gate and the second tri-state buffer gate are both connected to the gate of the N-channel MOSFET; the holding capacitor is connected between the gate of the N-channel MOSFET and ground; the gate of the N-channel MOSFET is also grounded through a first pull-down resistor and connected to the circuit output terminal through a third pull-up resistor; the source of the N-channel MOSFET is grounded. The power switching unit includes a P-channel MOSFET, the source of which is connected to a second power supply voltage, and the gate of which is connected to a first node via a current-limiting resistor; the first node is connected to the second power supply voltage via a fourth pull-up resistor, and is connected to the drain of the N-channel MOSFET via a second pull-down resistor; the drain of the P-channel MOSFET is the circuit output terminal.

[0008] By employing the above technical solution, two tri-state buffer gates are used to preset high and low level inputs respectively. A short low-level pulse at the output enable terminal can trigger the N-channel MOSFET to turn on and off respectively. A holding capacitor stores the gate charge, and a third pull-up resistor forms positive output feedback, achieving long-term self-holding of the N-channel MOSFET's state after the pulse disappears and the tri-state gate returns to a high-impedance state. The drain of the N-channel MOSFET drives the gate of the P-channel MOSFET through a second pull-down resistor and a current-limiting resistor, thus controlling the power supply to the backend device. The entire solution completely eliminates the dependence on the continuous output level of the microcontroller, avoiding the problem of malfunctioning power MOSFETs when the microcontroller malfunctions.

[0009] In some implementations, the output enable terminals of both the first and second tri-state buffer gates are active low. When the output enable terminal receives a low-level pulse signal, the tri-state buffer gate is turned on and outputs; when the output enable terminal is high, the tri-state buffer gate outputs a high-impedance state.

[0010] By adopting the above technical solution, using a low-level active output enable combined with a pull-up resistor with a default high level design, the tri-state buffer gate is always in a high-impedance state when there is no pulse input, so as not to interfere with the holding node.

[0011] In some embodiments, the state holding unit further includes a clamping diode, which is a Zener diode with its cathode connected to the gate of the N-channel MOSFET and its anode grounded, for clamping the gate voltage of the N-channel MOSFET below the regulated value.

[0012] By adopting the above technical solution, the gate voltage of the N-channel MOSFET is clamped within a safe range by using the method of connecting the cathode of the Zener diode to the gate and the anode to the ground, thus protecting the gate oxide layer from overvoltage damage.

[0013] In some implementations, the discharge time constant formed by the product of the holding capacitor's capacitance and the first pull-down resistor's resistance is greater than the required minimum holding time.

[0014] By adopting the above technical solution and maintaining a reasonable configuration of the capacitor value and the first pull-down resistor value, the discharge time constant meets the minimum holding time required by the system, ensuring that the circuit state can be reliably maintained for a sufficiently long time after the pulse disappears.

[0015] In some embodiments, the resistance value of the current-limiting resistor is less than the resistance value of the fourth pull-up resistor; when the N-channel MOSFET is off, the gate of the P-channel MOSFET is pulled up to near the second power supply voltage by the fourth pull-up resistor, and the P-channel MOSFET is off; when the N-channel MOSFET is on, the gate of the P-channel MOSFET is pulled down to near ground potential through the current-limiting resistor and the on-state N-channel MOSFET, and the P-channel MOSFET is on.

[0016] By adopting the above technical solution, and utilizing the resistance values ​​of the current-limiting resistor and the fourth pull-up resistor, it is ensured that when the N-channel MOSFET is turned off, the gate of the P-channel MOSFET is reliably pulled up to the off state, and when the N-channel MOSFET is turned on, the gate of the P-channel MOSFET is quickly pulled down to the on state, thus avoiding intermediate gate potential states and ensuring stable switching action without false triggering.

[0017] In some implementations, a status readback unit is also included, which includes a voltage divider resistor network connected in series between the circuit output and ground, and a comparator; the non-inverting input of the comparator is connected to the voltage divider node, the inverting input is connected to the reference voltage, and the output is connected to the readback port of the microcontroller.

[0018] By adopting the above technical solution, the microcontroller can obtain the power supply status of the back-end equipment in real time without sending control pulses, which facilitates telemetry monitoring and fault diagnosis.

[0019] In some embodiments, the state holding unit is provided with three independent groups; the gates of the N-channel MOS transistors of the three groups of state holding units are respectively connected to the output terminals of the first tri-state buffer gate and the second tri-state buffer gate through isolation resistors; the drains of the N-channel MOS transistors of the three groups of state holding units are connected to the gate of the P-channel MOS transistor through a three-out-of-two voting circuit. By adopting the above technical solution, even if one group of state-keeping units flips due to radiation, the other two groups still maintain the correct state. The three-out-of-two voting ensures the correct output and significantly improves radiation resistance reliability.

[0020] In some implementations, the three sets of state-holding units are spatially distributed on the PCB, with the spacing between adjacent sets of state-holding units being greater than the typical influence radius of a single-event effect.

[0021] By adopting the above technical solution, the spatially distributed arrangement reduces the probability of a single high-energy particle simultaneously affecting multiple state-preserving units, thereby enhancing the effectiveness of triple redundancy.

[0022] Secondly, this application provides a pulse control and holding method for a spaceborne computer, applied to the pulse control and holding circuit structure for a spaceborne computer described in the first aspect, comprising: Power-on initialization steps: After power-on, the output enable terminals of the first and second tri-state buffer gates are pulled to high level through the first and second pull-up resistors, both outputting a high-impedance state; the gate of the N-channel MOSFET is pulled to low level through the first pull-down resistor, and the N-channel MOSFET is turned off; the gate of the P-channel MOSFET is pulled up to near the second power supply voltage through the fourth pull-up resistor, and the P-channel MOSFET is turned off. There is no voltage output at the circuit output terminal, and the back-end device is in the default power-off state. Conduction control steps: A short low-level pulse is applied to the output enable terminal of the first tri-state buffer gate, turning on the first tri-state buffer gate, transmitting the first power supply voltage to the gate of the N-channel MOSFET and charging the holding capacitor, turning on the N-channel MOSFET, pulling the drain of the N-channel MOSFET low, and pulling the gate of the P-channel MOSFET low through the current-limiting resistor and the second pull-down resistor, turning on the P-channel MOSFET, and outputting the second power supply voltage at the circuit output terminal; after the pulse disappears, the first tri-state buffer gate returns to the high-impedance state, and the holding capacitor and the third pull-up resistor together maintain the gate charge of the N-channel MOSFET, keeping both the N-channel MOSFET and the P-channel MOSFET on, achieving self-holding of the conduction state; Shutdown control steps: A short low-level pulse is applied to the output enable terminal of the second tri-state buffer gate, turning on the second tri-state buffer gate and transferring the ground potential to the gate of the N-channel MOSFET. The charge on the holding capacitor is discharged, the N-channel MOSFET is turned off, and the gate of the P-channel MOSFET is pulled up to near the second power supply voltage, turning off the P-channel MOSFET and de-energizing the circuit output. After the pulse disappears, the second tri-state buffer gate returns to the high-impedance state, and the first pull-down resistor maintains the gate of the N-channel MOSFET at a low level. The N-channel MOSFET and the P-channel MOSFET remain off, achieving self-holding of the shutdown state.

[0023] By adopting the above technical solution, three complete steps are provided: power-on initialization, conduction control, and shutdown control. The state is maintained for a long time by holding the capacitor and the third pull-up resistor, and the microcontroller does not need to continuously participate in the control.

[0024] In some implementations, during the turn-on control step, the pulse width of the low-level short pulse is greater than the time required for the holding capacitor to charge to the gate-on threshold of the N-channel MOS transistor through the output impedance of the first tri-state buffer gate.

[0025] By adopting the above technical solution, the pulse width is constrained to ensure that the capacitor is fully charged, thus guaranteeing the reliability of each trigger.

[0026] In summary, this application includes at least the following beneficial technical effects: 1. By using two tri-state buffer gates to preset high and low level inputs respectively, the N-channel MOSFET can be triggered to turn on and off separately by a short low-level pulse at the output enable terminal. A holding capacitor stores the gate charge, and a third pull-up resistor forms positive output feedback, achieving long-term self-holding of the N-channel MOSFET's state after the pulse disappears and the tri-state gate returns to a high-impedance state. The drain of the N-channel MOSFET drives the gate of the P-channel MOSFET through a second pull-down resistor and a current-limiting resistor, realizing the on / off control of power supply to the backend device. The entire scheme completely eliminates the dependence on the continuous output level of the microcontroller, avoiding the problem of power MOSFET malfunction when the microcontroller is abnormal.

[0027] 2. By employing a three-set state-holding unit configuration, even if one set of state-holding units experiences a state flip due to radiation, the other two sets maintain the correct state. This three-out-of-two voting method ensures correct output, significantly improving radiation resistance reliability. Furthermore, the spatially distributed arrangement of the three sets of state-holding units reduces the probability of a single high-energy particle simultaneously affecting multiple sets of state-holding units, enhancing the effectiveness of triple redundancy.

[0028] 3. Positive feedback self-locking is provided to the gate of the N-channel MOSFET through the third pull-up resistor at the circuit output terminal. Only a single pulse trigger is needed to maintain the state for a long time without periodic refresh, thus completely eliminating the dependence on the microcontroller. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1A schematic diagram of a pulse control and holding circuit structure for a spaceborne computer provided in an embodiment of this application; Figure 2 This is a simulation diagram of the initial power-on state provided in an embodiment of this application; Figure 3 This is a simulation diagram of the trigger-on state provided in an embodiment of this application; Figure 4 This is a simulation diagram of the trigger shutdown state provided in the embodiments of this application; Figure 5 This is a flowchart of a pulse control and holding method for a spaceborne computer provided in an embodiment of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Furthermore, the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other.

[0032] The present application will now be described in detail with reference to the accompanying drawings and embodiments. Example 1

[0033] refer to Figure 1 As shown, Embodiment 1 of this application provides a pulse control and holding circuit structure for a spaceborne computer, including a turn-on trigger unit, a turn-off trigger unit, a state holding unit, and a power switch unit, used to control the power-on and power-off of the 12V backend spaceborne equipment, with a maximum output current of 5A. The external power supply of the circuit is introduced through a connector J1 with a through-hole pad. Pin 1 of J1 provides P12V (12V power supply), pin 2 provides P5V (5V power supply, 500mA), and pin 3 is GND.

[0034] In some implementations, the conduction trigger unit includes a first tri-state buffer gate U1. The first tri-state buffer gate U1 is an SN74AHC1G125-Q1 (SOT-23-5 package), with VCC (pin 5) connected to P5V, GND (pin 3) grounded, and a decoupling capacitor C1 (0.1μF, 0402 package, 16V withstand voltage) connected in parallel between VCC and GND.

[0035] Input terminal A (pin 2) of U1 is connected to the first power supply voltage P5V through R8 (10kΩ, 0603 package, 1% accuracy), so that the input terminal is stable at a 5V high level by default.

[0036] The output enable pin / OE (pin 1) of U1 is pulled up to P5V through the first pull-up resistor R5 (10kΩ, 0603 package, 1% accuracy), and is high (5V) by default. U1 outputs in a high-impedance state. The / OE pin is also connected to one end of the tactile switch SW1 (model TS665C), and the other end of SW1 is grounded. A filter capacitor C2 (0.1μF, 0402 package, 16V withstand voltage) is connected in parallel between the / OE pin and GND for button debouncing and anti-interference.

[0037] Operating status: When SW1 is not pressed, / OE=5V (high level), and the output terminal Y of U1 (pin 4) is in a high impedance state; when SW1 is pressed, / OE=0V (low level), U1 is turned on, and the output of Y = input of A = 5V.

[0038] In some implementations, the shutdown trigger unit includes a second tri-state buffer gate U2: The second three-state buffer gate U2 uses SN74AHC1G125-Q1. VCC is connected to P5V, GND is grounded, and a decoupling capacitor C3 (0.1μF, 0402 package, 16V withstand voltage) is connected in parallel between VCC and GND.

[0039] Input terminal A (pin 2) of U2 is grounded through R11 (10kΩ, 0603 package, 1% accuracy), so that the input terminal is at a default low level of 0V.

[0040] The U2 output enable pin / OE (pin 1) is pulled up to P5V through a second pull-up resistor R10 (10kΩ, 0603 package, 1% accuracy). The / OE pin is connected to a tactile switch SW2 (model TS665C), and the other end of SW2 is grounded. A filter capacitor C4 (0.1μF, 0402 package, 16V withstand voltage) is connected in parallel between the / OE pin and GND.

[0041] Operating status: When SW2 is not pressed, / OE=5V, and U2 output is in a high impedance state; when SW2 is pressed, / OE=0V, U2 is turned on, and Y output=A input=0V.

[0042] In some implementations, the state holding unit includes an N-channel MOSFET Q2, a clamping diode D1, a third pull-up resistor R7, a first pull-down resistor R9, and holding capacitors CP9 and CP10. The N-channel MOSFET Q2 is an L2N7002LT1G (SOT-23 package), with a typical VGS(th) value of 1.5V~2.5V, a maximum VGS=±20V, a maximum VDS=60V, and a maximum ID=115mA.

[0043] The gate (G) of Q2 is connected to the common node of the output terminals Y of U1 and U2. The source (S) of Q2 is grounded. The drain (D) of Q2 is connected to the second pull-down resistor R6, and R6 is connected to the first node (denoted as node A) between the fourth pull-up resistor R3 and the current-limiting resistor R4.

[0044] The clamping diode D1 is an MM5Z5V1T1G (5.1V Zener diode, SOD-523 package). The cathode of D1 is connected to the gate of Q2, and the anode of D1 is grounded. Under normal operation (gate voltage < 5.1V), D1 is in reverse cutoff state and does not affect the circuit; when the gate voltage exceeds approximately 5.1V due to interference or overshoot, D1 breaks down in reverse, discharging excess charge to ground and protecting the gate oxide layer of Q2.

[0045] The third pull-up resistor R7 (150kΩ, 0603 package, 1% accuracy) is connected between the circuit output P12V_OUT and the connection node between the gate of Q2 and R9, providing an additional pull-up path for the gate of Q2, helping to maintain the conduction state of Q2, and providing a stable potential reference for the gate of Q2 in case of circuit abnormality.

[0046] The first pull-down resistor R9 (100kΩ, 0603 package, 1% accuracy) is connected between the gate of Q2 and GND. Its core function is to reliably pull the gate of Q2 to 0V when there is no conduction trigger signal, ensuring that Q2 is turned off, guaranteeing the stability of the initial state and the off state of the circuit, and avoiding false turn-on caused by the gate of Q2 being floating.

[0047] Holding capacitors CP9 (2.2μF, 0805 package, 100V) and CP10 (2.2μF, 0805 package, 100V) are connected in parallel between the gate of Q2 and GND, with a total capacitance of 4.4μF, to store charge and achieve self-holding function after the conduction pulse disappears.

[0048] The discharge time constant τ = R9 × (CP9 + CP10) = 100 kΩ × 4.4 μF = 440 seconds.

[0049] In some embodiments, the power switching unit includes a P-channel MOSFET Q1, a fourth pull-up resistor R3, a current-limiting resistor R4, gate filter capacitors CP3 and CP5, a second pull-down resistor R6, and output filter capacitors CP1 and CP2; wherein: The P-channel MOSFET Q1 uses the HP806P550S (SOP-8 package), with a maximum VDS of -60V, a maximum ID of -5A (continuous), and a typical RDS(on) of approximately 50mΩ. Pin assignment: Pins 1 / 2 / 3 are the source (S) (S1 / S2 / S3 in parallel), pin 4 is the gate (G), and pins 5 / 6 / 7 / 8 are the drain (D) (D1 / D2 / D3 / D4 in parallel). This multi-source and multi-drain parallel design reduces on-resistance and increases current carrying capacity, meeting the requirement of a maximum output current of 5A.

[0050] The source of Q1 (pins 1 / 2 / 3) is connected to the second power supply voltage P12V (12V power supply). The power supply trace has a current carrying capacity of 5A to ensure that there is no risk of overheating or burning during long-term operation.

[0051] The gate of Q1 (pin 4) is connected to the right end of R4 (denoted as node B).

[0052] The drain of Q1 (pins 5 / 6 / 7 / 8) is the circuit output terminal P12V_OUT, which is used to provide 12V power to the back-end spaceborne equipment. In addition, when Q1 is turned on and P12V_OUT outputs 12V, R7 can inject a stable pull-up current into the gate of Q2, offsetting the pull-down effect of R9, and ensuring that the gate of Q2 maintains a high potential.

[0053] For the gate drive resistor network of Q1, where: The fourth pull-up resistor R3 (20kΩ, 0603 package, 1% accuracy): one end is connected to P12V and the other end is connected to node A. By default, node A is pulled up to 12V, providing a pull-up path for the gate of Q1.

[0054] Current-limiting resistor R4 (33Ω, 0603 package, 1% accuracy): The left end is connected to node A and the right end is connected to node B (Q1 gate), providing a drive path for Q1 gate, limiting the gate charging and discharging current, and protecting Q1 gate.

[0055] The second pull-down resistor R6 (20kΩ, 0603 package, 1% accuracy): the upper end is connected to node A, and the lower end is connected to the drain of Q2. Its core function is to provide a discharge path to ground for node A when Q2 is turned on, and work with R4 to pull down the gate potential of Q1 to realize the turn-on control of Q1; at the same time, it forms positive feedback to enhance the stability of the Q1 turn-on state.

[0056] Gate filter capacitors CP3 (2.2μF, 0805 package) and CP5 (10μF, C1210 package, 100V withstand voltage, model GRM32EC72A106ME05L): are connected in parallel between the gate of Q1 and P12V to filter out interference and high-frequency noise on the gate and prevent Q1 from malfunctioning due to gate interference.

[0057] Output filter capacitors CP1 (2.2μF, 0805 package) and CP2 (10μF, C1210 package, 100V withstand voltage, model GRM32EC72A106ME05L): connected in parallel between P12V_OUT and GND, to filter out output voltage ripple and noise, stabilize the output voltage, provide a stable power supply environment for downstream spaceborne equipment, and meet the high power supply stability requirements of spaceborne equipment.

[0058] The output terminal P12V_OUT is also connected to an LED indicator circuit: the anode of LED1 (green LED) is connected to P12V_OUT through a current-limiting resistor R1 (2.4kΩ, 0603 package, 1% accuracy), and the cathode of LED1 is grounded. A resistor R2 (model RX24-50W5RJ, power resistor) is also connected in parallel to ground at the node of R1 near the P12V_OUT terminal. LED1 is used to visually indicate the power supply status of the downstream device: LED1 lit indicates that P12V_OUT has output, and LED1 off indicates that P12V_OUT has no output.

[0059] Detailed analysis of the circuit's operation: (1) Initial power-on state (safe shutdown): After the P5V and P12V power supplies are established: the / OE terminals of U1 and U2 are pulled up to 5V high level through pull-up resistors (R5, R10), and both tri-state buffer gates output high impedance state, without any drive to the gate of Q2.

[0060] The gate of Q2 is pulled to GND (0V) through R9 (100kΩ), keeping capacitors CP9 and CP10 uncharged. Q2's VGS = 0V, which is much lower than Vth (about 2V), so Q2 is reliably cut off with its drain open.

[0061] Node A (Right end of R3, Left end of R4, Upper end of R6) is pulled up to 12V through R3. Node B (gate of Q1) follows the potential of node A through R4. The gate of Q1 is approximately 12V, VGS = 12V - 12V = 0V, and Q1 is reliably turned off.

[0062] P12V_OUT has no output, LED1 is off, and the system is in a safe shutdown state by default.

[0063] (2) On control (press SW1): Press SW1, SW1 is turned on, the / OE terminal of U1 is pulled to GND (0V), and U1 is turned on. U1 transmits the 5V high level of input terminal A to output terminal Y.

[0064] The gate potential of Q2 rises rapidly from 0V to approximately 5V (transferred via U1, where VOH is close to VCC=5V). The gate voltage is clamped below approximately 5.1V by D1, protecting Q2. Holding capacitors CP9+CP10 (4.4μF) are charged.

[0065] Q2's VGS≈5V, far exceeding Vth (approximately 2V), causes Q2 to conduct strongly. Q2's drain (D) is connected to GND through Q2's RDS(on) (approximately a few Ω), pulling Q2's drain potential down to near 0V.

[0066] After Q2 is turned on, node A (12V pulled up via R3) is connected to the drain of Q2 (≈0V) through R6, and the potential of node A is pulled up to ≈0V; node B (Q1 gate) follows the potential of node A through R4, Q1 gate ≈0V, VGS=0V-12V=-12V, which is far beyond the Q1 turn-on threshold (≈-2V~-4V), and Q1 is strongly turned on.

[0067] P12V_OUT output ≈ 12V (only the RDS(on) voltage drop of Q1), LED1 lights up, and the back-end device is powered on.

[0068] At this time, the current path is: P12V→R3→Node A→R6→Q2 drain→Q2 source→GND; at the same time, P12V→R3→Node A→R4→Q1 gate→Node A forms a loop, and the gate of Q1 is reliably pulled low.

[0069] After P12V_OUT outputs 12V, R7 injects pull-up current into the gate of Q2 to help maintain a high gate potential and enhance conduction stability. This positive feedback structure ensures that once Q2 is turned on, the output terminal continues to conduct through R7, achieving permanent self-locking on a single pulse without the need for continuous capacitor discharge or subsequent microcontroller intervention.

[0070] (3) Self-holding after the pulse disappears (releasing SW1): When SW1 is released, the / OE terminal of U1 is pulled up to 5V through R5, and U1 returns to a high-impedance output state. The output terminal Y of U1 becomes high-impedance, no longer providing drive current to the gate of Q2, nor drawing current from the gate of Q2.

[0071] At this point, the charge maintenance status of the Q2 gate is as follows: the holding capacitor CP9+CP10 (4.4μF) is charged to approximately 5V; the discharge path is: discharge to GND only through R9 (100kΩ); simultaneously, R7 injects pull-up current from P12V_OUT (12V) to maintain the Q2 gate at a high level. The holding capacitor is responsible for maintaining the Q2 gate potential momentarily after the pulse ends, while R7 provides positive feedback latching, allowing the Q2 gate potential to be maintained at a high level for an extended period without any holding time limit. It can be latched on indefinitely, achieving the effect of holding forever with just one press.

[0072] (4) Shutdown control (press SW2): With Q1 on, press SW2. SW2 turns on, pulling the / OE terminal of U2 to GND, and U2 turns on. U2 transmits the 0V low level from input A to output Y.

[0073] The output terminal Y of U2 outputs a low level (≈0V) and connects to the gate of Q2. The 5V charge on capacitor CP9+CP10 is rapidly discharged to GND through the low-impedance output path of U2. The low-level output VOL of U2 is approximately 0.1V, which discharges the 4.4μF capacitor through the output impedance of U2 (approximately tens of Ω). The discharge time constant is approximately 50Ω × 4.4μF = 220μs, meaning that the gate voltage can drop to near 0V within approximately 1ms.

[0074] When VGS of Q2 drops to 0V, Q2 is cut off. Q2's drain is open, and it no longer discharges current.

[0075] Node A is no longer discharged through R6, but is pulled up to 12V by R3. The gate of Q1 rises to 12V through R4 following the potential of node A. VGS≈0V, Q1 is turned off.

[0076] When P12V_OUT is de-energized, LED1 turns off, and the backend device is powered down.

[0077] (5) Self-holding in the off state (releasing SW2): Releasing SW2 restores U2 to its high-impedance state. The gate of Q2 is continuously pulled to GND (0V) through R9 (100kΩ), keeping the capacitor uncharged, and R7 also has no charge input. Q2 remains continuously off, and Q1 remains continuously off. This off-state is maintained indefinitely.

[0078] (6) Fail-safe feature verification: Scenario A: Microcontroller Crash: Assume that the microcontroller's GPIO is used to replace SW1 / SW2 to send pulses. After the microcontroller crashes, the GPIO becomes a high-impedance input. The / OE terminals of U1 and U2 are both kept at a high level of 5V through pull-up resistors, and both tri-state buffer gates output high impedance. If the circuit was in the on state before the crash, the holding capacitor keeps Q2 on, and Q1 continues to output 12V (within the holding time); if the circuit was in the off state before the crash, R9 keeps Q2 off, and Q1 remains off. The circuit is unaffected by the microcontroller crash, ensuring the power supply safety of the onboard equipment.

[0079] Scenario B, Microcontroller Reset: GPIO changes momentarily but recovers quickly. Because the / OE pin has pull-up resistors and filter capacitors (C2, C4), the brief glitches in the GPIO pin during reset can be filtered out, preventing malfunctions and ensuring circuit stability and reliability.

[0080] The above solution requires only two short pulses (once for each switch) to keep the MOSFET in a continuously conducting / cut-off state, eliminating the need for continuous output from the microcontroller. This completely solves the problem of MOSFET malfunction caused by uncertain GPIO states after a microcontroller crash or reset. Simultaneously, it achieves electrical isolation; the microcontroller only sends pulses and does not need to be continuously connected to the power circuit, significantly improving load handling capability.

[0081] refer to Figure 2 , Figure 3 , Figure 4 Furthermore, the embodiments of this application also perform simulation verification on the circuit.

[0082] Simulation conditions include: Input: A simulated pulse signal from a tactile switch.

[0083] Output: When SW1 is pressed, the circuit is successfully powered on; when SW2 is pressed, the circuit is successfully powered off.

[0084] Simulation process: Initial power-on state: such as Figure 2 As shown, in the initial power-on state, Q2 is off, Q1 is off, there is no voltage at C1, and LED1 is not lit.

[0085] Pulse-triggered (conduction) state: such as Figure 3 As shown, after S1 is triggered (pressed and released), Q2 and Q1 are turned on, the voltage at C1 is 12V, and LED1 is lit and remains lit.

[0086] Pulse off (cut-off) state: such as Figure 4 As shown, after S2 is triggered (pressed and released), Q2 is turned off, Q1 is turned off, the voltage at C1 is 0V, and LED1 is off and remains off.

[0087] Based on the above circuit structure, this application also provides a pulse control and holding method for a spaceborne computer, referencing... Figure 5 As shown, the method includes the following steps: S1. Power-on initialization steps: After power-on, the output enable terminals of the first and second tri-state buffer gates are pulled to high level through the first and second pull-up resistors, and both output high impedance state; the gate of the N-channel MOSFET is pulled to low level through the first pull-down resistor, and the N-channel MOSFET is cut off; the gate of the P-channel MOSFET is pulled up to close to the second power supply voltage through the fourth pull-up resistor, and the P-channel MOSFET is cut off. There is no voltage output at the circuit output terminal, and the back-end device is in the default power-off state.

[0088] S2. Turn-on control step: A short low-level pulse is applied to the output enable terminal of the first tri-state buffer gate, turning on the first tri-state buffer gate. This transmits the first power supply voltage to the gate of the N-channel MOSFET and charges the holding capacitor, turning on the N-channel MOSFET. The drain of the N-channel MOSFET is pulled low, and the gate of the P-channel MOSFET is pulled low through the current-limiting resistor and the second pull-down resistor, turning on the P-channel MOSFET. The circuit outputs the second power supply voltage. After the pulse disappears, the first tri-state buffer gate returns to a high-impedance state. The holding capacitor and the third pull-up resistor together maintain the gate charge of the N-channel MOSFET, keeping both the N-channel and P-channel MOSFETs on, thus achieving self-holding of the on-state. In this step, the pulse width of the short low-level pulse is greater than the time required for the holding capacitor to charge to the gate turn-on threshold of the N-channel MOSFET through the output impedance of the first tri-state buffer gate.

[0089] S3. Shutdown control steps: Apply a low-level short pulse to the output enable terminal of the second tri-state buffer gate. The second tri-state buffer gate is turned on, transmitting the ground potential to the gate of the N-channel MOSFET. The charge on the holding capacitor is discharged, the N-channel MOSFET is turned off, and the gate of the P-channel MOSFET is pulled up to near the second power supply voltage. The P-channel MOSFET is turned off, and the circuit output is de-energized. After the pulse disappears, the second tri-state buffer gate returns to the high-impedance state. The first pull-down resistor maintains the gate of the N-channel MOSFET at a low level. The N-channel MOSFET and the P-channel MOSFET remain turned off, achieving self-holding of the shutdown state. Example 2

[0090] Based on the pulse control and holding circuit structure and method for spaceborne computers provided in Embodiment 1, this Embodiment 2 provides some feasible alternative solutions.

[0091] For example, changing P12V to P28V (28V satellite bus voltage) or P42V (42V satellite bus voltage) does not change the corresponding circuit structure, but the model and value of each component can be adjusted accordingly.

[0092] For example, in the microcontroller automatic control mode: replace the tactile switches SW1 and SW2 with the microcontroller's GPIO ports. The microcontroller's first GPIO is connected to the / OE pin of U1, and the second GPIO is connected to the / OE pin of U2.

[0093] After the microcontroller is working normally, it will perform the following based on remote control commands from the host computer or its own judgment logic: When the backend device needs to be powered on: the first GPIO outputs a short low-level pulse (pulse width recommended 10ms~100ms), triggering Q1 to conduct and P12V_OUT to output; after the pulse ends, the GPIO returns to a high level or switches to high-impedance input mode.

[0094] When the backend device needs to be powered down: the second GPIO outputs a short low-level pulse, triggering Q1 to turn off and P12V_OUT to turn off.

[0095] The microcontroller only needs to send a single low-level short pulse to trigger the circuit into a permanent self-locking state. No subsequent control signals are required, and sleep, reset, and power-off do not affect the output state. For example, even if the microcontroller enters a low-power sleep mode and the GPIO no longer outputs any signals, the circuit can still maintain its current state by relying on the positive feedback of the holding capacitor and the third pull-up resistor R7, unaffected by the microcontroller's state. Example 3

[0096] In the radiation environment of space, single-event effects can cause the charge on the holding capacitor to be suddenly released (single-event discharge) or abnormal charge to be injected into the gate of a MOSFET (single-event flip), resulting in abrupt changes in the self-held state and unexpected power-on or power-off of the back-end equipment. Simultaneously, the ground-based telemetry and control system needs to know the current power supply status of the back-end equipment in real time for telemetry monitoring, but the basic scheme in Example 1 lacks a status readback mechanism. Therefore, Example 3, based on Example 1, further incorporates a status readback unit to address the lack of a status readback mechanism and sets up a triple redundancy module to address the problem of unexpected power-on or power-off of the back-end equipment.

[0097] Specifically, for the status readback unit, two voltage divider resistors are connected in series between P12V_OUT and GND: the first voltage divider resistor Rd1 (30kΩ) and the second voltage divider resistor Rd2 (10kΩ).

[0098] Voltage divider node voltage = P12V_OUT × Rd2 / (Rd1 + Rd2). When P12V_OUT = 12V, voltage divider node voltage = 12V × 10 / (30 + 10) = 3V; when P12V_OUT = 0V, voltage divider node voltage = 0V.

[0099] The comparator is an LM393 (or an aerospace-grade equivalent). The non-inverting input (+) is connected to a voltage divider node, and the inverting input (-) is connected to a 1.5V reference voltage (provided by a precision resistor divider network or a reference voltage source). The comparator output is connected to 3.3V / 5V via pull-up resistors and then connected to the microcontroller's ADC or GPIO readback port.

[0100] When P12V_OUT=12V, the voltage divider node 3V>1.5V reference, and the comparator outputs a high level (indicating "the device is powered on"). When P12V_OUT=0V, the voltage divider node 0V<1.5V reference, and the comparator outputs a low level (indicating "the device is powered off").

[0101] The microcontroller can read the comparator output to confirm the current power supply status of the backend equipment and report it to the ground station through the telemetry channel.

[0102] For triple redundancy modules, the state-keeping unit in Example 1 can be expanded into three independent groups.

[0103] Each of the three sets of state-maintaining units A, B, and C contains: N-channel MOSFETs Q2a / Q2b / Q2c (all L2N7002LT1G); Clamping diodes D1a / D1b / D1c (all MM5Z5V1T1G, cathode connected to gate, anode grounded). Pull-up resistors R7a / R7b / R7c (all 150kΩ); Pull-down resistors R9a / R9b / R9c (all 100kΩ); Maintain the capacitor bank CPa / CPb / CPc (all 2×2.2μF=4.4μF); The components are configured the same as in Example 1, and will not be described again here.

[0104] The output of U1 is connected to the gates of Q2a / Q2b / Q2c via three independent isolation resistors (Riso_a / Riso_b / Riso_c, each 1kΩ). The output of U2 is also connected via three isolation resistors. These isolation resistors ensure that a fault in one group will not affect other groups through the gate connection.

[0105] The 3-out-of-2 voting circuit: The drains of Q2a / Q2b / Q2c are connected to the voting node via Schottky diodes (Da / Db / Dc, anode connected to drain, cathode connected to the common voting node N_VOTE). The voting node N_VOTE is pulled up to the first power supply voltage through the voting pull-up resistor R_VOTE. Simultaneously, the voting node N_VOTE is also connected to node A through the second pull-down resistor R6.

[0106] How voting works: When at least two sets of N-channel MOSFETs are turned on, the voting node N_VOTE is pulled low to a low level. This low level is transmitted to node A through the second pull-down resistor R6, causing the potential of node A to be pulled low, which in turn turns on the P-channel MOSFET and supplies power to the output terminal. When fewer than two sets of N-channel MOSFETs are turned on, the voting pull-up resistor keeps N_VOTE at a high level, node A is pulled up to the second power supply voltage by the fourth pull-up resistor R3, the P-channel MOSFET is turned off, and the output is de-energized.

[0107] Furthermore, the three sub-units are arranged in a triangular layout on the PCB with an adjacent spacing of ≥20mm, which is much larger than the typical influence radius of a single event (<10μm), ensuring that a single heavy ion event will not simultaneously flip more than two sets of the hold-up state.

[0108] Furthermore, the microcontroller sends a refresh pulse every 30 seconds (to U1 in the on state and to U2 in the off state), simultaneously refreshing the three sets of holding capacitors. Even if one set of capacitors discharges or Q2 flips due to a radiation event, the other two sets remain in the correct state, with a two-out-of-three voting method ensuring correct output. When the next refresh pulse arrives, the faulty set will be reset to the correct state, achieving automatic error correction.

[0109] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A pulse control and holding circuit structure for a spaceborne computer, characterized in that, It includes a turn-on trigger unit, a turn-off trigger unit, a state holding unit, and a power switch unit; The conduction triggering unit includes a first tri-state buffer gate. The input terminal of the first tri-state buffer gate is connected to a first power supply voltage. The output enable terminal of the first tri-state buffer gate is connected to the first power supply voltage through a first pull-up resistor and is used to receive a conduction low-level pulse signal. The shutdown trigger unit includes a second tri-state buffer gate. The input terminal of the second tri-state buffer gate is grounded, and the output enable terminal of the second tri-state buffer gate is connected to the first power supply voltage through a second pull-up resistor and is used to receive a shutdown low-level pulse signal. The state holding unit includes an N-channel MOSFET and a holding capacitor; the output terminals of the first tri-state buffer gate and the second tri-state buffer gate are both connected to the gate of the N-channel MOSFET; the holding capacitor is connected between the gate of the N-channel MOSFET and ground; the gate of the N-channel MOSFET is also grounded through a first pull-down resistor and connected to the circuit output terminal through a third pull-up resistor; the source of the N-channel MOSFET is grounded. The power switching unit includes a P-channel MOSFET, the source of which is connected to a second power supply voltage, and the gate of which is connected to a first node via a current-limiting resistor; the first node is connected to the second power supply voltage via a fourth pull-up resistor, and is connected to the drain of the N-channel MOSFET via a second pull-down resistor; the drain of the P-channel MOSFET is the circuit output terminal. The output enable terminals of both the first and second tri-state buffer gates are active low. When the output enable terminal receives a low-level pulse signal, the tri-state buffer gate turns on and outputs; when the output enable terminal is high, the tri-state buffer gate outputs a high-impedance state. The state holding unit is provided in three independent groups; the gates of the N-channel MOS transistors of the three groups of state holding units are respectively connected to the output terminals of the first tri-state buffer gate and the second tri-state buffer gate through isolation resistors; the drains of the N-channel MOS transistors of the three groups of state holding units are connected to the gate of the P-channel MOS transistor through a three-out-of-two voting circuit; the three groups of state holding units are spatially distributed on the PCB, and the distance between two adjacent groups of state holding units is greater than the typical influence radius of the single-event effect.

2. The pulse control and holding circuit structure for a spaceborne computer according to claim 1, characterized in that, The state holding unit also includes a clamping diode, which is a Zener diode with its cathode connected to the gate of the N-channel MOS transistor and its anode grounded, used to clamp the gate voltage of the N-channel MOS transistor below the regulated value.

3. The pulse control and holding circuit structure for a spaceborne computer according to claim 1, characterized in that, The discharge time constant formed by the product of the holding capacitor's capacitance and the first pull-down resistor's resistance is greater than the required minimum holding time.

4. The pulse control and holding circuit structure for a spaceborne computer according to claim 1, characterized in that, The resistance value of the current-limiting resistor is less than the resistance value of the fourth pull-up resistor; when the N-channel MOSFET is off, the gate of the P-channel MOSFET is pulled up to near the second power supply voltage by the fourth pull-up resistor, and the P-channel MOSFET is off; when the N-channel MOSFET is on, the gate of the P-channel MOSFET is pulled down to near ground potential through the current-limiting resistor and the on-state N-channel MOSFET, and the P-channel MOSFET is on.

5. The pulse control and holding circuit structure for a spaceborne computer according to claim 1, characterized in that, It also includes a status readback unit, which includes a voltage divider resistor network connected in series between the circuit output terminal and ground, and a comparator; the non-inverting input terminal of the comparator is connected to the voltage divider node, the inverting input terminal is connected to the reference voltage, and the output terminal is connected to the readback port of the microcontroller.

6. A pulse control and hold method for a spaceborne computer, applied to the pulse control and hold circuit structure for a spaceborne computer as described in any one of claims 1-5, characterized in that, include: Power-on initialization steps: After power-on, the output enable terminals of the first and second tri-state buffer gates are pulled to high level through the first and second pull-up resistors, both outputting a high-impedance state; the gate of the N-channel MOSFET is pulled to low level through the first pull-down resistor, and the N-channel MOSFET is turned off; the gate of the P-channel MOSFET is pulled up to near the second power supply voltage through the fourth pull-up resistor, and the P-channel MOSFET is turned off. There is no voltage output at the circuit output terminal, and the back-end device is in the default power-off state. Conduction control steps: A short low-level pulse is applied to the output enable terminal of the first tri-state buffer gate, turning on the first tri-state buffer gate, transmitting the first power supply voltage to the gate of the N-channel MOSFET and charging the holding capacitor, turning on the N-channel MOSFET, pulling the drain of the N-channel MOSFET low, and pulling the gate of the P-channel MOSFET low through the current-limiting resistor and the second pull-down resistor, turning on the P-channel MOSFET, and outputting the second power supply voltage at the circuit output terminal; after the pulse disappears, the first tri-state buffer gate returns to the high-impedance state, and the holding capacitor and the third pull-up resistor together maintain the gate charge of the N-channel MOSFET, keeping both the N-channel MOSFET and the P-channel MOSFET on, achieving self-holding of the conduction state; Shutdown control steps: A short low-level pulse is applied to the output enable terminal of the second tri-state buffer gate, turning on the second tri-state buffer gate and transferring the ground potential to the gate of the N-channel MOSFET. The charge on the holding capacitor is discharged, the N-channel MOSFET is turned off, and the gate of the P-channel MOSFET is pulled up to near the second power supply voltage, turning off the P-channel MOSFET and de-energizing the circuit output. After the pulse disappears, the second tri-state buffer gate returns to the high-impedance state, and the first pull-down resistor maintains the gate of the N-channel MOSFET at a low level. The N-channel MOSFET and the P-channel MOSFET remain off, achieving self-holding of the shutdown state.

7. The pulse control and holding method for a spaceborne computer according to claim 6, characterized in that, In the conduction control step, the pulse width of the low-level short pulse is greater than the time required for the holding capacitor to charge to the gate turn-on threshold of the N-channel MOS transistor through the output impedance of the first tri-state buffer gate.

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