A reference drive circuit suitable for high-speed pipelined analog-to-digital converters

Abstract

This invention provides a reference drive circuit suitable for high-speed pipelined analog-to-digital converters (ADCs), including an error amplification and feedback network, a driver stage circuit, and a common-mode feedback circuit. The error amplification and feedback network combines a high-gain error amplifier with a resistive feedback network to achieve closed-loop control of the output voltage. By adjusting the configurable resistor combination in the feedback network, the output voltage value can be flexibly set and adjusted. The driver stage circuit uses a large-size current mirror output stage, significantly reducing the static power consumption of the reference driver amplifier and effectively improving the driving capability and transient response performance. The common-mode feedback circuit is used to accurately stabilize the common-mode level of the output differential reference voltage, ensuring its stability and consistency under changes in process, voltage, and temperature, thereby improving the linearity and dynamic performance of the entire ADC system. This invention achieves an optimized balance between power consumption and driving capability while ensuring high-speed reference driving.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a reference drive circuit suitable for high-speed pipelined analog-to-digital converters. Background Technology

[0002] High-speed pipelined analog-to-digital converters (ADCs) are core components in wireless communication, high-speed data acquisition, and radar systems, and their performance directly determines the accuracy and speed of the entire signal chain. During sampling, quantization, and residual amplification in each stage of the pipelined ADC, a highly stable and transiently responsive reference voltage is required to ensure the linearity and dynamic range of the signal conversion. Therefore, the performance of the reference driver circuit, which provides the reference voltage to the pipelined ADC, has become one of the key bottlenecks restricting the overall performance of the ADC system. Traditional reference driver circuits typically use operational amplifiers based on Class-A structures, with their output stages using a constant bias current source as a load. While this structure provides a certain level of accuracy, it has inherent drawbacks when driving high-speed ADCs. At the moment of sampling, the internal switched-capacitor network generates a huge transient current demand. The maximum output current of a traditional Class-A output stage is limited by its static bias current. When the transient current demand exceeds this static current, the output stage enters the saturation or cutoff region, resulting in insufficient reference voltage settling. This not only introduces nonlinear errors but also prolongs the settling time, directly limiting the effective conversion rate and spurious-free dynamic range of the ADC. To address the aforementioned insufficient driving capability, an intuitive approach is to increase the static bias current of the Class-A output stage. However, this leads to a linear increase in the static power consumption of the reference driver circuit, which contradicts the current design requirements for low power consumption in integrated circuits under deep submicron and nanometer processes. Especially in multi-channel, highly integrated systems, where multiple ADCs share or are equipped with their own reference drivers, the total power consumption becomes unacceptable. Summary of the Invention

[0003] To address the aforementioned issues, this invention proposes a reference drive circuit suitable for high-speed pipelined analog-to-digital converters. Through error amplification and feedback networks, output drive stages, and common-mode feedback circuits, a high-precision, low-power, and high-driving-capability reference drive circuit is achieved.

[0004] A reference drive circuit suitable for high-speed pipelined analog-to-digital converters is disclosed. The reference drive circuit includes an error amplification and feedback network, an output drive stage, and a common-mode feedback circuit. The error amplification and feedback network includes an open-loop amplifier, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. One end of the first resistor R1 is connected to the input port Vin, and the other end is connected to the negative input port of the open-loop amplifier and also to one end of the second resistor R2. The other end of the second resistor R2 is connected to the power supply ground. One end of the third resistor R3 is connected to the input port Vin, and the other end is connected to the positive input port of the open-loop amplifier and also to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the low reference voltage port VREFL of the output drive stage.

[0005] Further, the output drive stage includes a first N-type transistor MN1, a second N-type transistor MN2, a first P-type transistor MP1, a second P-type transistor MP2, a fifth resistor R5, and a sixth resistor R6. The gates of the first N-type transistor MN1 and the second N-type transistor MN2 are connected to the output port of the open-loop amplifier in the error amplifier and feedback network, and their sources are connected to the power supply ground. The drain of the first N-type transistor MN1 is connected to the gate and drain of the first P-type transistor MP1 and the gate of the second P-type transistor MP2. The drain of the second N-type transistor MN2 is connected to the output low reference voltage port VREFL and one end of the sixth resistor R6. The sources of the first P-type transistor MP1 and the second P-type transistor MP2 are connected to the power supply voltage. The drain of the second P-type transistor MP2 is connected to one end of the fifth resistor R5 and the output high reference voltage VREFH. The other end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the positive input port of the open-loop amplifier in the common-mode feedback circuit.

[0006] Furthermore, the common-mode feedback circuit includes an open-loop amplifier and a common-mode regulating transistor, a third N-type transistor MN3. The positive input port of the open-loop amplifier is connected to the common-mode output VOCM of the drive output, the negative input port of the open-loop amplifier is connected to the input port VCM, the output port of the open-loop amplifier is connected to the gate of the third N-type transistor MN3, the source of the third N-type transistor MN3 is connected to the power supply ground, and the drain is connected to the output low reference voltage port VREFL.

[0007] Furthermore, VCM is an external input voltage used to adjust the common-mode of the output reference voltage.

[0008] Furthermore, the relationship between the output voltage and the input reference voltage in the error amplification and feedback network is as follows:

[0009]

[0010] Where R1, R2, R3, and R4 are the resistance values ​​of the four resistors in the error amplification and feedback network. This is the input reference voltage.

[0011] This invention proposes a reference drive circuit suitable for high-speed pipelined analog-to-digital converters (ADCs), comprising an error amplifier and feedback network, an output drive stage, and a common-mode feedback circuit. The error amplifier and feedback network combines a high-gain error amplifier with a resistive feedback network. The feedback network consists of four high-precision, low-temperature-coefficient passive polysilicon resistors configured in a specific ratio and placed in the closed-loop negative feedback loop of the error amplifier, achieving closed-loop control of the output voltage. By adjusting the configurable resistor combination in the feedback network, the output voltage value can be flexibly set and adjusted to adapt to different reference voltage requirements. The drive stage circuit uses a large-size current mirror output stage, significantly reducing the static power consumption of the reference drive amplifier and overcoming the output current saturation problem caused by using a current source as a load in traditional designs, effectively improving drive capability and transient response performance. The common-mode feedback circuit is used to accurately stabilize the common-mode level of the output differential reference voltage, ensuring its stability and consistency under process, voltage, and temperature variations, thereby improving the linearity and dynamic performance of the entire ADC system. This invention achieves an optimized balance between power consumption and drive capability while ensuring high-speed reference drive. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a reference drive circuit for a high-speed pipeline analog-to-digital converter provided by an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] A reference driver circuit suitable for high-speed pipelined analog-to-digital converters, the reference driver circuit including an error amplification and feedback network, an output driver stage, and a common-mode feedback circuit, such as... Figure 1As shown, the error amplification and feedback network includes an open-loop amplifier, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. One end of the first resistor R1 is connected to the input port Vin, and the other end is connected to the negative input port of the open-loop amplifier, and also to one end of the second resistor R2. The other end of the second resistor R2 is connected to the power supply ground. One end of the third resistor R3 is connected to the input port Vin, and the other end is connected to the positive input port of the open-loop amplifier, and also to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the low reference voltage port VREFL of the output driver stage. This circuit can achieve the purpose of adjusting the output voltage through different resistor combinations.

[0016] The output drive stage includes a first N-type transistor MN1, a second N-type transistor MN2, a first P-type transistor MP1, a second P-type transistor MP2, a fifth resistor R5, and a sixth resistor R6. The gates of the first N-type transistor MN1 and the second N-type transistor MN2 are connected to the output port of the open-loop amplifier in the error amplifier and feedback network, and their sources are connected to the power supply ground. The drain of the first N-type transistor MN1 is connected to the gate and drain of the first P-type transistor MP1 and the gate of the second P-type transistor MP2. The drain of the second N-type transistor MN2 is connected to the output low reference voltage port VREFL and one end of the sixth resistor R6. The sources of the first P-type transistor MP1 and the second P-type transistor MP2 are connected to the power supply voltage. The drain of the second P-type transistor MP2 is connected to one end of the fifth resistor R5 and the output high reference voltage VREFH. The other end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the positive input port of the open-loop amplifier in the common-mode feedback circuit.

[0017] The common-mode feedback circuit includes an open-loop amplifier and a common-mode adjustment transistor, a third N-type transistor MN3. The positive input port of the open-loop amplifier is connected to the common-mode output VOCM of the drive output, and the negative input port of the open-loop amplifier is connected to the input port VCM, where VCM is an external input voltage used to adjust the common-mode of the output reference voltage. The output port of the open-loop amplifier is connected to the gate of the third N-type transistor MN3, the source of the third N-type transistor MN3 is connected to the power supply ground, and the drain is connected to the output low reference voltage port VREFL.

[0018] The error amplification and feedback network, the output driver stage, and the common-mode feedback circuit together constitute a high-precision, low-power, and high-driving-capability reference voltage buffer.

[0019] The error amplifier and feedback network are the core components of the circuit for achieving precise voltage setting. This module adopts a structure combining a high-gain error amplifier and a resistive feedback network. The feedback network consists of four high-precision, low-temperature-coefficient passive polysilicon resistors configured in a specific ratio and placed in the closed-loop negative feedback loop of the error amplifier. Based on the fundamental principles of virtual short and virtual open circuits satisfied by the operational amplifier operating in a deep negative feedback state, the relationship between the output voltage and the input reference voltage and the resistance ratio can be accurately established.

[0020]

[0021] Where R1, R2, R3, and R4 are the resistance values ​​of the four resistors in the feedback network. For the high-precision bandgap reference voltage input, this structural design brings two key advantages. First, the accuracy and temperature stability of the output voltage mainly depend on the proportional matching degree of the high-precision resistors, and are less related to the non-ideal open-loop gain of the amplifier itself, thus achieving excellent linearity and process robustness. Second, by adjusting the resistance ratio of the four resistors, the specific reference voltage level required by the ADC can be flexibly generated without changing the core amplifier circuit architecture, which greatly enhances the design reusability and configurability of the circuit in different application scenarios and process nodes.

[0022] The output driver stage employs a current source structure as its core driving unit. The width-to-length ratio (W / L) of the output power transistor is designed to be significantly larger than that of its input stage mirror transistor, creating a substantial proportional amplification relationship. This design, while maintaining a low quiescent current, significantly enhances the transconductance and current drive capability of the output stage. When the sampling switch inside the high-speed ADC causes a drastic transient change in the reference voltage load, the output node generates a rapid current demand. At this time, based on the current transfer characteristics of the mirror current source, the large-size power transistor at the output can quickly respond to the current change, providing or absorbing a dynamic drive current several times the quiescent current in a very short time. This rapidly compensates for voltage disturbances caused by load changes. This mechanism ensures that even under the worst load transient conditions, the output voltage can quickly recover and stabilize within the setup time window required by the ADC, effectively suppressing voltage slump and ringing phenomena caused by current saturation in traditional structures.

[0023] In addition to the core error amplification and drive stage, to ensure the long-term stability and accuracy of the differential reference voltage pair, the circuit of this invention also integrates an independent high-precision common-mode feedback module. Since the common-mode level of the output differential reference voltage cannot stabilize under open-loop conditions and is highly susceptible to process deviations, temperature drift, and power supply noise, it must be dynamically adjusted and locked through closed-loop feedback. First, a pair of highly matched resistors is used to precisely divide and sample the positive and negative differential reference voltages, directly extracting the real-time output common-mode voltage VOCM from its midpoint. This voltage is then fed into the positive input of a high-gain common-mode error amplifier and compared with a highly stable target common-mode reference voltage VCM provided internally or externally. The common-mode error amplifier amplifies the difference between the two, and this signal is fed back to the gate of the common-mode regulating transistor, forming a global negative feedback loop. By dynamically adjusting the conduction state of this transistor, the total current or load balancing of the output stage can be effectively controlled, thereby precisely locking the actual output common-mode voltage to the preset target value. This design ensures that the common-mode point of the output differential reference voltage remains highly stable throughout the entire operating temperature, power supply voltage range, and process angle variations. It effectively avoids problems such as ADC comparator misjudgment, dynamic range loss, and even-order harmonic distortion deterioration caused by common-mode drift, significantly improving the reliability and signal integrity of the entire ADC system.

[0024] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A reference drive circuit suitable for high-speed pipelined analog-to-digital converters, characterized in that, The reference drive circuit includes an error amplification and feedback network, an output drive stage, and a common-mode feedback circuit. The error amplification and feedback network includes an open-loop amplifier, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. One end of the first resistor R1 is connected to the input port Vin, and the other end is connected to the negative input port of the open-loop amplifier and also to one end of the second resistor R2. The other end of the second resistor R2 is connected to the power supply ground. One end of the third resistor R3 is connected to the input port Vin, and the other end is connected to the positive input port of the open-loop amplifier and also to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the low reference voltage port VREFL of the output drive stage. The output drive stage includes a first N-type transistor MN1, a second N-type transistor MN2, a first P-type transistor MP1, a second P-type transistor MP2, a fifth resistor R5, and a sixth resistor R6. The gates of the first N-type transistor MN1 and the second N-type transistor MN2 are connected to the output port of the open-loop amplifier in the error amplifier and feedback network, and their sources are connected to the power supply ground. The drain of the first N-type transistor MN1 is connected to the gate and drain of the first P-type transistor MP1 and the gate of the second P-type transistor MP2. The drain of the second N-type transistor MN2 is connected to the output low reference voltage port VREFL and one end of the sixth resistor R6. The sources of the first P-type transistor MP1 and the second P-type transistor MP2 are connected to the power supply voltage. The drain of the second P-type transistor MP2 is connected to one end of the fifth resistor R5 and the output high reference voltage VREFH. The other end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the positive input port of the open-loop amplifier in the common-mode feedback circuit. The common-mode feedback circuit includes an open-loop amplifier and a common-mode regulating transistor, a third N-type transistor MN3. The positive input port of the open-loop amplifier is connected to the common-mode output VOCM of the drive output, the negative input port of the open-loop amplifier is connected to the input port VCM, the output port of the open-loop amplifier is connected to the gate of the third N-type transistor MN3, the source of the third N-type transistor MN3 is connected to the power supply ground, and the drain is connected to the output low reference voltage port VREFL. VCM is an external input voltage used to adjust the common-mode voltage of the output reference voltage.

2. The reference drive circuit for high-speed pipelined analog-to-digital converters according to claim 1, characterized in that, The relationship between the output voltage and the input reference voltage in the error amplification and feedback network is as follows: Where R1, R2, R3, and R4 are the resistance values ​​of the four resistors in the error amplification and feedback network. This is the input reference voltage.

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