Multiplexer insertion loss optimization circuit, method and radio frequency front end module

Abstract

The application provides a multiplexer insertion loss optimization circuit, method and radio frequency front end module, and relates to the technical field of wireless communication.The circuit comprises a multiplexer, a switching circuit, a matching circuit and an antenna end, one end of the matching circuit is connected with the antenna end, the other end is connected with the switching circuit, the matching circuit comprises a first matching circuit and a second matching circuit, or only comprises the first matching circuit;the first matching circuit comprises all components of the second matching circuit, the switching circuit is used for connecting the multiplexer and the first matching circuit to adapt to a carrier aggregation scene, or connecting the multiplexer and the second matching circuit to adapt to a non-carrier aggregation scene, or connecting the multiplexer and all components of the second matching circuit contained in the first matching circuit to adapt to the non-carrier aggregation scene.The application sets corresponding matching circuits for the carrier aggregation scene and the non-carrier aggregation scene, reduces the impedance requirement of the multiplexer, and further reduces the insertion loss.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a multiplexer insertion loss optimization circuit, method, and radio frequency front-end module. Background Technology

[0002] Carrier aggregation, a key technology in mobile communication, expands the available transmission bandwidth by simultaneously bundling multiple spectrum carriers, thereby effectively improving the peak rate for a single user and the overall network capacity. Multiplexers perform intra-band continuous / discontinuous aggregation and inter-band aggregation on multiple spectrum carriers scattered across different frequency bands, enabling flexible scheduling and integration of dispersed spectrum resources.

[0003] In carrier aggregation scenarios, to ensure that multiple transmit or receive channels do not interfere with each other when operating simultaneously, the multiplexer not only needs to maintain low signal attenuation in each passband, but also must present extremely high impedance in non-operating frequency bands, i.e., close to an open circuit state, to prevent signal energy leakage or crosstalk. To meet the impedance requirements of carrier aggregation, the multiplexer usually needs to adjust the impedance in a specific frequency band to near infinity, sacrificing insertion loss. Moreover, the high impedance requirements of the multiplexer in non-carrier aggregation scenarios also lead to increased insertion loss.

[0004] Existing multiplexer insertion loss optimization schemes typically employ higher quality factor materials and optimized multimode resonant or cross-coupled topologies, which suffer from high cost and complex structure. Summary of the Invention

[0005] This invention provides a multiplexer insertion loss optimization circuit, method, and RF front-end module to address the shortcomings of existing multiplexer insertion loss optimization schemes, which typically employ higher quality factor materials and optimized multimode resonant or cross-coupled topologies, resulting in high costs and complex structures.

[0006] This invention provides a multiplexer insertion loss optimization circuit, including a multiplexer, a switching circuit, a matching circuit, and an antenna terminal. One end of the matching circuit is connected to the antenna terminal, and the other end of the matching circuit is connected to the switching circuit. The matching circuit includes a first matching circuit for carrier aggregation scenarios and a second matching circuit for non-carrier aggregation scenarios, or the matching circuit only includes the first matching circuit for carrier aggregation scenarios; the first matching circuit includes all the components of the second matching circuit. When the matching circuit includes a first matching circuit for carrier aggregation scenarios and a second matching circuit for non-carrier aggregation scenarios, the switching circuit is used to connect the multiplexer and the first matching circuit to adapt to the carrier aggregation scenario, or to connect the multiplexer and the second matching circuit to adapt to the non-carrier aggregation scenario. When the matching circuit only includes a first matching circuit for carrier aggregation scenarios, the switching circuit is used to connect the multiplexer to the first matching circuit to adapt to carrier aggregation scenarios, or to connect the multiplexer to all components of the second matching circuit included in the first matching circuit to adapt to non-carrier aggregation scenarios.

[0007] As one embodiment, the first matching circuit is disposed on the first branch formed by the antenna end and the switching circuit. The first matching circuit includes a first inductor, a first capacitor and a second inductor. One end of the first inductor is electrically connected to the first capacitor and the other end is grounded. One end of the second inductor is electrically connected to the other end of the first capacitor and the other end is grounded. The second matching circuit includes a third inductor. One end of the third inductor is connected to the second branch formed by the antenna end and the switching circuit and the other end of the third inductor is grounded.

[0008] As one embodiment, the first matching circuit is disposed on the first branch formed by the antenna end and the switching circuit. The first matching circuit includes a second capacitor, a third capacitor and a fourth inductor. One end of the fourth inductor is connected to the second capacitor and the third capacitor respectively, and the other end is grounded. The second matching circuit includes a third inductor. One end of the third inductor is connected to the second branch formed by the antenna end and the switching circuit, and the other end of the third inductor is grounded.

[0009] As an example, when the matching circuit includes a first matching circuit for carrier aggregation scenarios and a second matching circuit for non-carrier aggregation scenarios, the switching circuit includes a first switch, which is connected to the multiplexer, the first matching circuit and the second matching circuit respectively.

[0010] As one embodiment, the first switch includes a single-pole double-throw switch or a double-pole double-throw switch.

[0011] As an example, when the matching circuit only includes a first matching circuit for carrier aggregation scenarios, the switching circuit includes a second switch. One end of the second switch is electrically connected to the components of the second matching circuit included in the first matching circuit, and the other end is connected to the output terminal of the first matching circuit. In a carrier aggregation scenario, the second switch is open, and the multiplexer is connected to the first matching circuit. In a non-carrier aggregation scenario, the second switch is closed, and the multiplexer is connected to the components of the second matching circuit included in the first matching circuit.

[0012] As an example, when the matching circuit only includes a first matching circuit for carrier aggregation scenarios, the switching circuit includes a third switch and a fourth switch. One end of the third switch is electrically connected to the components of the second matching circuit included in the first matching circuit, and the other end is connected to the output terminal of the first matching circuit. The fourth switch is located between the output terminal of the first matching circuit and the third switch. In a carrier aggregation scenario, the third switch is open and the fourth switch is closed, and the multiplexer is connected to the first matching circuit. In a non-carrier aggregation scenario, the third switch is closed and the fourth switch is open, and the multiplexer is connected to the components of the second matching circuit included in the first matching circuit.

[0013] As one embodiment, the multiplexer includes several multiplexer units, each with the same structure. One of the multiplexer units includes a first resonator, a second resonator, a third resonator, a fourth resonator, and a fifth inductor. The first resonator and the second resonator are connected in series between the switching circuit and the transmitter / receiver of the multiplexer. One end of the third resonator is connected between the first resonator and the second resonator. One end of the fourth resonator is connected to the end of the second resonator away from the first resonator. The other ends of the third resonator and the other ends of the fourth resonator are respectively grounded through the fifth inductor.

[0014] This invention also provides a method for optimizing the insertion loss of a multiplexer, implemented based on the aforementioned multiplexer insertion loss optimization circuit, comprising: When the matching circuit includes a first matching circuit for carrier aggregation scenarios and a second matching circuit for non-carrier aggregation scenarios, the switching circuit is controlled to connect the multiplexer and the first matching circuit to adapt to the carrier aggregation scenario, or the switching circuit is controlled to connect the multiplexer and the second matching circuit to adapt to the non-carrier aggregation scenario. When the matching circuit only includes a first matching circuit for carrier aggregation scenarios, the switching circuit is controlled to connect the multiplexer to the first matching circuit to adapt to the carrier aggregation scenario; or, the switching circuit is controlled to connect the multiplexer to all components of the second matching circuit included in the first matching circuit to adapt to non-carrier aggregation scenarios.

[0015] The present invention also provides an RF front-end module, including the aforementioned multiplexer insertion loss optimization circuit.

[0016] The present invention provides a multiplexer insertion loss optimization circuit, method, and RF front-end module. The circuit includes a multiplexer, a switching circuit, a matching circuit, and an antenna terminal. One end of the matching circuit is connected to the antenna terminal, and the other end of the matching circuit is connected to the switching circuit. The matching circuit includes a first matching circuit for carrier aggregation scenarios and a second matching circuit for non-carrier aggregation scenarios, or the matching circuit only includes the first matching circuit for carrier aggregation scenarios. The first matching circuit includes all components of the second matching circuit. When the matching circuit includes both the first matching circuit for carrier aggregation scenarios and the second matching circuit for non-carrier aggregation scenarios, the switching circuit connects the multiplexer and the first matching circuit to adapt to the carrier aggregation scenario, or connects the multiplexer and the second matching circuit to adapt to the non-carrier aggregation scenario. When the matching circuit only includes the first matching circuit for carrier aggregation scenarios, the switching circuit connects the multiplexer and the first matching circuit to adapt to the carrier aggregation scenario, or connects the multiplexer and all components of the second matching circuit included in the first matching circuit to adapt to the non-carrier aggregation scenario. This invention provides corresponding matching circuits for carrier aggregation and non-carrier aggregation scenarios. In the non-carrier aggregation scenario, a second matching circuit with a simpler structure is used to reduce the impedance requirements of the multiplexer, thereby reducing insertion loss. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a block diagram of the multiplexer insertion loss optimization circuit provided by the present invention.

[0019] Figure 2This is one of the circuit schematics of the antenna terminal and matching circuit provided by the present invention.

[0020] Figure 3 This is the second circuit schematic diagram of the antenna terminal and matching circuit provided by the present invention.

[0021] Figure 4 This is one of the circuit schematics of the switching circuit and matching circuit provided by the present invention.

[0022] Figure 5 This is the second circuit schematic diagram of the switching circuit and matching circuit provided by the present invention.

[0023] Figure 6 This is the third circuit schematic diagram of the switching circuit and matching circuit provided by the present invention.

[0024] Figure 7 This is a circuit diagram of the multiplexer insertion loss optimization circuit provided by the present invention.

[0025] Figure 8 This is a flowchart illustrating the multiplexer insertion loss optimization method provided by the present invention.

[0026] Figure label: 1-Multiplexer, 2-Switching circuit, 3-Matching circuit, 301-First matching circuit, 302-Second matching circuit, 4-Antenna terminal. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0028] Figure 1 This is a schematic block diagram of the multiplexer insertion loss optimization circuit provided by the present invention, as shown below. Figure 1 As shown, the present invention provides a multiplexer insertion loss optimization circuit, including a multiplexer 1, a switching circuit 2, a matching circuit 3, and an antenna terminal 4. One end of the matching circuit 3 is used to connect to the antenna terminal 4, and the other end of the matching circuit 3 is used to connect to the switching circuit 2. The matching circuit 3 includes a first matching circuit 301 applied to a carrier aggregation scenario and a second matching circuit 302 applied to a non-carrier aggregation scenario, or the matching circuit 3 only includes the first matching circuit 301 applied to a carrier aggregation scenario; the first matching circuit 301 includes all the components of the second matching circuit 302.

[0029] When the matching circuit 3 includes a first matching circuit 301 for carrier aggregation scenarios and a second matching circuit 302 for non-carrier aggregation scenarios, the switching circuit 2 is used to connect the multiplexer 1 and the first matching circuit 301 to adapt to the carrier aggregation scenario, or to connect the multiplexer 1 and the second matching circuit 302 to adapt to the non-carrier aggregation scenario.

[0030] When the matching circuit 3 only includes the first matching circuit 301 applied to the carrier aggregation scenario, the switching circuit 2 is used to connect the multiplexer 1 and the first matching circuit 301 to adapt to the carrier aggregation scenario, or to connect the multiplexer 1 and all components of the second matching circuit 302 included in the first matching circuit 301 to adapt to the non-carrier aggregation scenario.

[0031] Optionally, the switching circuit 2 is used to control whether the multiplexer 1 is connected to the matching circuit 3 or some components of the matching circuit 3, and to select a first matching circuit 301 or a second matching circuit 302 suitable for carrier aggregation scenarios or non-carrier aggregation scenarios for the multiplexer 1.

[0032] Optionally, the insertion loss optimization circuit of the multiplexer 1 provided by the present invention further includes a control circuit, which is electrically connected to the switching circuit 2 and is used to send control commands to the switching circuit 2 so that the switching circuit 2 is used to connect the multiplexer 1 and the first matching circuit 301 to adapt to the carrier aggregation scenario, or connect the multiplexer 1 and the second matching circuit 302 to adapt to the non-carrier aggregation scenario, or connect the multiplexer 1 and all components of the second matching circuit 302 included in the first matching circuit 301 to adapt to the non-carrier aggregation scenario.

[0033] It is understood that the present invention sets the matching circuit 3 to include a first matching circuit 301 applied to the carrier aggregation scenario and a second matching circuit 302 applied to the non-carrier aggregation scenario, or the matching circuit 3 only includes the first matching circuit 301 applied to the carrier aggregation scenario; the first matching circuit 301 includes all the components of the second matching circuit 302, and corresponding matching circuits 3 are set for the carrier aggregation scenario and the non-carrier aggregation scenario respectively. In order to meet the requirements of carrier aggregation, the T-type or PI-type matching circuit corresponding to the first matching circuit 301 is used. The T-type or PI-type matching circuit is more complex and will increase the insertion loss. The present invention uses two sets of switchable matching circuits. In the non-CA scenario, the simpler matching circuit corresponding to the second matching circuit 302 is used to reduce the impedance requirement of the multiplexer 1, thereby reducing the insertion loss. The insertion loss in the non-CA scenario can be optimized compared with the CA scenario.

[0034] Figure 2 This is one of the circuit schematics of the antenna terminal and matching circuit provided by the present invention, such as... Figure 2 As shown in the embodiment, the first matching circuit 301 is disposed on the first branch formed by the antenna terminal 4 and the switching circuit 2. The first matching circuit 301 includes a first inductor, a first capacitor and a second inductor. One end of the first inductor is electrically connected to the first capacitor and the other end is grounded. One end of the second inductor is electrically connected to the other end of the first capacitor and the other end is grounded. The second matching circuit 302 includes a third inductor. One end of the third inductor is connected to the second branch formed by the antenna terminal 4 and the switching circuit 2 and the other end of the third inductor is grounded.

[0035] Optionally, the matching circuit 3 provided in this embodiment of the invention includes a first matching circuit 301 and a second matching circuit 302. The first inductor and the third inductor are both electrically connected to the switching circuit 2, and the output terminals of the second inductor and the third inductor are both connected to the load.

[0036] Optionally, in the 2.3-2.69GHz non-carrier aggregation scenario, the second matching circuit 302 only includes a third inductor as a grounding inductor. The parameters of the third inductor and the multiplexer 1 are in a deeply coupled collaborative design relationship. The third inductor is used to realize resonance and impedance transformation, and the inductance value directly determines the matching quality and isolation of the port of the multiplexer 1.

[0037] Specifically, the third inductor and the parasitic capacitance inside the multiplexer 1 form a parallel resonant network. The turn-off capacitor corresponding to the turn-off port of the multiplexer 1 and the third inductor form a parallel resonance at the center frequency point in the non-carrier aggregation scenario, thereby improving the isolation between channels. On the other hand, in the conduction path, the third inductor is used to cancel the inductive component brought by the turn-on transistor of the multiplexer 1, changing the input impedance to about 50 ohms, thereby reducing the insertion loss.

[0038] Therefore, the inductance value of the third inductor can be calculated by back-calculation based on the turn-off capacitance and on-resistance of multiplexer 1 in the 2.3–2.69 GHz frequency band.

[0039] It is understood that, by independently tuning the impedance trajectories of the first and second inductors connected in parallel to different frequency bands, this embodiment of the invention can more flexibly match multiple complex impedance points with significant differences in low-frequency high impedance and high-frequency low impedance simultaneously, avoiding mutual constraints between frequency bands. The first and second inductors exhibit high impedance in non-intrinsic frequency bands, and the first capacitor exhibits high impedance at low frequencies, forming a double blocking effect in non-operating frequency bands. This significantly improves the isolation between the ports of the multiplexer 1 and effectively prevents signal interference between carrier aggregation frequency bands.

[0040] Figure 3This is the second circuit schematic diagram of the antenna terminal and matching circuit provided by the present invention, as shown below. Figure 3 As shown in the embodiment, the first matching circuit 301 is disposed on the first branch formed by the antenna terminal 4 and the switching circuit 2. The first matching circuit 301 includes a second capacitor, a third capacitor and a fourth inductor. One end of the fourth inductor is connected to the second capacitor and the third capacitor respectively, and the other end is grounded. The second matching circuit 302 includes a third inductor. One end of the third inductor is connected to the second branch formed by the antenna terminal 4 and the switching circuit 2, and the other end of the third inductor is grounded.

[0041] Optionally, the second and third capacitors are connected in series, and the second and third capacitors can each form a single-channel L-type matching unit with the fourth inductor.

[0042] Optionally, the principle of the third inductor and the steps for calculating its inductance value are the same as in the above embodiment, and will not be repeated here.

[0043] It is understood that the present invention enables the second and third capacitors to form a single-channel L-type matching unit with the fourth inductor, requiring only one ground inductor, which helps to reduce the circuit size. It can also effectively filter out the second and third harmonics while matching the main frequency, reduce out-of-band noise and spurious signals, and simplify the filtering requirements.

[0044] Figure 4 This is one of the circuit schematics of the switching circuit and matching circuit provided by the present invention, such as... Figure 4 As shown, in one embodiment, when the matching circuit 3 includes a first matching circuit 301 applied to a carrier aggregation scenario and a second matching circuit 302 applied to a non-carrier aggregation scenario, the switching circuit 2 includes a first switch, which is connected to the multiplexer 1, the first matching circuit 301 and the second matching circuit 302 respectively.

[0045] Optionally, the first switch includes a single-pole double-throw switch or a double-pole double-throw switch.

[0046] Optionally, the single-pole double-throw switch includes an input terminal, a first output terminal, and a second output terminal. The input terminal is electrically connected to the multiplexer 1, the first output terminal is electrically connected to the first matching circuit 301, and the second output terminal is electrically connected to the second matching circuit 302.

[0047] Optionally, the double-pole double-throw switch includes a first input terminal and a first output terminal corresponding to the first input terminal, a second input terminal and a second output terminal corresponding to the second input terminal, both the first input terminal and the second input terminal being electrically connected to the multiplexer 1, the first output terminal being electrically connected to the first matching circuit 301, and the second output terminal being electrically connected to the second matching circuit 302.

[0048] It is understood that the embodiments of the present invention use a first switch to form a switching circuit 2, which is connected to the multiplexer 1, the first matching circuit 301 and the second matching circuit 302 respectively, which can reduce the complexity of the circuit and improve the compactness of the layout.

[0049] Figure 5 This is the second circuit schematic diagram of the switching circuit and matching circuit provided by the present invention, as shown below. Figure 5 As shown, in one embodiment, when the matching circuit 3 only includes the first matching circuit 301 applied to the carrier aggregation scenario, the switching circuit 2 includes a second switch. One end of the second switch is electrically connected to the components of the second matching circuit 302 included in the first matching circuit 301, and the other end is connected to the output terminal of the first matching circuit 301.

[0050] Optionally, in a carrier aggregation scenario, the second switch is open, and the multiplexer 1 is connected to the first matching circuit 301. In a non-carrier aggregation scenario, the second switch is closed, and the multiplexer 1 is connected to the components of the second matching circuit 302 included in the first matching circuit 301.

[0051] Optionally, the first matching circuit 301 includes a first inductor, a first capacitor, and a second inductor. One end of the first inductor is electrically connected to the first capacitor, and the other end is grounded. One end of the second inductor is electrically connected to the other end of the first capacitor, and the other end is grounded. The second matching circuit 302 includes the first inductor.

[0052] Optionally, the first matching circuit 301 includes a second capacitor, a third capacitor, and a fourth inductor. One end of the fourth inductor is connected to the second capacitor and the third capacitor, respectively, and the other end is grounded. The second matching circuit 302 includes the fourth inductor.

[0053] It is understood that this application achieves the functions of the first matching circuit 301 and the second matching circuit 302 by including only the first matching circuit 301 for carrier aggregation scenarios in the matching circuit 3, and then electrically connecting one end of the second switch to the components of the second matching circuit 302 included in the first matching circuit 301, and connecting the other end to the output terminal of the first matching circuit 301, thereby reducing the number of circuit components and reducing the circuit layout area.

[0054] Figure 6 This is the third circuit schematic diagram of the switching circuit and matching circuit provided by the present invention, as shown below. Figure 6As shown, in one embodiment, when the matching circuit 3 only includes the first matching circuit 301 applied to the carrier aggregation scenario, the switching circuit 2 includes a third switch and a fourth switch. One end of the third switch is electrically connected to the components of the second matching circuit 302 included in the first matching circuit 301, and the other end is connected to the output terminal of the first matching circuit 301. The fourth switch is located between the output terminal of the first matching circuit 301 and the third switch.

[0055] Specifically, in a carrier aggregation scenario, the third switch is open and the fourth switch is closed, connecting the multiplexer 1 to the first matching circuit 301. In a non-carrier aggregation scenario, the third switch is closed and the fourth switch is open, connecting the multiplexer 1 to the components of the second matching circuit 302 included in the first matching circuit 301.

[0056] Optionally, the first matching circuit 301 includes a first inductor, a first capacitor, and a second inductor. One end of the first inductor is electrically connected to the first capacitor, and the other end is grounded. One end of the second inductor is electrically connected to the other end of the first capacitor, and the other end is grounded. The second matching circuit 302 includes the first inductor. A third switch is electrically connected to the first inductor, and a fourth switch is connected to the second inductor and the third switch.

[0057] It is understood that, in this application, one end of the third switch is electrically connected to the components of the second matching circuit 302 included in the first matching circuit 301, and the other end is connected to the output terminal of the first matching circuit 301. The fourth switch is located between the output terminal of the first matching circuit 301 and the third switch, which can realize the functions of the first matching circuit 301 and the second matching circuit 302, reduce circuit components, and reduce circuit layout area.

[0058] Figure 7 This is a circuit schematic of the multiplexer insertion loss optimization circuit provided by the present invention, as shown below. Figure 7 As shown in the figure, as an embodiment, the multiplexer 1 includes a plurality of multiplexer units, each of which has the same structure. One of the multiplexer units includes a first resonator, a second resonator, a third resonator, a fourth resonator, and a fifth inductor. The first resonator and the second resonator are connected in series between the switching circuit and the transmitter / receiver of the multiplexer. One end of the third resonator is connected between the first resonator and the second resonator. One end of the fourth resonator is connected to the end of the second resonator away from the first resonator. The other ends of the third resonator and the other ends of the fourth resonator are respectively grounded through the fifth inductor. Figure 7 The embodiment shown includes four multiplexer units to form a two-way multiplexer. All multiplexer units have the same structure, which will not be described in detail here.

[0059] It is understood that the present invention uses a first resonator, a second resonator, a third resonator, a fourth resonator and a fifth inductor to form a multiplexer unit, and then uses multiple multiplexer units to form a multiplexer 1, which can make up for the deficiencies in in-band loss and out-of-band suppression.

[0060] It should be noted that the above Figures 2-7 In the diagram, C1-C3 are the first capacitor, the second capacitor, and the third capacitor, respectively; L1-L5 are the first inductor, the second inductor, the third inductor, the fourth inductor, and the fifth inductor, respectively; K1-K4 are the first switch, the second switch, the third switch, and the fourth switch, respectively; SAW1-SAW4 are the first resonator, the second resonator, the third resonator, and the fourth resonator, respectively; ANT is the antenna terminal; TX is the transmitter terminal of the multiplexer; and RX is the receiver terminal of the multiplexer.

[0061] The multiplexer insertion loss optimization method provided by the present invention is described below. The multiplexer insertion loss optimization method described below can be referred to in correspondence with the multiplexer insertion loss optimization circuit described above.

[0062] Figure 8 This is a flowchart illustrating the multiplexer insertion loss optimization method provided by the present invention, as shown below. Figure 8 As shown, the present invention also provides a method for optimizing the insertion loss of a multiplexer, implemented based on the aforementioned multiplexer insertion loss optimization circuit. The multiplexer insertion loss optimization circuit includes a multiplexer, a switching circuit, a matching circuit, and an antenna terminal. One end of the matching circuit is used to connect to the antenna terminal, and the other end of the matching circuit is used to connect to the switching circuit. The matching circuit includes a first matching circuit for carrier aggregation scenarios and a second matching circuit for non-carrier aggregation scenarios, or the matching circuit only includes the first matching circuit for carrier aggregation scenarios. The first matching circuit includes all the components of the second matching circuit. The method includes the following steps.

[0063] Step S100: When the matching circuit includes a first matching circuit for carrier aggregation scenarios and a second matching circuit for non-carrier aggregation scenarios, control the switching circuit to connect the multiplexer and the first matching circuit to adapt to the carrier aggregation scenario, or control the switching circuit to connect the multiplexer and the second matching circuit to adapt to the non-carrier aggregation scenario.

[0064] Step S200: If the matching circuit only includes a first matching circuit for carrier aggregation scenarios, control the switching circuit to connect the multiplexer to the first matching circuit to adapt to the carrier aggregation scenario; or, control the switching circuit to connect the multiplexer to all components of the second matching circuit included in the first matching circuit to adapt to non-carrier aggregation scenarios.

[0065] As one embodiment, the first matching circuit is disposed on the first branch formed by the antenna end and the switching circuit. The first matching circuit includes a first inductor, a first capacitor and a second inductor. One end of the first inductor is electrically connected to the first capacitor and the other end is grounded. One end of the second inductor is electrically connected to the other end of the first capacitor and the other end is grounded. The second matching circuit includes a third inductor. One end of the third inductor is connected to the second branch formed by the antenna end and the switching circuit and the other end of the third inductor is grounded.

[0066] As one embodiment, the first matching circuit is disposed on the first branch formed by the antenna end and the switching circuit. The first matching circuit includes a second capacitor, a third capacitor and a fourth inductor. One end of the fourth inductor is connected to the second capacitor and the third capacitor respectively, and the other end is grounded. The second matching circuit includes a third inductor. One end of the third inductor is connected to the second branch formed by the antenna end and the switching circuit, and the other end of the third inductor is grounded.

[0067] As an example, when the matching circuit includes a first matching circuit for carrier aggregation scenarios and a second matching circuit for non-carrier aggregation scenarios, the switching circuit includes a first switch, which is connected to the multiplexer, the first matching circuit and the second matching circuit respectively.

[0068] As one embodiment, the first switch includes a single-pole double-throw switch or a double-pole double-throw switch.

[0069] As an example, when the matching circuit only includes a first matching circuit for carrier aggregation scenarios, the switching circuit includes a second switch. One end of the second switch is electrically connected to the components of the second matching circuit included in the first matching circuit, and the other end is connected to the output terminal of the first matching circuit. In a carrier aggregation scenario, the second switch is open, and the multiplexer is connected to the first matching circuit. In a non-carrier aggregation scenario, the second switch is closed, and the multiplexer is connected to the components of the second matching circuit included in the first matching circuit.

[0070] As an example, when the matching circuit only includes a first matching circuit for carrier aggregation scenarios, the switching circuit includes a third switch and a fourth switch. One end of the third switch is electrically connected to the components of the second matching circuit included in the first matching circuit, and the other end is connected to the output terminal of the first matching circuit. The fourth switch is located between the output terminal of the first matching circuit and the third switch. In a carrier aggregation scenario, the third switch is open and the fourth switch is closed, and the multiplexer is connected to the first matching circuit. In a non-carrier aggregation scenario, the third switch is closed and the fourth switch is open, and the multiplexer is connected to the components of the second matching circuit included in the first matching circuit.

[0071] As one embodiment, the multiplexer includes several multiplexer units, each with the same structure. One of the multiplexer units includes a first resonator, a second resonator, a third resonator, a fourth resonator, and a fifth inductor. The first resonator and the second resonator are connected in series between the switching circuit and the transmitter / receiver of the multiplexer. One end of the third resonator is connected between the first resonator and the second resonator. One end of the fourth resonator is connected to the end of the second resonator away from the first resonator. The other ends of the third resonator and the other ends of the fourth resonator are respectively grounded through the fifth inductor.

[0072] It should be noted that the multiplexer insertion loss optimization method provided in this embodiment of the invention has the same technical effects as the multiplexer insertion loss optimization circuit, which will not be elaborated further.

[0073] The radio frequency front-end module provided by the present invention is described below. The radio frequency front-end module described below can be referred to in correspondence with the multiplexer insertion loss optimization circuit described above.

[0074] The present invention also provides an RF front-end module, including the aforementioned multiplexer insertion loss optimization circuit. Specifically, the multiplexer insertion loss optimization circuit includes a multiplexer, a switching circuit, a matching circuit, and an antenna terminal. One end of the matching circuit is used to connect to the antenna terminal, and the other end of the matching circuit is used to connect to the switching circuit. The matching circuit includes a first matching circuit for carrier aggregation scenarios and a second matching circuit for non-carrier aggregation scenarios, or the matching circuit only includes the first matching circuit for carrier aggregation scenarios; the first matching circuit includes all the components of the second matching circuit.

[0075] It should be noted that the RF front-end module provided in this embodiment of the invention has the same technical effect as the multiplexer insertion loss optimization circuit, which will not be elaborated further.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multiplexer insertion loss optimization circuit, characterized in that, The device includes a multiplexer, a switching circuit, a matching circuit, and an antenna terminal. One end of the matching circuit is connected to the antenna terminal, and the other end of the matching circuit is connected to the switching circuit. The matching circuit includes a first matching circuit for carrier aggregation scenarios, and the first matching circuit includes a third inductor for non-carrier aggregation scenarios. One end of the third inductor is connected to a second branch formed by the antenna terminal and the switching circuit, and the other end of the third inductor is grounded. The switching circuit is used to connect the multiplexer to the first matching circuit to adapt to the carrier aggregation scenario, or to connect the multiplexer to the third inductor included in the first matching circuit for non-carrier aggregation scenarios: the switching circuit includes a third switch and a fourth switch, one end of the third switch is electrically connected to the third inductor, and the other end is connected to the output terminal of the first matching circuit, and the fourth switch is located between the output terminal of the first matching circuit and the third switch; In a carrier aggregation scenario, the third switch is open, the fourth switch is closed, and the multiplexer is connected to the first matching circuit. In a non-carrier aggregation scenario, the third switch is closed, the fourth switch is open, and the multiplexer is connected to the third inductor.

2. The multiplexer insertion loss optimization circuit according to claim 1, characterized in that, The first matching circuit is located on the first branch formed by the antenna end and the switching circuit. The first matching circuit includes a first inductor, a first capacitor and a second inductor. One end of the first inductor is electrically connected to the first capacitor and the other end is grounded. One end of the second inductor is electrically connected to the other end of the first capacitor and the other end is grounded.

3. The multiplexer insertion loss optimization circuit according to claim 1, characterized in that, The first matching circuit is located on the first branch formed by the antenna end and the switching circuit. The first matching circuit includes a second capacitor, a third capacitor and a fourth inductor. One end of the fourth inductor is connected to the second capacitor and the third capacitor respectively, and the other end is grounded.

4. The multiplexer insertion loss optimization circuit according to claim 1, characterized in that, The multiplexer includes several multiplexer units, each with the same structure. One of the multiplexer units includes a first resonator, a second resonator, a third resonator, a fourth resonator, and a fifth inductor. The first resonator and the second resonator are connected in series between the switching circuit and the transmitter / receiver of the multiplexer. One end of the third resonator is connected between the first resonator and the second resonator. One end of the fourth resonator is connected to the end of the second resonator away from the first resonator. The other ends of the third resonator and the other ends of the fourth resonator are respectively grounded through the fifth inductor.

5. A method for optimizing the insertion loss of a multiplexer, implemented based on the multiplexer insertion loss optimization circuit according to any one of claims 1 to 4, characterized in that, include: When the matching circuit includes a first matching circuit for carrier aggregation scenarios, the switching circuit is controlled to connect the multiplexer to the first matching circuit to adapt to the carrier aggregation scenario; or, the switching circuit is controlled to connect the multiplexer to a third inductor included in the first matching circuit for non-carrier aggregation scenarios.

6. A radio frequency front-end module, characterized in that, Includes the multiplexer insertion loss optimization circuit as described in any one of claims 1 to 4.

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