Methods and apparatus for carrying multiple Ethernet services on a single-channel 224Gbps SerDes network

Abstract

Embodiments of the present application provide a method and device for carrying multiple Ethernet services on a single-channel 224Gbps SerDes, wherein the method comprises receiving at least two Ethernet service signals; performing bit-level interleaving on each service signal according to a preset interleaving granularity to obtain an interleaved bit stream, wherein the interleaving granularity corresponds to the interface data bit width of the physical media attachment sublayer of the SerDes; inserting an alignment mark and an overhead field into each data frame in the interleaved bit stream to encapsulate the data frame; and mapping the encapsulated data frame to the single-channel 224Gbps SerDes for transmission. This scheme can improve the utilization efficiency of SerDes resources, reduce system complexity, and is suitable for high-speed communication scenarios.

Description

Technical Field

[0001] This invention relates to communication technology, and more particularly to a method and apparatus for carrying multiple Ethernet services on a single-channel high-speed SerDes. Background Technology

[0002] With the surge in demand for artificial intelligence, large-scale model training, and data center bandwidth, next-generation high-speed SerDes technology, as a key physical layer support in high-bandwidth Ethernet systems, is rapidly evolving towards higher speeds. For example, in 800G or 1.6T Ethernet systems, 224Gbps SerDes is rapidly being commercialized as a key physical layer technology. Meanwhile, high-speed Ethernet services (such as 100GE) have been deployed on a large scale. How to achieve efficient interoperability between new and old systems without increasing cost and protocol complexity has become a core issue of industry concern. For example, in existing technologies, a single 112Gbps SerDes physical channel typically carries one 100GE Ethernet service. When two or more Ethernet services of equal speed need to be carried, traditional methods often employ parallel configuration of multiple SerDes channels. This approach not only significantly increases high-speed interface resources and costs but also faces more complex signal integrity design and protocol adaptation challenges.

[0003] Currently, there is no unified solution or standard in the industry for carrying dual 100GE services on a single 224Gbps SerDes, and there is a lack of specifications for multiplexing 100GE using a 224Gbps physical channel. Furthermore, there is no universally accepted implementation solution in the high-speed interconnect chip field. While it is possible to aggregate multiple Ethernet services using higher-level encapsulation technologies (such as OTN frame structures or FlexE links), these methods increase overhead, complicate protocol stacks, increase latency, and have high implementation barriers, making them unsuitable for efficient transmission at the physical layer.

[0004] Therefore, there is an urgent need for a simple and effective implementation scheme that can use a single-channel high-speed SerDes resource to achieve efficient carrying and transparent transmission of multiple Ethernet services at the physical layer, thereby improving system resource utilization. Summary of the Invention

[0005] The present invention aims to solve the above-mentioned technical problems and provides a method and apparatus for carrying multiple Ethernet services on a single-channel high-speed SerDes.

[0006] A first aspect of the present invention provides a method for carrying multiple Ethernet services on a single-channel high-speed SerDes, comprising receiving at least two Ethernet service signals; performing bit-level interleaving of each service signal according to a preset interleaving granularity to obtain an interleaved bitstream, wherein the interleaving granularity corresponds to the interface data bit width of the physical medium attachment sublayer of the SerDes; inserting alignment flags and overhead fields into each data frame in the interleaved bitstream to encapsulate the data frame; and mapping the encapsulated data frame to the single-channel high-speed SerDes for transmission.

[0007] Compared to traditional OTN or FlexE encapsulation methods, bit-level interleaving directly integrates bitstreams without requiring complex data link layer frame structures and mapping logic. Through bit-level interleaving, two or more Ethernet services can be aggregated onto a single-channel high-speed SerDes for transmission, doubling SerDes resource utilization and significantly reducing port costs and hardware resource consumption of network devices. Furthermore, the interleaving granularity corresponds to the interface data bit width of the SerDes physical media attachment sublayer, avoiding cumbersome bit-width conversion overhead.

[0008] Optionally, according to a first aspect of the present invention, the method for carrying multiple Ethernet services on a single-channel high-speed SerDes includes bit-level interleaving of each service signal, which includes interleaving using a time-evolution interleaving mode based on preset rules. The time-evolution interleaving mode includes multiple interleaving modes in which the interleaving order dynamically changes over time.

[0009] Optionally, the generation rule for the time-evolutionary interleaving pattern is based on a mirror-symmetric interleaving pattern as the base interleaving pattern, which can serve as the starting point for interleaving pattern evolution (e.g., "abba"). Multiple mirror-symmetric interleaving patterns with progressively increasing lengths are generated by repeatedly inserting the base interleaving pattern at predetermined positions within it. This dynamic interleaving method possesses spectral spreading characteristics, which helps reduce EMI and electromagnetic interference, improve signal integrity, and enhance communication security. For example, the predetermined position can be the middle position of the base interleaving pattern or the middle position of the previous interleaving pattern generated according to this rule.

[0010] Optionally, the bit-level interleaving of each service signal includes: interleaving using different interleaving modes, wherein the interleaving modes are selected from a set of interleaving modes, the set of interleaving modes includes at least one basic interleaving mode and multiple evolved interleaving modes generated iteratively from the basic interleaving modes, each of the evolved interleaving modes is obtained by inserting one or more basic interleaving modes into one of the basic interleaving modes one or more times, and all basic interleaving modes and evolved interleaving modes are centrally mirror-symmetric and have equal time slot allocation for each service signal.

[0011] The set of interleaving patterns is predetermined. Besides the basic interleaving pattern, other interleaving patterns are generated by iteratively or nestedly inserting the basic interleaving pattern. The basic interleaving pattern can be one or more; inserting the same and / or different basic interleaving patterns one or more times onto a basic interleaving pattern can yield multiple interleaving patterns. For example, nesting one of the basic interleaving patterns at the center-symmetric position of the interleaving pattern in each iteration, or at other suitable positions, can generate a new interleaving sequence. Optionally, the set of interleaving patterns includes a basic interleaving pattern and multiple evolving interleaving patterns generated iteratively from the basic interleaving pattern. Each evolving interleaving pattern is obtained by inserting the basic interleaving pattern one or more times into the center of the basic interleaving pattern.

[0012] Optionally, the interleaving granularity is N×32 bits, where N is a positive integer, and is set such that the data frame length is adapted to the interface data bit width of the SerDes physical medium attachment sublayer. This granularity can be naturally aligned with existing 112G PMA (4×32 bits) and anticipated 224Gbps PMA (8×32 bits) interfaces, thereby avoiding additional bit width conversion and simplifying the implementation process.

[0013] Optionally, the alignment flag includes a predefined bit sequence inserted at a fixed period. The receiving end detects the predefined bit sequence a set number of times at predetermined intervals to synchronize data frames, thereby achieving frame synchronization and improving the reliability and robustness of frame recognition. For example, when the receiving end detects the predefined bit sequence more than three times, it can be considered that the frame header has been successfully recognized.

[0014] Optionally, the overhead field may include, but is not limited to, service validity flag, link error flag, pass-through indication flag, location indication, and service mode identifier, which are used to correctly parse the service channel, service status, and transmission mode at the receiving end to assist in link management and service identification.

[0015] Unlike traditional FlexE or OTN encapsulation methods, the data frames of this invention do not include complex data link layer frame structures. Instead, they adopt a lightweight frame structure scheme, avoiding high-overhead frame mapping and logic parsing processes, thus reducing implementation complexity and transmission latency.

[0016] Optionally, the interleaving using different interleaving modes includes the sending and receiving ends using the same pseudo-random number generator and shared seed parameters, using the current frame number as an index, and mapping the corresponding interleaving mode in real time according to the output value of the pseudo-random number generator to achieve synchronous switching of the interleaving modes at the sending and receiving ends; or the sending and receiving ends include the same lookup table and state machine, the lookup table storing the set of interleaving modes, and the state machine calling the corresponding interleaving mode from the lookup table based on the current frame number or frame count value, based on a preset step size or the output value of the pseudo-random number generator. Optionally, the real-time mapping of the corresponding interleaving mode according to the output value of the pseudo-random number generator can be implemented using a lookup table, or the output value of the pseudo-random number generator can be used as a nested parameter to directly obtain its corresponding interleaving mode. The latter can be obtained through real-time calculation by logic circuits.

[0017] Optionally, in a preferred embodiment, at least two Ethernet service signals are 100Gbps Ethernet signals, which are encapsulated and transmitted via a single-channel 224Gbps SerDes, significantly improving the bandwidth utilization of the single-channel SerDes.

[0018] A second aspect of the present invention also provides a communication device, including a processor and a SerDes module. The processor is used to perform the aforementioned interleaving and encapsulation operations, and the SerDes module is used to transmit the encapsulated data frame output by the processor to an optical module. This communication device can be implemented as a GearBox chip or a transparent transmission chip, respectively suitable for scenarios such as link aggregation and long-distance transparent forwarding.

[0019] Furthermore, a third aspect of the present invention provides an Ethernet service bearer system, including at least one of the aforementioned communication devices, wherein the processor of the communication device is configured in a GearBox chip or a pass-through chip. This system architecture can be flexibly deployed in devices such as switches, optical modules, and data center interconnect devices, adapting to current and future network infrastructure upgrade needs.

[0020] Embodiments of this invention aggregate multiple (e.g., two) Ethernet services onto a single-channel high-speed SerDes, doubling SerDes resource utilization and significantly reducing port costs and complexity in high-end network equipment. Furthermore, embodiments of this invention employ bit-level interleaving and a lightweight frame structure, skipping complex encapsulations such as OTN / FlexE, resulting in lower implementation difficulty and transmission latency, facilitating rapid chip implementation and deployment. Moreover, embodiments of this invention adapt to different rates and scenario requirements through dynamic interleaving modes. Using a time-evolutionary interleaving mode as the dynamic interleaving mode optimizes signal integrity, reduces electromagnetic interference, and provides a certain level of physical layer security and link diagnostic capabilities.

[0021] Implementing any apparatus or method of the present invention does not necessarily require achieving all of the advantages described above simultaneously. Other features and advantages of the invention will be set forth in the following description and will be apparent in part from the description and embodiments, or may be learned by practicing the invention. The objects and advantages of the embodiments of the invention can be realized and obtained by means of the structures pointed out in the description, claims, and drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present invention, and are not intended to limit the present invention.

[0023] Figure 1 This is a schematic diagram of the data processing flow at the sending end according to an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the data processing flow at the receiving end according to an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the frame format according to an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of a communication system architecture that uses a single-channel 224Gbps SerDes to carry two 100GE services according to an embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of a communication system architecture that uses a single-channel 224Gbps SerDes to carry two 100GE services according to another embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Different embodiments can be combined with each other to constitute other embodiments not shown in the following description. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, “an” or “a” and similar terms do not necessarily indicate a quantity limitation. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0030] Figure 1 This is a schematic diagram of the data processing flow at the transmitting end according to an embodiment of the present invention. In step S11, at least two Ethernet service signals are received. For example, at least two bitstream signals of Ethernet services are obtained through an interface module (such as the Physical Coding Sublayer (PCS)). For example, this embodiment includes two 100GE service signals, denoted as service stream A and service stream B, respectively, each corresponding to a high-speed bitstream of approximately 112Gbps.

[0031] In step S12, according to the set interleaving granularity (e.g., N×32bit, where N is a positive integer), bits are alternately extracted from at least service flow A and service flow B and output to the interleaving buffer to form an interleaved bit stream. If the number of service paths with the same rate exceeds two, a round-robin approach can be used to extract bit streams evenly from each service path sequentially, achieving flexible expansion of multi-service fusion. The frame formed in this way is called a lightweight bit frame in this invention, which is a simplified frame structure composed of bit-level interleaving, interleaving with single bits. Because the complex data structure of technologies such as OTN frames or FlexE is no longer considered, but a very intuitive bit interleaving approach is adopted, the frame structure of this invention is relatively simple compared to the data layer encapsulation frame structure of technologies such as OTN or FlexE. During the data interleaving process, the order of interleaving of each service is not strictly defined, and the length of the interleaved data is, for example, N×32bit, where N can be determined according to the commonly used data bit width of the current interface. For example, the interface data width of an existing 112Gbps SerDes Physical Medium Attachment (PMA) sublayer is typically 4*32 bits, while the expected interface data width of a 224Gbps PMA is 8*32 bits. Determining N based on the commonly used interface data width can simplify the data link implementation logic and avoid introducing circuits such as bit width conversion.

[0032] For example, to match the data bit width of the SerDes interface, N can be set to 16, with each Ethernet service signal outputting 256 bits, resulting in a total interleaving length of 512 bits for each frame.

[0033] In step S13, a frame encapsulation operation is performed, during which link control information is inserted. Specifically, an alignment marker and an overhead field can be inserted, with at least the alignment marker placed in the frame header. The overhead field can be included in the frame header or other suitable locations. To achieve efficient carrying of multiple Ethernet service signals on a single-channel SerDes link, this invention designs a lightweight encapsulation frame format. Figure 3 An example of a frame format encapsulation according to the present invention is shown. This frame format uses N×32-bit data frames as the basic unit of interleaving and encapsulation, inserting alignment flags and overhead fields into each frame to achieve synchronization, status identification, and channel identification between the transmitting and receiving ends. Figure 3 In the example, the interleaving module interleaves two Ethernet service signals (denoted as A and B) at the bit level, using an alternating method to sequentially arrange the bits of the two services to form a bearer bit stream. Specifically, the interleaving sequence is to extract one bit from service A, then one bit from service B, and so on, forming an interleaving sequence A1, B1, A2, B2, A3, B3... until the accumulated number of interleaved bits reaches a preset length, such as N×32 bits (N is a positive integer), thus forming a complete interleaved data frame. This bit-level interleaving is suitable for service scenarios with equal bandwidth (e.g., both 100GE). This interleaving mode facilitates peer-to-peer restoration during subsequent deinterleaving and provides good signal spectrum uniformity and link adaptability.

[0034] Alignment flags are used to indicate the start of a data frame for frame synchronization at the receiving end, i.e., for frame header alignment. To facilitate the receiver's identification of the alignment flag, a predetermined pattern (i.e., a predetermined sequence of binary bits) can be inserted at fixed periods / intervals. The receiver checks according to a preset period; if the same specific pattern is detected three times consecutively, frame synchronization and locking operations are completed accordingly. For example, the transmitter inserts an alignment flag at the header of each frame, and the receiver performs continuous matching with a preset frame length as the step size, searching for the preset pattern in the received bitstream and verifying it at two fixed frame length intervals. If a matching pattern is detected three times consecutively, frame locking is determined. This mechanism eliminates interference from random patterns in the data payload, avoids misidentification problems caused by occasional bit errors or link jitter, and balances synchronization reliability with implementation complexity. If the predefined bit sequence is not detected at the expected position within a predetermined consecutive data frame period, frame out-of-synchronization is determined, and a realignment process is triggered.

[0035] The overhead field (OH) can include the following flags: Service validity flag (Client_vld), indicating whether the corresponding data frame is a valid or real service; otherwise, it indicates an "empty" service. Transponder mode flag (transpondermode), indicating whether the next-level station does not need to perform data parsing and can directly transmit the data, or whether data parsing is required according to the overhead indication. Link status or link error flag (Link_error), indicating whether there is an error or anomaly in the link. Position indication, used for alternating flips to identify frame loss or logical synchronization failure. Service mode flag, used to indicate the current frame's working status, such as whether it is in normal data transmission mode or link diagnostic test mode. The overhead field can also include a service flow identifier (Client_id) to identify the characteristics of each service. The encapsulated interleaved bitstream ensures that it can be accurately identified and reconstructed at the receiving end.

[0036] Here is a specific example of the overhead field OH:

[0037] Bits 7 and 6 in the overhead field indicate whether services 0 and 1 are valid, respectively. Bits 5 and 4 in the overhead field indicate whether services 0 and 1 are in transparent transmission mode or deinterleaving mode. In transparent transmission mode, the original service flow is directly transmitted. In deinterleaving mode, the receiving end must perform deinterleaving operation based on the overhead data to restore the original service flow. Bits 3 and 2 in the overhead field indicate whether there are errors or anomalies in the links of services 0 and 1, respectively. Bit 1 in the overhead field indicates the position indicator of the service flow, used to identify the position of service 1 in the interleaving sequence. This bit provides a phase reference indicator in the time domain for service 1 by alternating logical values ​​between adjacent frames. Optionally, bit 1 can also be used to indicate the position of service 0. At the receiving end, after extracting the data block of service 1, the corresponding bit 1 is synchronously detected. If bit 1 remains unchanged for two consecutive frames (both 0 or both 1), it can be determined that a frame is lost or logically out of sync, and a realignment process can be triggered. Here, high-precision phase alignment under the time-division multiplexing architecture is achieved with only 1 bit of extremely low overhead. By monitoring the toggle status of bit1, physical layer link failures and higher-layer protocol logic errors can be distinguished, improving system maintainability. With a larger number of services, the location indicator here can occupy more than one bit, providing a location reference flag for the service through toggle or regular changes. Bit0 in the overhead field indicates the current service mode, for example, it can be used to distinguish between normal working mode and maintenance test mode.

[0038] It should be understood that although the overhead field is 8 bits in the above example, in actual applications, the length and bit definition of the overhead field can be extended or remapped as the number of services carried increases.

[0039] The service flow identifier (Client_id) can be used for service identification, distribution, and parsing / reassembly. It is a unique identifier for each service, facilitating identification by the receiving end. In this example, each service flow identifier has 12 bits, and its length can be modified as needed.

[0040] In step S14, the carried bit stream is mapped to the PMA, and data is transmitted via the optical module through the single-channel SerDes physical link, converting the electrical signal into an optical signal for long-distance transmission.

[0041] Figure 2This is a schematic flowchart of the data processing at the receiving end according to an embodiment of the present invention. In step S21, the SerDes module receives the bearer bitstream and completes clock data recovery (CDR) and serial-to-parallel conversion operations, providing parallel data for subsequent processing. In step S22, the presence of an alignment flag is detected. When a predetermined pattern is detected a set number of times (e.g., a binary bit sequence can be repeatedly detected three times at a predetermined frame interval), the frame header is considered successfully identified, thus entering a frame locking or frame synchronization state. The overhead field is then parsed to extract information such as the service flow flag, service validity flag, and / or link error flag corresponding to each data frame. In step S23, based on the overhead parsing results, the interleaved bitstream is deinterleaved and reassembled to recover each Ethernet service signal for output to downstream modules, such as the PCS layer module or MAC module. In step S24, two or more Ethernet service signals are 64b / 66b decoded and frame recovered, completing the parsing, processing, and forwarding of Ethernet frames. Through the above receiving process, the parsing and effective splitting of received frames are achieved. This ensures that the original business data can be accurately restored.

[0042] Figure 1 and Figure 2 The methods of the transmitting end and the receiving end of the present invention are mutually corresponding.

[0043] This invention significantly improves the resource utilization of SerDes channels by interleaving multiple Ethernet service bitstreams at the bit level and mapping them to a single-channel high-speed SerDes for transmission. Compared to the existing method of each SerDes channel carrying one Ethernet service, this solution doubles the channel carrying efficiency, significantly reduces the SerDes channel requirements and chip resource consumption in high-end network equipment, and has a significant cost optimization effect. This invention breaks away from the complex mode of traditional network protocol layer encapsulation, and achieves transparent transmission of multiple independent services through efficient bitstream integration at the physical layer, avoiding the high latency and high complexity caused by complex processing at the PCS layer.

[0044] In scenarios where a single-channel 224Gbps SerDes carries two 100GE Ethernet services, this invention adapts the data bit widths of the 112Gbps and 224Gbps PMA interfaces (4×32bit and the expected 8×32bit, respectively) at the interleaving granularity. This avoids introducing additional bit width conversion circuitry and achieves transparent encapsulation without altering the upper-layer PCS / MAC processing flow, thus improving the simplicity of engineering implementation. This solution is applicable to various hardware platforms such as FPGA and ASIC, facilitating rapid deployment by chip manufacturers.

[0045] exist Figure 1 and Figure 2In this embodiment, to optimize transmission quality, a time-evolved interleaving mode can be used as a dynamic interleaving mode instead of a static interleaving mode. In a static interleaving mode, for example, two service flows, a and b, can be interleaved in a fixed ababab or abba pattern. The time-evolved interleaving mode refers to dynamically switching the interleaving order according to predetermined rules to achieve superior transmission performance, signal integrity, and system resilience. The time-evolved interleaving mode forms a series of variable-length and topologically symmetric pseudo-random interleaving sequences. This dynamic evolution can form a deterministic, timing-predictable, dynamically changing interleaving structure. For example, a shorter mirrored interleaving mode (e.g., abba) can be used as the base mirrored interleaving mode, and this base mirrored interleaving mode can be used as the initial mode. Each subsequent evolved interleaving mode can be based on the previous interleaving mode, inserting one or more of the aforementioned base mirrored interleaving modes at predetermined positions to gradually expand the interleaving length and enhance the interleaving complexity. Each resulting interleaving mode is symmetric and longer than the previous interleaving mode. For example, the predetermined position can be the middle position of the base interleaving mode or the middle position of the previous interleaving mode generated according to this rule. For example, a time-evolutionary interleaving pattern could be abba→ababbaba→abababbababa→ababababbabababa, etc. Here, the various interleaving patterns constructed from these two services can evolve over longer periods. The length of the interleaving configuration is related to the payload capacity of the service frame. For example, the interleaving length can not exceed N*32 bits. Multiple interleaving patterns can be used cyclically or selected according to different stages of communication. For instance, if N=2, carrying two Ethernet services, the longest interleaving pattern could be 16 ab and 16 ba connected together.

[0046] For the case of three services a1, b1, and c1, the basic mirroring patterns may include, but are not limited to, abccba, bcaacb, and cabbac. During pattern evolution, a new mirroring pattern is obtained by inserting one of the above-mentioned basic mirroring patterns once or multiple times at a predetermined position (such as the center position or other predetermined positions) in the current mirroring pattern. For example, the evolution process may be abccba→abcabccbacba→abcabcabccbacbacba, or alternatively, the evolution process may be abccba→abcbcaacbcba→abcbcaabccbaacbcba, etc. In one embodiment of the present invention, a non-unique set of basic pattern candidates may be preset, and each basic pattern in the candidate set satisfies the following constraints: the sequence structure is centrally mirror-symmetric, and within a single basic pattern period, the number of physical time slots allocated to each Ethernet service is exactly equal.

[0047] This interleaving design brings multi-dimensional technical advantages by introducing a time-evolving interleaving mode. First, the dynamic evolution of the interleaving mode causes the spectral characteristics of the output signal to change continuously over time, significantly reducing discrete spectral peaks. This effectively improves electromagnetic compatibility, enhances signal integrity and anti-crosstalk capabilities, facilitates compliance testing, and reduces interference to other circuits within the system.

[0048] Secondly, because the interleaving sequence is not fixed, it avoids resonance problems with specific interference frequencies and, combined with a pseudo-random control mechanism, provides physical layer encryption, thereby enhancing the system's anti-interference and anti-detection security. If the mode-switching sequence is part of a preset key, even if an unauthorized receiver locks the data stream, it cannot correctly deinterleave the data because it does not understand the pattern of mode changes. This provides a higher level of confidentiality for the data than a static mode.

[0049] In addition, the mechanism supports flexible selection of interleaving modes of different lengths and complexities based on the communication stage, realizing adaptive optimization of the link. That is, a short mode with low latency and fast synchronization is used in the initial stage, while a long mode with stronger anti-interference and fault resistance is used in the stable stage to improve the overall communication robustness.

[0050] Furthermore, the system can infer channel conditions by analyzing bit error rate performance in different modes, thus possessing certain link diagnostic and health monitoring capabilities. For example, if the bit error rate is low in short-mode but high in long-mode, it may indicate specific jitter or interference at specific frequencies in the channel. This mechanism can also support protocol negotiation and evolutionary design without changing the hardware architecture. Simultaneously, it enables low-barrier interoperability between multiple vendors, demonstrating good system resilience and compatibility.

[0051] Furthermore, the mode switching timing can evolve deterministically under this method, and the overall transmission delay of the communication system is determined by the longest interleaving mode, which does not introduce additional jitter, thus ensuring the predictability and stability of the system.

[0052] To ensure that the timing evolution interleaving mode can be synchronized between the receiver and the transmitter, a mode identifier (such as the Mode ID field) can be optionally set in the overhead field to mark different modes.

[0053] In another optional embodiment of the present invention, to achieve dynamic evolution and configurable control of the interleaving mode, a set of hardware logic for mode control can be configured at both the transmitting and receiving ends, comprising a combination of a lookup table (LUT) and a state machine. Compared to the fixed mode, this dynamic mode requires additional control logic to store the mode sequence and manage the switching timing, which can be implemented using a lookup table and a state machine. This approach increases hardware overhead in hardware such as FPGAs or ASICs, but the increased hardware overhead is acceptable. This approach can implement the lookup table (LUT) with extremely low logic resource consumption, resulting in a low overall system resource utilization.

[0054] The lookup table can be preset with multiple interleaving mode sequences, each corresponding to a set of bit interleaving order or bit path control information. This lookup table can be stored in a register array or programmable memory, allowing access to a specific interleaving mode via an index. The state machine manages the current interleaving mode state of the system and triggers state transitions according to preset rules. State transition rules may include, but are not limited to: reaching a certain threshold for the number of transmitted or received frames, entering a specific mode after system initialization, dynamic transitions based on the output of a pseudo-random number generator (PRNG), or fixed interleaving strategies set by configuration registers.

[0055] When the state switching rule is based on dynamic switching using a pseudo-random number generator, both the transmitting and receiving ends can achieve synchronous and deterministic switching of the interleaving mode based on the pseudo-random number generator and shared seed parameters. Optionally, to achieve synchronous switching of the interleaving mode, after successfully detecting the alignment flag and completing frame locking, the receiving end uses the start time of the lock as the initial zero point for frame sequence number counting. The receiving end loads the same seed parameters as the transmitting end at this zero point, ensuring that the output sequence of the local pseudo-random number generator is strictly aligned with that of the transmitting end. Since both parties use this determined frame header position as the starting reference for PRNG evolution, the interleaving mode of both ends remains absolutely consistent. More specifically, during the initialization of the communication system, the transmitting and receiving ends can pre-agree on the same pseudo-random number generation algorithm and seed parameters, and agree on a set of mapping rules between frame number ranges and interleaving mode indices. For example, there are four interleaving modes. Frames 1 to 100 use the basic interleaving mode 1; frames 101 to 500 select a mode (e.g., mode 2) based on the nth output generated by the pseudo-random number generator; and frames 501 to 1000 select a mode (e.g., mode 4) based on the mth output of the PRNG. Here, m and n can be determined based on the frame number.

[0056] In another optional embodiment of the invention, the switching of the interleaving mode can be generated in real time by pseudo-random logic, without relying on a combination of large-scale lookup tables and complex state machines. Similarly, both the sending and receiving ends deploy the same pseudo-random number generator and share the same seed parameters. The output generated each time by the pseudo-random number generator is used to control the switching of the bit interleaving mode. The system obtains the output of the pseudo-random number generator by using the transmitted frame sequence number as an index.

[0057] For example, if a total of four interleaving modes are supported, the system can use the following mapping method:

[0058] For the p-th frame (where p is an integer), the pseudo-random number generator outputs PRNG(p). The result of PRNG(p) mod 4 is used as the selection factor for the interleaving mode, i.e.:

[0059] If PRNG(p)mod4=0, then mode1 is used;

[0060] If PRNG(p)mod4=1, then mode2 is used;

[0061] If PRNG(p)mod4=2, then mode3 is used;

[0062] If PRNG(p)mod4=3, then mode4 is used.

[0063] Since the same pseudo-random number generators run synchronously at both the sending and receiving ends, this mechanism can achieve synchronous switching of interleaving modes without explicit signaling, ensuring data consistency and anti-interference capability of the communication system.

[0064] The above-mentioned real-time mapping of the pseudo-random number generator's output value to the corresponding interleaving mode can be implemented using a lookup table, or the pseudo-random number generator's output value can be used as nested parameters to directly obtain the corresponding interleaving mode. Using a lookup table eliminates the need for complex logical operations, reducing processing latency. Real-time calculation using nested parameters saves storage space and easily supports more evolution modes.

[0065] The above design balances system flexibility, complexity, and power consumption. Because the switching process is based on real-time algorithmic logic calculations, it avoids processing latency caused by memory access. While significantly reducing hardware logic overhead, it can also be expanded to support interleaving control requirements with different security levels. For example, lookup tables can be used as part of physical layer encryption, enhancing the data link's anti-interference and anti-detection capabilities without altering the frame structure. This synchronous design ensures that the system can achieve highly reliable frame synchronization and mode alignment even under high-speed dynamic interleaving conditions.

[0066] Furthermore, the system can also incorporate a counter-based deterministic switching mechanism, maintaining consistency in interleaving mode switching through a pseudo-random number generator and seed shared by the sender and receiver. This mechanism avoids reliance on explicit signaling, thereby improving the system's synchronization robustness. This design ensures highly reliable frame synchronization and mode alignment even under dynamic interleaving conditions.

[0067] Embodiments of the present invention also provide a communication device, which can be a transmitter for sending Ethernet service data to an optical transport network. The communication device includes a processor and a SerDes module. The processor can be configured to at least execute reference... Figure 1 Steps S11-S13 are described above. Specifically, the processor receives at least two Ethernet service signals and performs bit-level interleaving on them, with the interleaving granularity corresponding to the interface data bit width of the SerDes PMA. The processor inserts alignment flags and overhead fields into the interleaved data payload to complete data frame encapsulation. The SerDes module receives the encapsulated data frame, performs parallel-to-serial conversion and physical layer encoding, and then transmits it through a single-channel physical link.

[0068] Alignment flags may include predetermined bit patterns / combinations. Overhead fields may include at least a traffic flow flag, a traffic valid flag, a pass-through mode indicator, and a link error flag.

[0069] The processor can also perform bit-level interleaving of at least two Ethernet service signals using the timing evolution interleaving mode described above. The interleaving mode is mirror-symmetric, and its generation rule can be based on a basic short symmetric mode (such as "abba") as the base interleaving mode. By inserting the base interleaving mode once or multiple times at predetermined positions within it, a longer symmetric interleaving mode with progressively increasing length is generated. This can be a mirror interleaving mode. The longest interleaving mode does not exceed the length of the data frame. According to the above embodiment, the granularity of the data frame can be N*32. The processor can be an ASIC, FPGA, or other hardware processing unit with programmable logic gates, or a combination of one or more of these devices. The processor can include instructions, and the corresponding instructions can be stored in memory or other hardware devices.

[0070] Furthermore, embodiments of the present invention provide another communication device, which can be a receiver for receiving data transmitted by an optical transport network. This communication device includes a processor and a SerDes module. The processor can at least execute the reference... Figure 2Steps S21-S23 are described above. Specifically, the processor receives parallel data from the SerDes module, identifies alignment flags in the bitstream for data frame synchronization, and then parses the overhead field. The processor then performs a reverse deinterleaving process corresponding to the transmitting end, splitting the interleaved composite bitstream into at least two Ethernet service signals. The processor sends the split at least two Ethernet service signals to a downstream module (such as PCS or MAC layer logic), which performs 64b / 66b decoding and frame recovery to obtain the original Ethernet service data. The deinterleaving method of the processor can correspond to the interleaving method of the receiving end's communication device. The processor can be an ASIC, FPGA, or other hardware processing unit with programmable logic gates, or a combination of one or more of these devices. The processor may include instructions, which can be stored in memory or other hardware devices.

[0071] Figure 4 This diagram illustrates an Ethernet service bearer system based on a single-channel high-speed SerDes according to an embodiment of the present invention, using two 100GE services as examples to illustrate how the invention is applied in a communication link. Two 100GE Ethernet service signals are emitted via a first set of 100GE chips and respectively enter a first GearBox chip. The first GearBox chip uses the bit-level interleaving method described in this invention to interleave and encapsulate the two Ethernet signals to form a single bearer bitstream, thereby generating a signal that meets the single-channel 224Gbps first SerDes rate interface requirements. The signal output from the first SerDes is transmitted to the optical network via an optical module. The receiving optical module transmits the received signal to a single-channel 224Gbps second SerDes, which is then restored to two 112Gbps Ethernet service signals via a second GearBox chip, and the original Ethernet service data is recovered by the corresponding second set of 100GE chips. In this embodiment, the GearBox chip is used to implement bit-level interleaving of two 100GE Ethernet service signals and encapsulate the data frames to form a structured interleaved bit stream. After receiving data sent via SerDes, it can perform deinterleaving, service splitting, and recovery.

[0072] Figure 5 This diagram illustrates another Ethernet service bearer system based on a single-channel high-speed SerDes according to an embodiment of the present invention. Figure 4The difference lies in its inclusion of a transponder chip designed for long-distance transmission. Two 100GE Ethernet service signals are transmitted via a third set of 100GE chips and then enter the third GearBox chip. The third GearBox chip uses the bit-level interleaving method described in this invention to interleave and encapsulate the two Ethernet signals into a single-pass bitstream, thereby generating a signal that meets the requirements of the single-channel 224Gbps third SerDes rate interface. The signal output from the third SerDes is transmitted to the optical network via an optical module. The transponder chip of the relay node receives the 224Gbps data stream from the transmitter and can operate in two modes: transparent transmission mode and decapsulation-recapsulation mode. In transparent transmission mode, it directly forwards the bitstream transparently without decapsulation and reassembly. When transmission quality deteriorates due to increased bit error rate or decreased signal-to-noise ratio, the relay node can switch to decapsulation-recapsulation mode to reconstruct the frame structure, ensuring downstream communication quality. Simultaneously, it can encapsulate corresponding alignment and overhead fields for downstream nodes to parse and adapt. The receiving optical module transmits the received signal to the single-channel 224Gbps fourth SerDes, which is then converted back into two 112Gbps Ethernet service signals by the fourth GearBox chip. The original Ethernet service data is then recovered by the corresponding fourth group of 100GE chips. The GearBox chip and... Figure 4 The illustrated embodiments function identically. In the structure of this embodiment, the transparent transmission chip enables remote and transparent transmission of two 100GE services over a single-channel 224Gbps high-speed SerDes, without relying on traditional FlexE, OTN, or wavelength division multiplexing equipment, reducing power consumption and complexity while maintaining high link utilization efficiency. This application scenario can also be applied to data center interconnect (DCI), high-speed interconnection between switch chips, low-cost long-distance transmission, and other fields. Both the transparent transmission chip and the GearBox chip can implement the bit-level interleaving method described in this invention to achieve a system that aggregates two or more Ethernet service signals into a single high-speed SerDes channel; they can include the processor described in the embodiments above.

[0073] exist Figure 4 and Figure 5 In this embodiment, the Gearbox chip is used to implement service access and aggregation within the network device; the pass-through chip is used to implement long-distance transmission and pass-through.

[0074] Although the above embodiments of the present invention are illustrated using two 100GE services as an example, the present invention is not limited thereto. Within the allowable range of interleaving granularity, the system can be expanded to three or more constant-speed Ethernet services. Bits are sequentially extracted from multiple service streams and interleaved in an alternating manner to form a unified lightweight bit frame, thereby further improving the carrying capacity of the SerDes channel. The interleaving granularity can be adaptively adjusted to match SerDes interfaces with different baud rates (such as 112G, 224G, or future 448G), achieving decoupling between logical architecture and physical rate.

[0075] This invention can be applied to point-to-point interconnection architectures and also supports transparent transmission or decapsulation / recapsulation structures in relay scenarios. By introducing a transparent transmission indicator field and dividing the functions of GearBox units and transparent transmission units, a flexible and expandable physical link structure can be constructed to adapt to different deployment requirements from inside the data center to the metropolitan area backbone network.

[0076] This invention can directly serve fields with stringent requirements for instantaneous bandwidth and end-to-end latency, such as AI / ML computing clusters and 800G / 1.6T data centers. By providing a high-efficiency, low-cost interconnect solution, it significantly reduces the energy consumption per bit of transmission, providing underlying technical support for improving the interconnect stability and energy efficiency of ultra-large-scale computing clusters, and is suitable for the construction of next-generation digital infrastructure.

[0077] The embodiments of the present invention can be modified and altered in various ways without departing from the spirit and scope of the invention. Therefore, it should be understood that the scope of protection of the present invention should not be limited to the exemplary embodiments described above, but should cover the full scope defined by the claims and their equivalents.

Claims

1. A method for carrying multiple Ethernet services on a single-channel 224Gbps SerDes, characterized in that, include: Receive at least two independent Ethernet service signals; According to the preset interleaving granularity, each service signal is interleaved bit by bit. Bits are extracted from each service stream and output to the interleaving buffer to obtain an interleaved bit stream. The interleaving granularity corresponds to the interface data bit width of the physical medium attachment sublayer of SerDes. An alignment flag and an overhead field are inserted into each data frame in the interleaved bitstream to encapsulate the data frame, wherein the overhead field includes a traffic flow identifier; The encapsulated data frames are mapped to a single-channel 224Gbps SerDes for transmission. The single-bit interleaving of each service signal includes: Single-bit interleaving is performed using different interleaving modes, which are selected from a set of interleaving modes, including at least one basic interleaving mode and multiple evolved interleaving modes generated iteratively from the basic interleaving mode. Each evolved interleaving mode is obtained by inserting one or more basic interleaving modes into one of the basic interleaving modes one or more times. All basic interleaving modes and evolved interleaving modes are centrally mirror-symmetric and have equal time slot allocation for each service signal.

2. The method for carrying multiple Ethernet services on a single-channel 224Gbps SerDes according to claim 1, characterized in that, The set of interleaving patterns includes a basic interleaving pattern and multiple evolved interleaving patterns generated iteratively from the basic interleaving pattern. Each of the evolved interleaving patterns is obtained by inserting the basic interleaving pattern once or multiple times into the center of the basic interleaving pattern.

3. The method for carrying multiple Ethernet services on a single-channel 224Gbps SerDes according to claim 1, characterized in that, The interleaving granularity is N×32 bits, where N is a positive integer and is set such that the data frame length is adapted to the interface data bit width of the physical medium attachment sublayer of the SerDes.

4. The method for carrying multiple Ethernet services on a single-channel 224Gbps SerDes according to claim 1, characterized in that, The alignment flag includes a predefined bit sequence inserted at a fixed period. The receiving end synchronizes data frames by detecting the predefined bit sequence a set number of times at predetermined intervals.

5. The method for carrying multiple Ethernet services on a single-channel 224Gbps SerDes according to claim 1, characterized in that, The overhead field includes a service validity flag, a link error flag, a pass-through indication flag, a location indication, and a service mode identifier. The location indication is used to identify frame loss or logical synchronization failure at the receiving end by alternating and flipping logical values ​​between adjacent frames.

6. The method for carrying multiple Ethernet services on a single-channel 224Gbps SerDes according to claim 1, characterized in that, The data frames do not include OTN frame structures or FlexE frame structures.

7. The method for carrying multiple Ethernet services on a single-channel 224Gbps SerDes according to claim 1, characterized in that, The use of different interleaving modes for interleaving includes: The transmitting and receiving ends use the same pseudo-random number generator and shared seed parameters, with the current frame number as an index, to map the corresponding interleaving mode in real time according to the output value of the pseudo-random number generator, thereby achieving synchronous switching of the interleaving modes at the transmitting and receiving ends; or The sending end and the receiving end include the same lookup table and state machine. The lookup table stores the set of interleaving modes. The state machine calls the corresponding interleaving mode from the lookup table based on the current frame sequence number or frame count value, based on a preset step size or the output value of a pseudo-random number generator.

8. A communication device, characterized in that, It includes a processor and a SerDes module, the processor being configured to perform the method as described in any one of claims 1-7, and the SerDes module being configured to transmit the encapsulated data frame output by the processor to an optical module.

9. An Ethernet service bearer system, characterized in that, It includes at least one communication device as described in claim 8, wherein the processor of the communication device is configured in a GearBox chip or a pass-through chip.

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