Gain adaptive infrared focal plane readout circuit and control method

Abstract

The present disclosure provides a gain adaptive infrared focal plane readout circuit and a control method, which realizes in-pixel gain adaptive switching and coarse-fine two-level quantization splicing, significantly expands the dynamic range while considering the sensitivity of weak signals, reduces the risk of saturation distortion and halation crosstalk, and thus improves the overall signal-to-noise ratio and output stability of infrared focal plane imaging.

Description

Technical Field

[0001] This disclosure relates to the field of infrared imaging detection technology, and more specifically, to a gain-adaptive infrared focal plane readout circuit and control method. Background Technology

[0002] Infrared focal plane imaging systems typically consist of an infrared detector array and a readout integrated circuit. The photocurrent output by the detector varies greatly under different scene brightness conditions: under weak radiation conditions, the output signal amplitude is very small and easily overwhelmed by circuit noise, device mismatch, and quantization errors; while under strong radiation conditions, the output signal amplitude increases significantly, which can cause the pixel integration node voltage to reach the saturation threshold quickly, resulting in problems such as integration distortion, readout clipping, and even pixel overflow interfering with adjacent pixels.

[0003] To achieve stable imaging of the infrared focal plane in complex scenes, the readout link, under traditional fixed integrating capacitor or fixed gain designs, struggles to simultaneously meet the requirements of weak signal sensitivity and strong signal non-saturation. If a smaller integrating capacitor is used to improve both high gain and weak signal resolution, the integrating voltage rises faster under strong light or thermal background conditions, making pixels more prone to saturation and triggering reset, resulting in a shortened effective integration time and limited output dynamic range. If a larger integrating capacitor is used to avoid saturation under strong light conditions, the amplitude of the integrating voltage change decreases under weak signal conditions, reducing the quantization utilization of the column-level ADC, decreasing the quantization accuracy of weak signals, and making it easier to lose details in dark areas of the image.

[0004] Therefore, traditional solutions still suffer from problems such as insufficient accuracy for weak signals, easy saturation for strong signals, quantization faults caused by gain switching, and insufficient ability to suppress halo crosstalk. Summary of the Invention

[0005] This disclosure provides at least one gain-adaptive infrared focal plane readout circuit and control method. By using intra-pixel gain adaptive switching and coarse-fine two-level quantization stitching, the dynamic range is significantly expanded while taking into account weak signal sensitivity, and the risks of saturation distortion and halo crosstalk are reduced, thereby improving the overall signal-to-noise ratio and output stability of infrared focal plane imaging.

[0006] This disclosure provides a gain-adaptive infrared focal plane readout circuit, including a pixel array composed of multiple pixel units arranged in a row and column matrix, and a column-level readout circuit connected to the pixel array in columns. Each pixel unit includes at least: a capacitor transimpedance amplifier module, a variable gain integral capacitor network, a reset trigger module, a counter module, a gain adaptive control logic module, and a signal output stage; The capacitor transimpedance amplifier module is used to integrate the detector output photocurrent and output an integrated voltage; the variable gain integrating capacitor network includes a first integrating capacitor, a second integrating capacitor, and a gain switching switch for controlling the switching state of the second integrating capacitor. The reset trigger module is used to compare the integrated voltage with at least one comparison threshold and generate a reset trigger signal when the condition is met; the counter module is used to count the reset events corresponding to the reset trigger signal within the integration period to form coarse quantization data. The gain adaptive control logic module is connected to the gain switching switch and the counter module, and is used to switch between the first gain mode and the second gain mode according to the counting state; the signal output stage is used to output the residual signal at the end of the integration period. The column-level readout circuit includes a sample-and-hold circuit and a column-level analog-to-digital converter, used to fine-quantize the residual signal and output fine-quantized data. Furthermore, the final pixel data output by the readout circuit is obtained by combining the coarse-quantized data and the fine-quantized data.

[0007] In one optional implementation, the first integrating capacitor is connected between the non-inverting input terminal and the output terminal of the operational amplifier in the capacitor transimpedance amplifier module to form a basic integrating circuit. The second integrating capacitor is connected in parallel with the first integrating capacitor via the gain switching switch, so as to form the total parallel capacitance of the first integrating capacitor and the second integrating capacitor in the second gain mode.

[0008] In one optional implementation, the first gain mode is a high-gain mode that only connects the first integrating capacitor; The second gain mode is a low gain mode in which both the first integrating capacitor and the second integrating capacitor are connected simultaneously. The gain adaptive control logic module performs finite state machine switching based on the overflow bit information of the counter module.

[0009] In one optional implementation, the reset trigger module includes a comparator; The comparator receives the integrated voltage and the reference voltage at its input terminal, and outputs a reset trigger signal when the integrated voltage reaches the comparison threshold to trigger the capacitor transimpedance amplifier module to reset and drive the counter module to count.

[0010] In one optional implementation, the counter module includes at least: A first counter for characterizing the number of resets corresponding to the high-gain mode, a second counter for characterizing the number of resets corresponding to the low-gain mode, and a timing counter for characterizing the reset interval or saturation time; The gain adaptive control logic module determines the light intensity level based on the first counter, the second counter, and the timing counter, and outputs the gain state at the next moment.

[0011] In one optional implementation, the gain adaptive control logic module includes a data decision unit, which receives the reset trigger signal, the overflow bit signal of the counter module and the value of the current gain status register, and determines and outputs the gain status and system reset signal at each clock cycle or reset time.

[0012] In one optional implementation, the data decision unit has at least one of dynamic range expansion logic, sensitivity priority logic, and state maintenance logic; Regarding the dynamic range extension logic, when a reset is triggered in the first gain mode and the counter overflow bit of the counter module indicates strong light, the gain switching switch is closed to allow the circuit to enter the second gain mode and the counter module is reset. Regarding the sensitivity priority logic, when a reset is triggered in the second gain mode and the counter overflow bit of the counter module indicates weak light, the gain switching switch is disconnected to return the circuit to the first gain mode. Regarding the state maintenance logic, the current gain mode is maintained when the counter overflow bit of the counter module indicates that the light intensity is moderate or still strong.

[0013] In one optional implementation, each pixel unit further includes an anti-halo control circuit; The anti-nausea control circuit includes an anti-nausea switch; When the circuit is in the second gain mode and the integrated voltage is detected to reach the saturation threshold within a preset clock cycle, the gain adaptive control logic module controls the anti-corona switch to close, bypassing the photocurrent to the absorption power supply or ground, so as to suppress charge overflow to the adjacent pixel unit.

[0014] In one optional implementation, the coarse quantization data is the count value of the number of complete charge packets during the integration process by the in-pixel counter; The fine quantization data is the quantization code of the residual voltage at the end of integration by the column-level analog-to-digital converter; The final pixel data is the weighted sum of the coarse quantization data shifted left by a preset number of bits and the fine quantization data, wherein the preset number of bits is determined by the ratio between the first integrating capacitor and the sum of the first integrating capacitor and the second integrating capacitor.

[0015] This disclosure also provides a control method for a gain-adaptive infrared focal plane readout circuit, applied to any of the gain-adaptive infrared focal plane readout circuits described in the above embodiments, the method comprising: Perform a global reset on the pixel array and initialize the pixel units to the first gain mode, connecting only the first integrating capacitor; Integrating is initiated, allowing photocurrent to be injected into the first integrating capacitor and forming the integrating voltage; The integral voltage is compared with the comparison threshold. When the integral voltage reaches the comparison threshold, the reset trigger signal is generated to trigger the capacitor transimpedance amplifier module to reset and the counter module to increment its count. When a reset is triggered, the light intensity level is determined based on the counter overflow state or the timer counter state, and adaptively switches between the first gain mode and the second gain mode. When the integration period ends, the counting and integration are stopped and the counter value is latched as the coarse quantization data. The residual voltage at the end of the integration is transmitted to the column-level readout circuit and converted by the column-level analog-to-digital converter to obtain fine quantization data. The coarse quantization data and the fine quantization data are stitched together and corrected according to the gain status flag, and the final image data is output.

[0016] This disclosure also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they execute the steps of the control method for the gain adaptive infrared focal plane readout circuit described above, or any possible implementation of the control method for the gain adaptive infrared focal plane readout circuit described above.

[0017] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the control method of the above-described gain-adaptive infrared focal plane readout circuit, or any possible implementation of the control method of the above-described gain-adaptive infrared focal plane readout circuit.

[0018] This disclosure also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the control method of the above-described gain-adaptive infrared focal plane readout circuit, or the steps in any possible implementation of the control method of the above-described gain-adaptive infrared focal plane readout circuit.

[0019] The present invention discloses a gain-adaptive infrared focal plane readout circuit and control method, which significantly expands the dynamic range while taking into account weak signal sensitivity and reduces the risk of saturation distortion and halo crosstalk, thereby improving the overall signal-to-noise ratio and output stability of infrared focal plane imaging. This is achieved by using intra-pixel gain adaptive switching and coarse-fine two-level quantization stitching.

[0020] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0022] Figure 1 This diagram shows an overall framework of a gain-adaptive infrared focal plane readout circuit provided in an embodiment of the present disclosure. Figure 2 A schematic diagram of the circuit principle of a pixel unit provided in an embodiment of this disclosure is shown; Figure 3 A flowchart is shown showing another control method for a gain-adaptive infrared focal plane readout circuit provided in an embodiment of this disclosure; Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0026] Research has revealed that, to achieve stable imaging of the infrared focal plane in complex scenes, the readout link, under traditional fixed integrating capacitor or fixed gain designs, struggles to simultaneously meet the requirements of weak signal sensitivity and strong signal non-saturation. If a smaller integrating capacitor is used to improve both high gain and weak signal resolution, the integrating voltage rises faster under strong light or thermal background conditions, making pixels more prone to saturation and triggering resets, resulting in a shortened effective integration time and limited output dynamic range. Conversely, if a larger integrating capacitor is used to avoid saturation under strong light conditions, the amplitude of the integrating voltage change decreases under weak signal conditions, reducing the utilization rate of the column-level ADC quantization, lowering the quantization accuracy of weak signals, and making it easier to lose details in dark areas of the image.

[0027] Based on the above research, this disclosure provides a gain-adaptive infrared focal plane readout circuit and control method. By adaptive switching of intra-pixel gain and coarse-fine two-level quantization stitching, the dynamic range is significantly expanded while taking into account the sensitivity of weak signals, and the risks of saturation distortion and halo crosstalk are reduced, thereby improving the overall signal-to-noise ratio and output stability of infrared focal plane imaging.

[0028] To facilitate understanding of this embodiment, a gain-adaptive infrared focal plane readout circuit disclosed in this disclosure will first be described in detail. (See also...) Figure 1 The diagram shown is an overall framework diagram of a gain-adaptive infrared focal plane readout circuit provided in an embodiment of this disclosure.

[0029] like Figure 1 As shown, the overall system architecture of the gain adaptive infrared digital readout circuit provided by the present invention includes a pixel array, a column circuit, a row select circuit, and an encoder and buffer module, and is equipped with a control register and a status register to form a data path from pixel acquisition, row and column addressing, column-level readout to digital output.

[0030] Specifically, the pixel array integrates multiple pixel units arranged in a row-column matrix. It responds to the photocurrent output by the infrared detector to perform operations such as pixel integration, reset triggering, and counting, thereby forming analog residual signals and corresponding pixel digital information for readout at the pixel side. The row direction of the pixel array is addressed and driven by a row selection circuit. Based on the row address, scan mode, and timing control signals issued by the control register, the row selection circuit selects the target row pixels, establishing an electrical connection between the output node of the selected row pixel and the corresponding column circuit, thus enabling row-by-row scanning readout or row-by-row scanning according to a preset strategy.

[0031] Here, the column circuits are connected to the pixel array column by column to perform parallel processing on the output of each column of pixels in the selected pass. The column circuits may include functional modules such as sample-and-hold, column-level amplification, column-level analog-to-digital conversion, and column-level data alignment. They are used to convert the analog residual signals output from the pixel array into column-level digital quantities and to receive and aggregate digital information such as the counting results output from the pixel side for subsequent digital stitching, correction, and formatting processing. By performing parallel processing in the column direction, readout latency can be reduced and system throughput improved while maintaining frame rate.

[0032] Here, the encoding and caching module is connected to the column circuit and is used to encode, package, and manage the pixel digital data output by the column circuit. Encoding processing may include concatenating coarse and fine quantization data, bit width alignment, inserting data validity flags, generating error detection codes, and adapting output protocols; caching processing may include row buffering or frame buffering, data flow control, output bandwidth matching, and burst transmission management. The output of the encoding and caching module is used to output the processed pixel data to an external image processor or main control system in a preset digital interface format.

[0033] Here, the control register and status register are used to configure the system's operating mode and monitor its running status. The control register stores and sends configuration information such as scan mode, integration duration, gain adaptive strategy enablement, threshold parameters, readout timing parameters, and output format parameters; the status register is used to read back the system's current operating status, including row and column scan indication, data output busy / idle status, abnormal / overflow flags, calibration / self-test flags, etc., to achieve closed-loop control and fault diagnosis.

[0034] Among them, the control register and the status register establish configuration and feedback paths with the row selection circuit, the column circuit and the encoding and buffering module, respectively, so that the entire readout circuit can adaptively adjust its working state and stably output digital image data under different scene irradiance.

[0035] Thus, through the above architecture, the present invention achieves the coordination of pixel array, row and column driving and data output path at the system level: the row gating circuit completes row addressing and readout clock control, the column circuit completes column parallel sampling and analog-to-digital conversion, and the encoding and buffering module completes data splicing, encoding and output, thereby providing a reliable hardware foundation for subsequent gain adaptive readout and high dynamic range digital output.

[0036] Next, a detailed description of the circuit of a pixel unit disclosed in the embodiments of this disclosure will be provided, see [link to relevant documentation]. Figure 2 The diagram shown is a schematic diagram of the circuit principle of a pixel unit provided in an embodiment of this disclosure.

[0037] like Figure 2 As shown, the pixel unit includes at least: a capacitor transimpedance amplifier module, a variable gain integral capacitor network, a reset trigger module, a counter module, a gain adaptive control logic module, and a signal output stage.

[0038] Specifically, the capacitor transimpedance amplifier module is used to integrate the detector output photocurrent and output an integrated voltage; the variable gain integrating capacitor network includes a first integrating capacitor C. int1 Second integrating capacitor C int2 and the second integrating capacitor C int2 Gain switching switch S1 in switch state.

[0039] Here, the first integrating capacitor C int1 The basic integrating circuit is formed between the non-inverting input and output terminals of the operational amplifier in the capacitor transimpedance amplifier module; the second integrating capacitor C int2 The first integrating capacitor C via the gain switching switch int1 Parallel connection to form the first integrating capacitor C in the second gain mode. int1 With the second integrating capacitor C int2 The total parallel capacitance.

[0040] In practical implementation, the transimpedance amplifier module is used to perform the integral conversion of the detector current signal to a voltage signal. The detector outputs a photocurrent under incident infrared radiation, which is injected into the input terminal of the transimpedance amplifier module. Under the negative feedback of the operational amplifier, the input node potential is stabilized near a preset reference potential, thereby suppressing the nonlinear effects of the input node voltage changing with the photocurrent. The cumulative effect of the photocurrent is transferred to the feedback integration branch to output a time-varying integrated voltage signal V. out .

[0041] Wherein, the integral voltage V outThe rising or falling trend is consistent with the direction of the detector photocurrent, and its rate of change is inversely proportional to the size of the equivalent integral capacitance, providing a simulation reference for subsequent reset triggering, coarse counting quantization, and column-level residual sampling.

[0042] Here, a variable gain integral capacitor network is positioned in the integral feedback path of the capacitor-transimpedance amplifier module. This network is used to dynamically configure the pixel gain by changing the equivalent integral capacitor without altering the detector or integration timing. The variable gain integral capacitor network includes a first integral capacitor C. int1 Second integrating capacitor C int2 And gain switching switch S1.

[0043] Among them, the first integrating capacitor C int1 As a basic integrating capacitor, it is connected between the output terminal and the inverting input terminal of the operational amplifier to form a basic integrating circuit, so that the pixel can perform integration readout with a high current-to-voltage conversion gain in the default state, thereby ensuring that the variation of the integrated voltage is large enough under low light conditions and improving the quantization resolution in dark and low-irradiance scenes.

[0044] Here, the second integrating capacitor C int2 The gain is adaptively switched by selectively connecting the basic integrator circuit through the gain switching switch S1. Specifically, the second integrator C... int2 One end of the capacitor is connected to the output of the operational amplifier, and the other end is connected to the inverting input of the operational amplifier via a gain switching switch S1, so that when S1 is closed, the second integrating capacitor C... int2 With the first integrating capacitor C int1 They form a parallel relationship, resulting in an equivalent integral capacitance of C. int1 +C int2 The total parallel capacitance; when S1 is open, the second integrating capacitor C int2 Bypassing the feedback path, the integrating circuit consists only of the first integrating capacitor C. int1 Provide a feedback capacitor.

[0045] Based on the above structure, the pixel unit can switch between two gain modes: when S1 is disconnected and only C is connected. int1 When S1 is closed and C is connected, the pixel operates in the first gain mode (high gain mode), which is characterized by a small equivalent integrating capacitance and a fast rate of change of integrating voltage, making it suitable for low light or low signal scenarios; int1 +C int2 When the pixel operates in the second gain mode (low gain mode), it is characterized by an increase in the equivalent integrating capacitance and a decrease in the amplitude of the integral voltage change caused by a unit photocurrent, thereby delaying the time for the integrating node to reach the saturation threshold, increasing the available integration time under strong light conditions and expanding the dynamic range.

[0046] Specifically, the reset trigger module is used to compare the integral voltage with at least one comparison threshold and generate a reset trigger signal when the condition is met; the counter module is used to count the reset events corresponding to the reset trigger signal within the integration period to form coarse quantization data.

[0047] Here, the reset trigger module includes a comparator. The input of the comparator receives the integrated voltage V. out With reference voltage V ref2 And in the integral voltage V out When the comparison threshold is reached, a reset trigger signal EN is output to trigger the capacitor transimpedance amplifier module to reset and drive the counter module to count. The counter module includes at least: a first counter (Low Gain 10-bit Counter) to characterize the number of resets corresponding to the high gain mode, a second counter (High Gain 10-bit Counter) to characterize the number of resets corresponding to the low gain mode, and a timing counter (5-bit Counter) to characterize the reset interval or saturation time. The gain adaptive control logic module determines the light intensity level based on the first counter (Low Gain 10-bit Counter), the second counter (High Gain 10-bit Counter), and the timing counter (5-bit Counter) and outputs the gain state for the next moment.

[0048] In a specific implementation, the reset trigger module includes a comparator. The inputs of the comparator receive the integral voltage Vout and the reference voltage Vref2, respectively. When the integral voltage Vout rises and reaches or exceeds the comparison threshold set by the reference voltage Vref2, the comparator outputs a reset trigger signal EN. The reset trigger signal EN serves two purposes: firstly, it triggers the capacitor-transimpedance amplifier module to perform a reset operation, returning the integral feedback branch to its initial state to begin the next integral accumulation; secondly, it serves as a counting event input to drive the counter module to update the count value, thus equating the process of reaching the threshold and resetting to counting the number of complete charge packets.

[0049] Here, the counter module includes at least: a first counter, a second counter, and a timing counter. The first counter is a low-gain 10-bit counter, used to count the number of resets corresponding to the reset trigger signal EN when the pixel is in low-gain mode; the second counter is a high-gain 10-bit counter, used to count the number of resets corresponding to the reset trigger signal EN when the pixel is in high-gain mode; the timing counter is a 5-bit counter, used to time the time interval between two adjacent reset triggers, or to characterize the time characteristic of the integration node reaching the saturation threshold within a certain clock window, providing auxiliary criteria related to the reset frequency.

[0050] Furthermore, the gain adaptive control logic module is connected to the first counter (Low Gain 10-bit Counter), the second counter (High Gain 10-bit Counter), and the timer counter (5-bit Counter) to determine the current counting state at each reset trigger or each clock cycle: when the reset trigger frequency is high and the timer counter indicates a short reset interval, it is determined to be a strong light level and the gain state for the next moment is output to switch to low gain mode, thereby increasing the equivalent integration capacitance and delaying integration saturation; when the reset trigger frequency is low and the timer counter indicates a long reset interval, it is determined to be a weak light level and the gain state for the next moment is output to switch to high gain mode, thereby improving the amplitude of weak signal integration voltage change and quantization resolution; in the case of intermediate values, the current gain mode is maintained to avoid frequent gain state jitter. Through the above-mentioned reset trigger-counting-decision-switching closed-loop control, pixel-level dynamic range expansion and adaptive readout can be achieved without increasing column-level readout complexity.

[0051] Specifically, the gain adaptive control logic module, connected to the gain switching switch S1 and the counter module, is used to switch between the first gain mode and the second gain mode based on the counting state; the signal output stage is used to output the residual signal at the end of the integration period. The column-level readout circuit includes a sample and hold circuit and a column-level analog-to-digital converter (ADC) for fine-quantizing the residual signal and outputting fine-quantized data. Furthermore, the final pixel data output by the readout circuit is obtained by combining the coarse-quantized data and the fine-quantized data.

[0052] Here, the gain adaptive control logic module includes a data judgement, which receives a reset trigger signal, the overflow bit signals (Co1, Co2) from the counter module, and the current gain status register S. n The value of S is determined at each clock cycle or reset time, and the gain state S for the next time step is output. n+1 And the system reset signal Rst.

[0053] In practical implementation, the gain adaptive control logic module is signal-connected to the gain switching switch S1 and the counter module. It is used to achieve closed-loop adaptive switching of the gain based on the counting state during pixel integration readout, thereby dynamically switching the pixel between the first gain mode and the second gain mode. Through this adaptive switching mechanism, when a strong input photocurrent is detected and the integration voltage rises too quickly, it can automatically switch to a low-gain mode to expand the usable integration range; when a weak input photocurrent is detected and the reset trigger is sparse, it can automatically switch to a high-gain mode to improve weak signal resolution. The signal output stage is used to output a residual signal at the end of an integration cycle. The residual signal is the residual voltage of the integration node at the moment of integration end or its corresponding analog output quantity, used to provide fine-grained information beyond charge packet counting.

[0054] Here, the column-level readout circuit is connected to the pixel array column by column. The column-level readout circuit includes a sample-and-hold circuit and a column-level analog-to-digital converter (ADC). The sample-and-hold circuit samples and holds the residual signal at the end of the integration period to prevent the residual signal from changing due to timing disturbances such as pixel reset and row gating switching during subsequent readout and conversion. The column-level ADC performs analog-to-digital conversion on the sample-and-hold residual signal to obtain refined data.

[0055] Ultimately, the final pixel data output by the readout circuit is obtained by combining the coarse quantization data output by the in-pixel counter module and the fine quantization data output by the column-level analog-to-digital converter, thereby achieving both wide dynamic range and high quantization accuracy without significantly increasing the pixel area.

[0056] In this embodiment, the gain adaptive control logic module includes a data judgement and a gain status register. The input of the data judgement receives at least a reset trigger signal, overflow bit signals Co1 and Co2 from the counter module, and the current gain status register S. n The data decision unit performs a logical decision on the above inputs at each clock cycle or at the reset trigger time, and outputs the gain state S for the next time step. n+1Based on this, the gain switching switch S1 is turned on or off to achieve the switching from high gain mode to low gain mode, or from low gain mode to high gain mode.

[0057] Meanwhile, the data decision unit also outputs a system reset signal Rst, which is used to synchronously reset and clear the counter module and / or related registers in scenarios such as gain switching, counter overflow, or state update, so as to ensure clear boundaries of counting results in different gain modes, avoid cross-mode counting aliasing, and improve the reliability of coarse and fine quantization splicing and subsequent data processing.

[0058] In specific implementation, the data decision unit possesses at least one of the following: dynamic range extension logic, sensitivity priority logic, and state maintenance logic. Regarding the dynamic range extension logic, when a reset is triggered in the first gain mode and the counter overflow bit of the counter module indicates strong light, the gain switching switch is closed to allow the circuit to enter the second gain mode, and the counter module is reset. Regarding the sensitivity priority logic, when a reset is triggered in the second gain mode and the counter overflow bit of the counter module indicates weak light, the gain switching switch is opened to allow the circuit to return to the first gain mode. Regarding the state maintenance logic, the current gain mode is maintained when the counter overflow bit of the counter module indicates moderate or still strong light intensity.

[0059] Here, the data decision unit is used to implement the core decision logic for adaptive gain switching. It can have at least one of dynamic range extension logic, sensitivity priority logic, and state maintenance logic, or multiple logics simultaneously and executed in a preset priority combination. Based on the reset trigger signal, the overflow bit signals Co1 and Co2 of the counter module, and the state value of the current gain state register Sn, the data decision unit determines the current light intensity level at each clock cycle or reset trigger moment, and outputs the gain state Sn+1 for the next moment and the corresponding control signal, thereby driving the gain switching switch to complete the gain mode switching or maintenance.

[0060] Regarding the dynamic range extension logic, when a pixel is in the first gain mode (high gain mode), the integrated voltage is more likely to reach the comparison threshold and trigger a reset in a shorter time. In this mode, if the data decision unit detects a reset trigger and the counter overflow bit of the counter module indicates that the current input is a strong light level (e.g., the reset trigger frequency is too high, the count value reaches the upper limit, or the overflow bit is a preset strong light combination state), then it is determined that the current gain configuration is insufficient to cover the input dynamic range.

[0061] At this point, the data decision unit controls the closed gain switching switch, causing the second integrating capacitor to be engaged in the integration feedback path, thereby switching the circuit to the second gain mode (low gain mode). This increases the equivalent integrating capacitor to reduce the rate of change of the integrating voltage, delay saturation, and expand the measurable dynamic range. Simultaneously, to avoid cross-mode aliasing of counts before and after gain switching, the data decision unit outputs a system reset signal to reset or clear the counter module, allowing subsequent counts to restart accumulation in the new gain mode, thus ensuring clear mode boundaries for the coarse quantization data.

[0062] For the sensitivity-priority logic, when a pixel is in the second gain mode (low gain mode), the increase in the equivalent integrating capacitance leads to a decrease in the amplitude of the integrated voltage change per unit photocurrent. If the data decision unit detects a reset trigger and the counter overflow bit of the counter module indicates that the current input is a weak light level (e.g., sparse reset triggers, a long reset interval indicated by the timer counter, or a preset weak light combination of overflow bits), it determines that maintaining the low gain mode will reduce the quantization resolution capability of weak signals.

[0063] At this point, the data decision controller disconnects the gain switching switch, causing the second integrating capacitor to bypass the integrating feedback path, thereby returning the circuit to the first gain mode (high gain mode) to improve the amplitude of the integrating voltage change and enhance the output sensitivity and quantization accuracy under low light conditions.

[0064] Regarding the state maintenance logic, when the data decision unit determines that the light intensity level indicated by the counter overflow bit of the counter module is moderate or still in strong light but has not reached the switching threshold, the data decision unit maintains the current gain state register S. n Keep it unchanged and output the corresponding S. n+1 =S n This keeps the gain switching switch in its current on or off state to avoid frequent gain mode jitter under light fluctuations or noise disturbances.

[0065] In this way, by introducing state maintenance logic, the stability of gain adaptive control can be improved, and the statistical consistency between coarse quantization count and fine quantization residual within the same gain range can be guaranteed, which is beneficial for the subsequent combination and correction of coarse and fine quantization data.

[0066] For example, in a scenario where a pixel is initially in high-gain mode (S1=0) and suddenly encounters strong light (such as scanning a hot object), Cint1 is instantly filled. Before the timer counter can even count, the comparator flips. It determines that S1=0 and Co1=0, Co2=0 (meaning a reset occurs in a very short time), at which point S... n+1←1 (Switch to low gain); Rst←1 (Reset counter). In scenarios with moderate lighting suitable for integration with small capacitors, the reset occurs within a reasonable time interval, determining S1=0 and Co1=1 (normal counter carry). At this time, S... n+1 ←0 (maintain high gain). In scenes gazing into deep space or against a dark background, the comparator doesn't flip for a long time during integration. S1 is set to 0, and neither Co1 nor Co2 overflows, allowing the timer counter to accumulate for an extended period. At this point, S... n +1 ←0 (maintaining high gain, the circuit behavior degenerates into traditional long-time integration). In scenarios with direct sunlight or laser blinding, even when switching to a large capacitor (S1=1), the comparator still flips instantly, determining S1=1 and Co1=0, Co2=0 (the large capacitor also fills instantly), at which point Sn+1←1 (maintaining low gain), and simultaneously closing the anti-corona switch. This is to prevent excessive photocurrent from burning out the capacitor transimpedance amplifier module op-amp or causing charge diffusion to the substrate, resulting in a corona. In scenarios observing high-temperature targets with stable light intensity, in large capacitor mode, the reset frequency is normal, determining S1=1 and Co1 has a normal carry, S... n+1 ←1 (Maintain low gain). In a scene where the high-temperature target moves out of the field of view and the background darkens, in low gain mode, if the comparator does not flip after a long time, it determines that S1=1 and the timer / counter overflows or Co2 remains unchanged for a long time. At this time, S... n+1 ←0 (Switch back to high gain).

[0067] As one possible implementation, each pixel unit also includes an anti-blooming control circuit; the anti-blooming control circuit includes an anti-blooming switch; when the circuit is in the second gain mode and the integrated voltage is detected to reach the saturation threshold within a preset clock cycle, the gain adaptive control logic module controls the closing of the anti-blooming switch to bypass the photocurrent to the absorption power supply or ground, so as to suppress charge overflow to adjacent pixel units.

[0068] It should be noted that the coarse quantization data is the count value of the number of complete charge packets during the integration process by the in-pixel counter; the fine quantization data is the quantization code of the residual voltage at the end of integration by the column-level analog-to-digital converter; the final pixel data is the weighted sum of the coarse quantization data shifted left by a preset number of bits and the fine quantization data, wherein the preset number of bits is determined by the ratio between the first integrating capacitor and the sum of the first integrating capacitor and the second integrating capacitor.

[0069] Specifically, coarse quantization is performed within a pixel. The counter value represents N full-scale charge packets (Q... max Because the counter bit depth can reach 10 bits or more, and the gain is variable, this step provides a huge dynamic range extension (up to 2). 15(Multiple reference range). Fine quantization is performed at the column level. At the end of integration, the analog voltage remaining on the capacitor, which is less than one full scale, is sampled and held, and quantized by a high-precision (e.g., 12-bit) column-level ADC.

[0070] Based on the same inventive concept, this disclosure also provides a control method for a gain-adaptive infrared focal plane readout circuit.

[0071] See Figure 3 The diagram shows a flowchart of a control method for a gain-adaptive infrared focal plane readout circuit provided in an embodiment of this disclosure. The method includes steps S101 to S105, wherein: S101. Perform a global reset on the pixel array and initialize the pixel unit to the first gain mode, connecting only the first integrating capacitor.

[0072] S102. Start integration, so that photocurrent is injected into the first integrating capacitor and the integrating voltage is formed; compare the integrating voltage with the comparison threshold, and when the integrating voltage reaches the comparison threshold, generate the reset trigger signal to trigger the capacitor transimpedance amplifier module to reset, and increment the count of the counter module.

[0073] S103. When a reset is triggered, the light intensity level is determined based on the counter overflow state or the timer counter state, and the light intensity level is adaptively switched between the first gain mode and the second gain mode.

[0074] S104. When the integration period ends, stop counting and integration and latch the counter value as the coarse quantization data. Transmit the residual voltage at the end of integration to the column-level readout circuit and convert it into fine quantization data through the column-level analog-to-digital converter.

[0075] S105. Based on the gain status flag, the coarse quantization data and the fine quantization data are spliced ​​and corrected to output the final image data.

[0076] In practical implementation, the control method of the gain-adaptive infrared focal plane readout circuit is used to complete the combined output of pixel integration, reset trigger counting, gain adaptive switching, and coarse / fine quantization data within one integration cycle. This method can be executed collaboratively by the row and column driving timing and the intra-pixel gain adaptive control logic module, as detailed below.

[0077] First, a global reset is performed on the pixel array to restore the integration node voltage of each pixel unit to a preset initial level, and to clear or initialize the digital states such as the pixel counter and gain status register; simultaneously, the pixel unit is initialized to the first gain mode, that is, the control gain switching switch is in the off state, and only the first integration capacitor C is connected. int1The pixel participates in integration, thus enabling it to enter the integration preparation state with a higher current-to-voltage conversion gain. Through the aforementioned global reset and gain initialization, it is ensured that the starting conditions of each pixel are consistent, avoiding the influence of residual charge and historical states on subsequent integration results.

[0078] Integration is then initiated. Within the integration window, the photocurrent output by the detector is continuously injected into the first integrating capacitor, and under the integration feedback of the capacitor transimpedance amplifier module, an integrating voltage V that varies with time is formed. out The rate of change of the integrated voltage is determined by both the input photocurrent and the current equivalent integrating capacitance. Under low light conditions, V out The change is relatively slow, under strong light conditions V out It rises even faster.

[0079] During the integration process, the reset trigger module triggers the integration voltage V. out Comparison threshold (given by reference voltage V) ref2 (Settings) to perform real-time comparisons; when V out When the comparison threshold is reached or exceeded, the comparator outputs a reset trigger signal EN. The reset trigger signal EN triggers the capacitor transimpedance amplifier module to reset the integrator branch, so that the integrator node returns to its initial state and begins the next charge accumulation; on the other hand, it serves as a counting event input, causing the counter module to incrementally update its count value, thereby equating the process of reaching the threshold and resetting to counting the number of complete charge packets, forming coarse quantization information within the pixel.

[0080] Upon each reset trigger or within a preset clock cycle, the gain adaptive control logic module determines the current light intensity level based on the counter overflow state (e.g., overflow bits Co1 and Co2 of the high / low gain counter) or the timing state of the timer counter (used to characterize the reset interval or saturation time), and performs adaptive switching between the first gain mode and the second gain mode: when the light intensity level is determined to be strong, the gain switching switch is closed, causing the second integrating capacitor to be input into the integrating feedback path to enter the second gain mode (low gain mode), thereby reducing the rate of change of the integrating voltage, delaying saturation, and expanding the dynamic range by increasing the equivalent integrating capacitor; when the light intensity level is determined to be weak, the gain switching switch is opened to return to the first gain mode (high gain mode), thereby increasing the amplitude of the integrating voltage change under weak signal conditions and improving the quantization resolution; when the light intensity is moderate or the switching conditions are not met, the current gain state is maintained to avoid gain jitter and maintain the consistency of counting statistics.

[0081] When the integration cycle ends, counting and integration operations are stopped, and the count value of the counter module is latched as coarse quantization data. Simultaneously, the residual voltage at the end of integration (i.e., the remaining integrated voltage that did not reach the threshold after the last reset, or its corresponding analog residual signal) is transmitted to the column-level readout circuit through the signal output stage. The sample-and-hold circuit samples and holds the residual signal, and then the column-level analog-to-digital converter converts the residual signal into fine quantization data. Thus, within one integration cycle, both high-order coarse quantization information formed by pixel-level counting and low-order fine quantization information formed by the column-level ADC are obtained simultaneously.

[0082] Finally, the coarse quantization data and the fine quantization data are concatenated and corrected according to the gain status flag to obtain the final image data output. Specifically, the coarse quantization count can be shifted or weighted according to the equivalent integral capacitance relationship corresponding to the current gain mode, and combined with the fine quantization residual, thereby maintaining numerical continuity in different gain intervals, reducing quantization gaps at gain switching points, and improving the overall dynamic range and output accuracy.

[0083] The present invention discloses a gain-adaptive infrared focal plane readout circuit and control method, which significantly expands the dynamic range while taking into account weak signal sensitivity and reduces the risk of saturation distortion and halo crosstalk, thereby improving the overall signal-to-noise ratio and output stability of infrared focal plane imaging. This is achieved by using intra-pixel gain adaptive switching and coarse-fine two-level quantization stitching.

[0084] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0085] Corresponding to Figure 3 The present disclosure also provides an electronic device 400, such as a control method for a gain-adaptive infrared focal plane readout circuit. Figure 4 The diagram shown is a structural schematic of an electronic device 400 provided in an embodiment of this disclosure, including: Processor 41, memory 42, and bus 43; memory 42 is used to store execution instructions, including main memory 421 and external memory 422; the main memory 421, also called internal memory, is used to temporarily store the computational data in processor 41, as well as the data exchanged with external memory 422 such as hard disk. Processor 41 exchanges data with external memory 422 through main memory 421. When the electronic device 400 is running, processor 41 and memory 42 communicate through bus 43, enabling processor 41 to execute... Figure 3 The steps of the control method for the gain-adaptive infrared focal plane readout circuit.

[0086] This disclosure also provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program performs the steps of the control method for the gain-adaptive infrared focal plane readout circuit described in the above-described method embodiments. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0087] This disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, they can perform the steps of the control method for the gain adaptive infrared focal plane readout circuit described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0088] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0089] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this disclosure, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0090] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0091] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0092] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0093] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A gain-adaptive infrared focal plane readout circuit, characterized in that, It includes a pixel array consisting of multiple pixel units arranged in a row and column matrix, and a column-level readout circuit connected to the pixel array column by column; Each pixel unit includes at least: a capacitor transimpedance amplifier module, a variable gain integral capacitor network, a reset trigger module, a counter module, a gain adaptive control logic module, and a signal output stage; The capacitor transimpedance amplifier module is used to integrate the detector output photocurrent and output an integrated voltage; the variable gain integrating capacitor network includes a first integrating capacitor, a second integrating capacitor, and a gain switching switch for controlling the switching state of the second integrating capacitor. The reset trigger module is used to compare the integrated voltage with at least one comparison threshold and generate a reset trigger signal when the condition is met; the counter module is used to count the reset events corresponding to the reset trigger signal within the integration period to form coarse quantization data. The gain adaptive control logic module is connected to the gain switching switch and the counter module, and is used to switch between the first gain mode and the second gain mode according to the counting state; the signal output stage is used to output the residual signal at the end of the integration period. The first gain mode is a high-gain mode that only connects the first integrating capacitor; the second gain mode is a low-gain mode that connects both the first integrating capacitor and the second integrating capacitor; the gain adaptive control logic module performs finite state machine switching based on the overflow bit information of the counter module. The gain adaptive control logic module includes a data decision unit and a gain status register. The input of the data decision unit receives at least the reset trigger signal, the overflow bit signal of the counter module, and the current status value of the gain status register. At each clock cycle or reset time, it determines and outputs the gain status of the next time moment and the system reset signal. Based on the gain status of the next time moment, it controls the conduction or deactivation of the gain switching switch to realize the switching from high gain mode to low gain mode or from low gain mode to high gain mode. The data decision unit also outputs a system reset signal, which is used to synchronously reset and clear the counter module and / or related registers in scenarios such as gain switching, counter overflow or status update, so as to ensure clear boundaries of counting results in different gain modes and avoid cross-mode aliasing of counting. The column-level readout circuit includes a sample-and-hold circuit and a column-level analog-to-digital converter, used to fine-quantize the residual signal and output fine-quantized data. Furthermore, the final pixel data output by the readout circuit is obtained by combining the coarse-quantized data and the fine-quantized data.

2. The gain-adaptive infrared focal plane readout circuit according to claim 1, characterized in that: The first integrating capacitor is connected between the non-inverting input terminal and the output terminal of the operational amplifier in the capacitor transimpedance amplifier module to form a basic integrating circuit. The second integrating capacitor is connected in parallel with the first integrating capacitor via the gain switching switch, so as to form the total parallel capacitance of the first integrating capacitor and the second integrating capacitor in the second gain mode.

3. The gain-adaptive infrared focal plane readout circuit according to claim 1, characterized in that, The reset trigger module includes a comparator; The comparator receives the integrated voltage and the reference voltage at its input terminal, and outputs a reset trigger signal when the integrated voltage reaches the comparison threshold to trigger the capacitor transimpedance amplifier module to reset and drive the counter module to count.

4. The gain-adaptive infrared focal plane readout circuit according to claim 1, characterized in that, The counter module includes at least: A first counter for characterizing the number of resets corresponding to the high-gain mode, a second counter for characterizing the number of resets corresponding to the low-gain mode, and a timing counter for characterizing the reset interval or saturation time; The gain adaptive control logic module determines the light intensity level based on the first counter, the second counter, and the timing counter, and outputs the gain state at the next moment.

5. The gain-adaptive infrared focal plane readout circuit according to claim 1, characterized in that, The data decision unit has at least one of dynamic range expansion logic, sensitivity priority logic, and state maintenance logic. Regarding the dynamic range extension logic, when a reset is triggered in the first gain mode and the counter overflow bit of the counter module indicates strong light, the gain switching switch is closed to allow the circuit to enter the second gain mode and the counter module is reset. Regarding the sensitivity priority logic, when a reset is triggered in the second gain mode and the counter overflow bit of the counter module indicates weak light, the gain switching switch is disconnected to return the circuit to the first gain mode. Regarding the state maintenance logic, the current gain mode is maintained when the counter overflow bit of the counter module indicates that the light intensity is moderate or still strong.

6. The gain-adaptive infrared focal plane readout circuit according to claim 1, characterized in that, Each pixel unit further includes an anti-halo control circuit; The anti-nausea control circuit includes an anti-nausea switch; When the circuit is in the second gain mode and the integrated voltage is detected to reach the saturation threshold within a preset clock cycle, the gain adaptive control logic module controls the closing of the anti-corona switch to bypass the photocurrent to the absorption power supply or ground, so as to suppress charge overflow to the adjacent pixel unit.

7. The gain-adaptive infrared focal plane readout circuit according to claim 1, characterized in that: The coarse quantization data is the count value of the number of complete charge packets during the integration process by the in-pixel counter. The fine quantization data is the quantization code of the residual voltage at the end of integration by the column-level analog-to-digital converter; The final pixel data is the weighted sum of the coarse quantization data shifted left by a preset number of bits and the fine quantization data, wherein the preset number of bits is determined by the ratio between the first integrating capacitor and the sum of the first integrating capacitor and the second integrating capacitor.

8. A control method for a gain-adaptive infrared focal plane readout circuit, characterized in that, The method, applied to the gain-adaptive infrared focal plane readout circuit as described in any one of claims 1-7, comprises: Perform a global reset on the pixel array and initialize the pixel units to the first gain mode, connecting only the first integrating capacitor; Integrating is initiated, allowing photocurrent to be injected into the first integrating capacitor and forming the integrating voltage; The integral voltage is compared with the comparison threshold. When the integral voltage reaches the comparison threshold, the reset trigger signal is generated to trigger the capacitor transimpedance amplifier module to reset and the counter module to increment its count. When a reset is triggered, the light intensity level is determined based on the counter overflow state or the timer counter state, and adaptively switches between the first gain mode and the second gain mode. When the integration period ends, the counting and integration are stopped and the counter value is latched as the coarse quantization data. The residual voltage at the end of the integration is transmitted to the column-level readout circuit and converted by the column-level analog-to-digital converter to obtain fine quantization data. The coarse quantization data and the fine quantization data are stitched together and corrected according to the gain status flag, and the final image data is output.

Images