Semiconductor structure and method of forming the same, electronic device

Abstract

Embodiments of the present application provide a semiconductor structure, a forming method thereof and an electronic device; the semiconductor structure comprises a substrate, a plurality of capacitor structures and a plurality of support structures; the substrate comprises a first region and a second region adjacent along a first direction; the plurality of capacitor structures are located on the first region, extend along the first direction and are arranged in an array along a second direction and a third direction; the capacitor structure comprises a first electrode; the first electrode is a cylindrical structure with an opening facing away from the second region; the plurality of support structures are respectively located between outer end portions of the first electrodes adjacent along the third direction; the outer end portions are end portions away from the second region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same, and an electronic device. Background Technology

[0002] With the increasing demands for integration and storage capacity in various electronic devices, three-dimensional (3D) stacked semiconductor structures have emerged. Because the capacitor structure in a semiconductor structure extends laterally, it is prone to bending or collapse.

[0003] In related technologies, in order to ensure the stability of the capacitor structure, although the lower electrode of the capacitor structure can be supported by wrapping it with a support structure, the support structure will compress the space of the lower electrode, resulting in a reduction in the effective capacitance of the capacitor structure, thereby affecting the fabrication yield and performance of the semiconductor structure. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same.

[0005] In a first aspect, this application provides a semiconductor structure, comprising: The substrate includes a first region and a second region adjacent to each other along a first direction; Multiple capacitor structures are located on the first region, extending along the first direction and arranged in an array along the second and third directions; each capacitor structure includes a first electrode, which is a cylindrical shape with its opening facing away from the second region. Multiple support structures are respectively located between the outer ends of adjacent first electrodes along the third direction; the outer ends are the ends away from the second region; Wherein, the first direction and the second direction intersect and are parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

[0006] In some embodiments, the dimension of the first electrode along the second direction is greater than the dimension of the support structure along the second direction.

[0007] In some embodiments, the dimension of the middle portion of the first electrode along the third direction is greater than the dimension of the outer end portion of the first electrode along the third direction.

[0008] In some embodiments, the capacitor structure further includes: The dielectric layer and the second electrode are located, sequentially, on the inner surface of the first electrode and the outer surface of the middle portion of the first electrode.

[0009] In some embodiments, the second electrodes of the plurality of capacitor structures arranged along the third direction are an integrally connected structure; or... The second electrodes of the plurality of capacitor structures arranged along the third direction and the second direction are interconnected as an integral structure.

[0010] In some embodiments, the outer end of the first electrode does not extend beyond the support structure in the first direction.

[0011] In some embodiments, the semiconductor structure further includes: Multiple transistors are located on the second region, extending along the first direction and arranged in an array along the second direction and the third direction; the source of each transistor is electrically connected to the first electrode of the corresponding capacitor structure. Multiple bit line structures are arranged along the second direction and extend along the third direction; the multiple bit line structures are respectively electrically connected to the drains of multiple transistors arranged along the third direction.

[0012] Secondly, this application also provides a method for forming a semiconductor structure, comprising: A substrate is provided, the substrate comprising a first region and a second region adjacent to each other along a first direction; In the first region, multiple support structures are formed in an array arranged along the second and third directions; Between two adjacent support structures along the third direction, a capacitor structure is formed on the first region and extending along the first direction; the capacitor structure includes a first electrode, which is a cylindrical shape with its opening facing away from the second region, and the support structure is located at the outer end of the first electrode; the outer end is the end away from the second region; Wherein, the first direction and the second direction intersect and are parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

[0013] In some embodiments, after providing the substrate, the method includes: A stacked structure is formed on the substrate; the stacked structure includes a plurality of semiconductor pillars extending along the first direction and arranged in an array along the second direction and the third direction, and a first sacrificial structure surrounding a first portion of the semiconductor pillars; the first portion is located in the first region; The first sacrificial structure is etched to form a first etched groove extending along the third direction; the first etched groove is located at the outer end of the semiconductor pillar; A second sacrificial structure is formed in the first etched groove, and the second sacrificial structure contacts the outer end of the semiconductor pillar.

[0014] In some embodiments, before forming the second sacrificial structure, the method further includes: The first sacrificial structure is etched laterally, such that the first etched groove extends between the third-direction adjacent semiconductor pillars.

[0015] In some embodiments, the stacked structure has a second etched groove adjacent to the first region; the support structure is formed by the following steps: Based on the second etched groove, a portion of the first sacrificial structure is etched laterally to form a first lateral groove; the first lateral groove is located between adjacent second sacrificial structures along the second direction; The support structure is formed in the first transverse groove.

[0016] In some embodiments, after forming the support structure, the method further includes: Based on the second etched groove, the second sacrificial structure is removed, exposing the first etched groove; A third sacrificial structure is formed in the first etched groove; the third sacrificial structure is made of the same material as the first sacrificial structure. The etching selectivity ratio of the support structure to any one of the first sacrificial structure, the second sacrificial structure, and the third sacrificial structure is less than 1:2.

[0017] In some embodiments, the capacitor structure is formed by the following steps: Based on the second etched groove, the first portion of the semiconductor pillar is removed to form a second transverse groove; The first electrode is formed in the second transverse groove; Remove the first sacrificial structure and the third sacrificial structure to expose the two side surfaces of the first electrode and the outer surface of the middle part of the first electrode; A dielectric layer and a second electrode are sequentially formed on the inner and outer surfaces exposed by the first electrode.

[0018] In some embodiments, the dimension of the second transverse groove along the second direction is larger than the dimension of the support structure along the second direction; and / or, The middle part of the second transverse groove is larger in the third direction than the outer end of the second transverse groove.

[0019] In some embodiments, before forming the capacitor structure extending along the first direction, the method further includes: In the second region, a plurality of transistors are formed extending along the first direction and arranged in an array along the second direction and the third direction; the source of the transistor is electrically connected to the first electrode of the corresponding capacitor structure; A plurality of bit line structures are formed, arranged along the second direction and extending along the third direction; the bit line structures are electrically connected to the drains of a plurality of transistors arranged along the third direction.

[0020] Thirdly, this application also provides an electronic device, comprising: processor; A memory coupled to the processor, wherein the memory includes the semiconductor structure described in any of the preceding embodiments.

[0021] This application provides a semiconductor structure and its formation method, and an electronic device; wherein, the semiconductor structure includes: a substrate, a plurality of capacitor structures and a plurality of support structures, the substrate including a first region and a second region adjacent along a first direction; the plurality of capacitor structures are located on the first region, extending along the first direction and arranged in an array along a second direction and a third direction; the capacitor structure includes a first electrode, the first electrode being a cylindrical shape with its opening facing away from the second region; the plurality of support structures are respectively located between the outer ends of the first electrode adjacent along the third direction, the outer ends being the ends away from the second region.

[0022] In this embodiment, by placing the support structure between the outer ends of adjacent first electrodes along a third direction, not only can stable mechanical support be provided at the outer ends of the first electrodes, but also the non-end positions of the first electrodes can form a double-sided capacitor. In this way, the capacitance of the capacitor structure is increased while preventing the first electrodes (i.e., the capacitor structure) from bending and deforming. Attached Figure Description

[0023] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0024] Figure 1 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 1 ; Figure 2 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 2 ; Figure 3 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 3 ; Figure 4Schematic diagram of the capacitor structure and support structure provided in the embodiments of this application Figure 1 ; Figure 5 Schematic diagram of the capacitor structure and support structure provided in the embodiments of this application Figure 2 ; Figure 6 Schematic diagram of the capacitor structure and support structure provided in the embodiments of this application Figure 3 ; Figure 7 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 4 ; Figure 8 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 5 ; Figure 9 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this application; Figure 10 This application provides a schematic diagram of the semiconductor structure formation process. Figure 1 ; Figure 11 This application provides a schematic diagram of the semiconductor structure formation process. Figure 2 ; Figure 12 This application provides a schematic diagram of the semiconductor structure formation process. Figure 3 ; Figure 13 This application provides a schematic diagram of the semiconductor structure formation process. Figure 4 ; Figure 14 This application provides a schematic diagram of the semiconductor structure formation process. Figure 5 ; Figure 15 This application provides a schematic diagram of the semiconductor structure formation process. Figure 6 ; Figure 16 This application provides a schematic diagram of the semiconductor structure formation process. Figure 7 ; Figure 17 This application provides a schematic diagram of the semiconductor structure formation process. Figure 8 ; Figure 18 This application provides a schematic diagram of the semiconductor structure formation process. Figure 9 ; Figure 19 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 ; Figure 20 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 one; Figure 21 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 two; Figure 22 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 three; Figure 23 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 Four; Figure 24 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 five; Figure 25 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 six; Figure 26 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 seven; Figure 27 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 eight; Figure 28 This application provides a schematic diagram of the semiconductor structure formation process. Figure 10 Nine; Figure 29 This application provides a schematic diagram of the semiconductor structure formation process. Figure 2 ten; Figure 30 This application provides a schematic diagram of the semiconductor structure formation process. Figure 2 eleven; Figure 31 This application provides a schematic diagram of the semiconductor structure formation process. Figure 2 twelve; Figure 32 This application provides a schematic diagram of the semiconductor structure formation process. Figure 2 Thirteen; Figure 33 This application provides a schematic diagram of the semiconductor structure formation process. Figure 2 fourteen; Figure 34 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0025] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0026] In the following description, numerous details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] In the following description, the terms "first," "second," and "third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first," "second," and "third" may be interchanged in a specific order or sequence where permissible, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein. In the drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] Currently, capacitor structures, as charge storage modules in semiconductor structures, determine the overall electrical performance, mass production yield, and long-term reliability of the semiconductor structure through their structural stability and effective capacitance area. The capacitor structures in related technologies mainly include the following two types: The first method involves supporting the lower electrode of the capacitor structure with a fully enclosed support structure. However, since the support structure occupies the space outside the lower electrode, it not only reduces the cross-sectional size of the lower electrode but also causes the loss of capacitance in the outer layer of the lower electrode, affecting the amount of charge stored in the capacitor structure.

[0032] The second type is the unsupported capacitor structure, which means there is no supporting structure to support the lower electrode of the capacitor structure. Although this can increase the cross-section of the lower electrode and maximize the effective area of ​​the lower electrode, the capacitor structure is very prone to bending deformation, which can lead to problems such as capacitor structure failure and cannot meet the long-term reliability requirements of mass production of high-density semiconductor structures.

[0033] Based on this, embodiments of this application provide a semiconductor structure and a method for forming the same; the semiconductor structure and method for forming the same in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0034] Before introducing the embodiments of this application, let's define three directions that may be used to describe the three-dimensional structure in the following embodiments. These three directions may include the X-axis (first), Y-axis (second), and Z-axis (third) directions. The Z-axis direction can be a direction perpendicular to the plane where the substrate is located; the X-axis and Y-axis directions are two intersecting or perpendicular directions on the plane where the substrate is located, wherein the X-axis direction can be the direction in which the capacitor structure extends. Furthermore, a-a' shows a cross-sectional schematic diagram of the plane formed by the Y-axis and Z-axis of the semiconductor structure, b-b' shows a cross-sectional schematic diagram of the plane formed by the X-axis and Z-axis of the semiconductor structure, and c-c' shows a cross-sectional schematic diagram of another plane formed by the X-axis and Z-axis of the semiconductor structure.

[0035] This application provides a semiconductor structure 100, with reference to... Figure 1 and Figure 2 The semiconductor structure 100 includes: a substrate 110, a plurality of capacitor structures 120, and a plurality of support structures 130; the substrate 110 includes a first region A and a second region B adjacent along the X-axis direction (the positions of which can be referenced). Figure 3 Multiple capacitor structures 120 are located on the first region A, extending along the X-axis and arranged in an array along the Y-axis and Z-axis directions; each capacitor structure 120 includes a first electrode 121, which is a cylindrical shape with its opening facing away from the second region; multiple support structures 130 are located between the outer ends C of adjacent first electrodes 121 along the Z-axis direction; the outer ends C are the ends away from the second region.

[0036] In this embodiment, the substrate 110 can be a silicon substrate, a germanium substrate, a silicon germanide substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.

[0037] In this embodiment, the first region A and the second region B are the regions where the memory array is located, for example, a dynamic random access memory (DRAM) array composed of transistor structures, bit line structures, and capacitor structures; wherein, the first region A is the region where the capacitor structure 120 is located, and the second region B is the region where the transistor structure and the bit line structure are located. Here, every two first regions A are arranged adjacently, so that the second electrodes 123 of the capacitor structures 120 in adjacent memory cells can be interconnected, thereby increasing the integration density of the semiconductor structure 100. In other embodiments, the first regions A and the second regions B can also be arranged alternately.

[0038] Please refer to the embodiments in this application. Figure 1 and Figure 2 The capacitor structure 120 extends along the X-axis, meaning it is horizontal. Compared to a vertical capacitor structure with a high aspect ratio, the horizontal capacitor structure reduces the possibility of tipping over or breaking, thus improving its stability. Furthermore, stacking multiple horizontal capacitor structures 120 along the Z-axis increases the integration density of the semiconductor structure 100, enabling miniaturization.

[0039] Furthermore, the number of layers in the capacitor structure 120 can be set according to actual needs. The more layers the capacitor structure 120 has, the greater the capacitance density and the higher the integration level of the semiconductor structure 100. For example, the capacitor structure 120 can have 5 layers (e.g., Figure 1 and Figure 2 (as shown), 50 floors, 100 floors, etc.

[0040] In this embodiment, the material of the first electrode 121 may include any suitable conductive material such as metal nitride or metal silicide. The first electrode 121 has a cylindrical structure with its opening facing away from the second region B. That is, the open end of the first electrode 121 is away from the second region B, while the closed end points towards the second region B. The cylindrical structure of the first electrode 121 is beneficial to increasing the effective area of ​​the capacitor structure 120 and improving the storage capacity.

[0041] Please refer to the embodiments in this application. Figures 1-3 The support structure 130 is located between the outer ends C of adjacent first electrodes 121 along the Z-axis direction, so that at least a portion of the outer ends of the capacitor structure 120 constitutes a single-sided capacitor, and the remaining area constitutes a double-sided capacitor. In this way, compared with a single-sided capacitor, the present application can increase the effective area of ​​the capacitor structure 120 and improve the storage capacity. Compared with a double-sided capacitor, the present application can support the capacitor structure 120 (i.e., the first electrode 121) through the support structure 130, prevent deformation caused by the large depth-to-width ratio of the capacitor structure, and significantly improve the mechanical stability of the capacitor structure.

[0042] In this embodiment, the material of the support structure 130 can be a high mechanical strength insulating material such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon carbide (SiC).

[0043] In summary, by arranging the support structure 130 between the outer ends C of adjacent first electrodes 121 along the Z-axis, a stable mechanical support is provided for the arrayed capacitor structure 120. This not only prevents the capacitor structure 120 from bending and deforming, but also increases the capacitance of the capacitor structure 120, thus balancing the mechanical stability and electrical performance of the semiconductor structure 100.

[0044] In the embodiments of this application, please refer to Figures 3 to 8 The semiconductor structure 100 is described in detail.

[0045] In some embodiments, reference Figure 3 The capacitor structure 120 also includes a dielectric layer 122 and a second electrode 123, which are located on the inner surface of the first electrode 121 and the outer surface of the middle part of the first electrode 121, respectively.

[0046] In this embodiment, the material of the second electrode 123 may include any suitable conductive material such as metal nitride or metal silicide; wherein, the second electrode 123 may be composed of one or more conductive materials, such as silicon nitride covering the surface of the dielectric layer 122 and tungsten filling the gaps between the silicon nitride.

[0047] In this embodiment, the material of the dielectric layer 122 may include a high-k dielectric material, such as one or any combination of lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiOx), or zirconium oxide (ZrO2). In other embodiments, the material of the second electrode 123 may also include polycrystalline silicon, for example, a stack of titanium nitride and polycrystalline silicon.

[0048] It should be noted that the second electrode 123 and the corresponding first electrode 121 are disposed opposite to each other on both sides of the dielectric layer 122; wherein, the dielectric layer 122 extends along the outline of the capacitor structure 120 and forms a connection between adjacent capacitor structures 120.

[0049] Please refer to the embodiments in this application. Figure 3 The support structure 130 is located between the outer ends of adjacent first electrodes 121 along the Z-axis direction, such that at least a portion of the outer end C of the capacitor structure 120 in the Z-axis direction constitutes a single-sided capacitor (e.g., Figure 3As shown in the dashed area, a double-sided capacitor is formed in the remaining area; thus, compared with a single-sided capacitor, this application can increase the effective area of ​​the capacitor structure 120 and improve the storage capacity; compared with a double-sided capacitor, this application can support the capacitor structure (i.e., the first electrode 121) through the support structure 130, prevent deformation caused by the large depth-to-width ratio of the capacitor structure, and significantly improve the mechanical stability of the capacitor structure.

[0050] For details, please continue to refer to Figure 3 The fact that at least a portion of the outer end C of the capacitor structure 120 in the Z-axis direction constitutes a single-sided capacitor means that: since the outer end C of the first electrode 121 in the Z-axis direction is connected to the support structure 130, the first electrode 121 in this region, as well as the dielectric layer 122 and the second electrode 123 inside the first electrode 121, constitute a single-sided capacitor.

[0051] Please continue to refer to this. Figure 3 The capacitor structure 120 forms a double-sided capacitor in the remaining area because the inner and outer sides of the area outside the first electrode 121 that is in contact with the support structure 130 can be sequentially covered by the dielectric layer 122 and the second electrode 123. Thus, in this area, the first electrode 121, and the dielectric layer 122 and the second electrode 123 on both sides of the first electrode 121, form a double-sided capacitor. Here, the area outside the contact between the first electrode 121 and the support structure 130 includes the inner and outer sides of the first electrode 121 along the Y-axis direction, and the area of ​​the first electrode 121 not covered by the support structure 130 along the Z-axis direction.

[0052] It is understood that the area of ​​a single-sided capacitor is the area in the first electrode 121 that is in contact with the support structure 130, and the area of ​​a double-sided capacitor is the area in the first electrode 121 that is not blocked by the support structure 130. Those skilled in the art can adjust the area ratio of single-sided capacitors and double-sided capacitors according to the target capacitance, array arrangement density and mechanical support requirements of the capacitor structure 120.

[0053] In some embodiments, the second electrodes 123 of the plurality of capacitor structures 120 arranged along the Z-axis and Y-axis directions are an integral structure that is interconnected.

[0054] Please refer to the embodiments in this application. Figure 3 The second electrodes 123 of the capacitor structure 120 in the adjacent first region A are connected to each other, which can effectively utilize the space in the semiconductor structure and further realize the miniaturization of the semiconductor structure.

[0055] In some embodiments, the second electrodes 123 of the plurality of capacitor structures 120 arranged along the Z-axis are interconnected as an integral structure; this makes the layout of the memory cells more flexible and increases the application range.

[0056] Next, please refer to Figures 4 to 8 The dimensions of the first electrode 121 are described in detail.

[0057] In some embodiments, reference Figure 4 The dimension d1 of the first electrode 121 along the Y-axis is greater than the dimension d2 of the support structure 130 along the Y-axis.

[0058] In other words, the first electrode 121 extends outward along the Y-axis, or the support structure 130 is recessed inward along the Y-axis. This not only increases the area of ​​the first electrode 121, but also avoids the support structure 130 occupying additional horizontal (i.e. Y-axis) space, thereby increasing the storage capacity of the capacitor structure 120.

[0059] In some embodiments, reference Figure 5 The dimension d3 of the middle part of the first electrode 121 along the Z-axis is greater than the dimension d4 of the outer end C of the first electrode 121 along the Z-axis.

[0060] In other words, the first electrode 121 extends outward along the Z-axis, thereby increasing the area of ​​the first electrode 121 and thus increasing the storage capacity of the capacitor structure 120.

[0061] In some embodiments, reference Figure 6 The outer end C of the first electrode 121 does not extend beyond the support structure 130 in the X-axis direction.

[0062] In other words, the support structure 130 extends outward along the X-axis direction. In this way, while ensuring the support performance of the support structure 130, more of the surface of the first electrode 121 can be exposed, thereby increasing the storage capacity of the capacitor structure 120.

[0063] It should be noted that in other embodiments, the first electrode 121 may also be of other types of size; for example, Figure 4 The dimension d1 of the first electrode 121 along the Y-axis can be equal to the dimension d2 of the supporting structure 130 along the Y-axis; for example, Figure 5 The dimension d3 of the middle part of the first electrode 121 along the Z-axis can also be less than or equal to the dimension d4 of the outer end C of the first electrode 121 along the Z-axis. For example, Figure 6 The outer end of the first electrode 121 is flush with the support structure 130 in the X-axis direction.

[0064] In the embodiments of this application, please refer to Figure 7 The dielectric layer 122 and the second electrode 123 may not extend to the inner end of the first electrode 121 (e.g., Figure 7(As shown in the dashed area), this allows the first electrode 121 to be supported at its inner end by an isolation structure (such as the first isolation structure 182); that is, the first electrode 121 is supported at both ends along the X-axis, thereby improving the stability of the capacitor structure 120.

[0065] In the embodiments of this application, please refer to Figure 8 The dielectric layer 122 and the second electrode 123 may extend to the inner end of the first electrode 121 (e.g., Figure 8 (As shown in the dashed area), this increases the area covered by the dielectric layer 122 and the second electrode 123, effectively improving the storage capacity of the capacitor structure 120.

[0066] In some embodiments, such as Figure 3 and Figure 7 ,or Figure 3 and Figure 8 As shown, the semiconductor structure 100 further includes: a plurality of transistors 160 and a plurality of bit line structures 170. The plurality of transistors 160 are located on the second region B, extending along the X-axis direction and arranged in an array along the Y-axis and Z-axis directions. The source of the transistors 160 is electrically connected to the first electrode 121 of the corresponding capacitor structure 120. The plurality of bit line structures 170 are arranged along the Y-axis direction and extend along the Z-axis direction. The plurality of bit line structures 170 are electrically connected to the drain of the plurality of transistors 160 arranged along the Z-axis direction, respectively.

[0067] In some embodiments, transistor 160 includes an active pillar 161 and a gate structure 162; wherein the active pillar 161 extends along the X-axis direction. The gate structure 162 includes a gate dielectric layer (not shown) and a gate conductive layer (not shown) located on the surface of the middle portion (i.e., channel) of the active pillar 161; a plurality of gate conductive layers arranged along the Y-axis direction are interconnected to form a word line structure.

[0068] In some embodiments, the active pillar 161 may be made of semiconductor materials such as silicon and germanium, or metal oxide materials such as indium gallium zinc oxide (IGZO) and indium tin oxide (ITO).

[0069] In some embodiments, the gate dielectric layer may be composed of a high dielectric constant (HK) material or other suitable materials such as silicon oxide. High dielectric constant materials may include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), zirconium oxide (ZrO2), and aluminum oxide (Al2O3). The gate conductive layer may be made of any material with good conductivity, such as any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

[0070] In some embodiments, the material of the bit line structure 170 includes tungsten, cobalt, copper, aluminum, titanium nitride, polycrystalline silicon, or any combination thereof.

[0071] In some embodiments, please refer to Figure 7 or Figure 8 The semiconductor structure 100 further includes a contact structure 181 located between the source of the transistor 160 and the corresponding first electrode 121. The contact structure 181 may be made of any one or more highly conductive materials such as metal silicide or polysilicon, which can reduce the contact resistance between the transistor 160 and the first electrode 121, thereby reducing the power consumption of the semiconductor structure 100.

[0072] Please refer to the embodiments in this application. Figure 7 or Figure 8 The semiconductor structure 100 further includes: a first isolation structure 182 and a second isolation structure 183; the first isolation structure 182 is located between the gate structure 162 and the capacitor structure 120, and between the gate structure 162 and the bit line structure 170; the second isolation structure 183 is located between adjacent transistors 160 along the Z-axis direction.

[0073] In this embodiment of the application, the generation of leakage current can be reduced by the first isolation structure 182 and the second isolation structure 183; wherein, the materials of the first isolation structure 182 and the second isolation structure 183 can be composed of any one or more insulating materials, such as silicon oxide or silicon oxynitride.

[0074] In addition, embodiments of this application also provide a method for forming a semiconductor structure 100. Figure 9 This is a schematic flowchart of the method for forming a semiconductor structure 100 provided in an embodiment of this application, as shown below. Figure 9 As shown, the method for forming the semiconductor structure 100 includes the following steps: Step S110: Provide a substrate, the substrate including a first region and a second region adjacent to each other along the X-axis direction.

[0075] In step S120, multiple support structures are formed in the first region, arranged in an array along the Y-axis and Z-axis directions.

[0076] Step S130: A capacitor structure is formed between two adjacent support structures along the Z-axis direction, located on the first region and extending along the X-axis direction.

[0077] For details, please refer to Figure 8 The capacitor structure 120 includes a first electrode 121, which is a cylindrical shape with its opening facing away from the second region B. The support structure 130 is located at the outer end C of the first electrode 121; the outer end C is the end away from the second region B.

[0078] In this embodiment, by placing the support structure 130 between the outer ends of adjacent first electrodes 121 along the Z-axis, not only can stable mechanical support be provided at the outer ends of the first electrodes 121, but also the non-end positions of the first electrodes 121 can form a double-sided capacitor. In this way, while preventing the first electrodes 121 (i.e., capacitor structure 120) from bending and deforming, the capacitance of capacitor structure 120 is increased.

[0079] Next, combined Figures 10 to 33 The method for forming semiconductor structures is described in detail.

[0080] Perform step S110, providing, for example Figure 10 The substrate 110 shown includes a first region A and a second region B that are adjacent along the X-axis direction.

[0081] In some embodiments, after providing the substrate 110, the method for forming the semiconductor structure further includes steps S11 to S13.

[0082] Step S11, forming as shown in the figure on the substrate 110 Figure 17 and Figure 18 The stacked structure 111 shown includes a plurality of semiconductor pillars 161a extending along the X-axis and arranged in an array along the Y-axis and Z-axis, and a first sacrificial structure 152 surrounding the periphery of a first portion D1 in the semiconductor pillars 161a; the first portion D1 is located in a first region A.

[0083] In this embodiment of the application, step S11 specifically includes steps S11a to S11e.

[0084] Step S11a, on the surface of substrate 110, form as shown in the figure. Figure 11 The initial stacked structure 111a shown includes semiconductor layers 112 and a fourth sacrificial structure 113 that are alternately stacked along the Z-axis direction.

[0085] In this embodiment, the semiconductor layer 112 may be a silicon layer, or may include other semiconductor elements, such as germanium, or semiconductor compounds, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof. The material of the fourth sacrificial structure 113 may be germanium (Ge), silicon germanide (SiGe), silicon carbide, etc.

[0086] In this embodiment, the materials of the fourth sacrificial structure 113 and the semiconductor layer 112 are different because the fourth sacrificial structure 113 needs to be removed from the stacked structure, while the semiconductor layer 112 is retained. Therefore, the fourth sacrificial structure 113 has a larger selective etching ratio than the semiconductor layer 112, meaning that under the same etching conditions, the fourth sacrificial structure 113 is easier to etch and remove than the semiconductor layer 112. For example, the fourth sacrificial structure 113 can be a silicon germanide layer, and the semiconductor layer 112 can be a silicon layer.

[0087] Please refer to the embodiments in this application. Figure 11 The number of semiconductor layer 112 and fourth sacrificial structure 113 can be set according to the required capacitance density (or storage density). The more semiconductor layer 112 and fourth sacrificial structure 113 there are, the higher the integration density and the greater the capacitance density of the resulting three-dimensional semiconductor structure. For example Figure 11 The semiconductor layer 112 and the fourth sacrificial structure 113 shown are both ten layers.

[0088] The formation processes involved in the embodiments of this application include deposition processes and growth processes. The deposition processes include, but are not limited to: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), and combinations thereof. The growth processes include, but are not limited to: Vapor Phase Epitaxy (VPE), Liquid Phase Epitaxy (LPE), Molecular Beam Epitaxy (MBE), Ion Beam Epitaxy, Solid Phase Epitaxy, and combinations thereof.

[0089] Step S11b: Etch the initial stacked structure 111a located on the side of the first region A away from the second region B, forming as shown in the figure. Figure 12The second etched groove 150 extends along the Y-axis direction as shown.

[0090] The etching processes described in this application include, but are not limited to, dry etching, wet etching, and combinations thereof. It should be noted that, in order to ensure that each layer in the initial stacked structure 111a is etched, the second etching groove 150 extends into the substrate 110.

[0091] Step S11c, etch the stacked structure 111 to form as shown Figure 13 The third etched grooves 151 are arranged at intervals along the Y-axis direction as shown; the remaining semiconductor layers 112 in the stacked structure constitute semiconductor pillars 161a.

[0092] In this embodiment, a plurality of third etching grooves 151 extend along the X-axis direction and are spaced apart along the Y-axis direction.

[0093] In this embodiment, the order in which the third etching groove 151 and the second etching groove 150 are formed is not limited; for example, the third etching groove 151 may be formed first, and then the second etching groove 150 may be formed.

[0094] In step S11d, based on the second etched groove 150, the fourth sacrificial structure 113 is etched laterally to form as shown. Figure 15 and Figure 16 The third transverse groove 115 is shown.

[0095] During implementation, firstly, a groove is formed in the third etched groove 151 as shown in the figure. Figure 14 The first sub-sacrificial structure 152a is shown. Next, based on the second etched groove 150, the fourth sacrificial structure 113 is etched laterally to form as shown. Figure 15 and Figure 16 The third transverse groove 115 is shown.

[0096] It should be noted that, while etching the fourth sacrificial structure 113, a portion of the semiconductor pillar 161a is also etched, thereby increasing the space available for the subsequently formed support structure. In some other embodiments, the semiconductor pillar 161a may also be thinned to provide sufficient space for the formation of the support structure.

[0097] Step S11e, forming as shown in the third transverse groove 115 Figure 17 and Figure 18 The second sub-sacrifice structure 152b shown, the first sub-sacrifice structure 152a and the second sub-sacrifice structure 152b constitute the first sacrifice structure 152.

[0098] In this embodiment, the materials of the first sub-sacrificial structure 152a and the second sub-sacrificial structure 152b may include any suitable material such as polycrystalline silicon, silicon oxide, silicon germanium (SiGe), silicon nitride (SiN), silicon oxynitride (SiON), amorphous carbon (aC), or silicon carbonitride oxynitride (SiOCN). The materials of subsequent sacrificial structures can be understood accordingly.

[0099] Step S12, etch the first sacrificial structure 152 to form as shown. Figure 19 and Figure 20 The first etched groove 153a extends along the Z-axis direction as shown; the first etched groove 153a is located at the outer end C of the active post 161.

[0100] In practice, a sacrificial material layer (not shown) can be formed in the second etched groove 150; next, a mask layer (not shown) is formed on the surface of the sacrificial material layer (not shown), the first sub-sacrificial structure 152a, and the semiconductor pillar 160a, which exposes the first sub-sacrificial structure 152a between the outer ends C of the active pillar 161; subsequently, the exposed first sub-sacrificial structure 152a is removed based on the mask layer to form a structure as shown in the figure. Figure 19 and Figure 20 The first etched groove 153a extends along the Z-axis direction as shown; finally, the sacrificial material layer and mask layer in the second etched groove 150 are removed. Here, the depth of the first etched groove 153a along the X-axis direction can be determined based on the depth of the subsequent support structure along the X-axis direction.

[0101] In this embodiment, since the first etched groove 153a can be formed based on dry etching (such as plasma etching), the second sub-sacrificial structure 152b will not be etched while the first sub-sacrificial structure is being etched. Therefore, the materials of the first sub-sacrificial structure 152a and the second sub-sacrificial structure 152b can be the same.

[0102] In some embodiments, in forming such Figure 4 When the structure shown is used, the method for forming the semiconductor further includes: referencing Figure 21 The first sacrificial structure 152 (i.e. the second sub-sacrificial structure 152b) is etched laterally, so that the first etched groove 153a extends to the space between the adjacent active pillars 161 in the Z-axis direction.

[0103] This makes the second sub-sacrificial structure 152b between the first etched grooves 153a smaller in size along the Y-axis, thereby making the support structure 130 smaller in size along the Y-axis, which in turn makes the capacitor structure 120 more spacious and increases the capacitance of the capacitor structure 120.

[0104] Step S13, in the first etched groove 153a, form as shown Figure 22 and Figure 23 The second sacrificial structure 153 shown is in contact with the outer end C of the active post 161.

[0105] It should be noted that, since the first sacrificial structure 152 and the second sacrificial structure 153 need to be removed in subsequent processes, the materials of the first sacrificial structure 152 and the second sacrificial structure 153 are different; for example, the material of the first sacrificial structure 152 is silicon oxide, and the material of the second sacrificial structure 153 is silicon nitride.

[0106] Execute step S120 to form, on the first region A, as shown in the figure Figure 27 The diagram shows multiple support structures 130 arranged in an array along the Y-axis and Z-axis directions.

[0107] In some embodiments, the support structure 130 is formed by the following steps: steps S121 and S122.

[0108] Step S121, based on the second etched groove 150, the first sacrificial structure 152 is etched laterally to form as shown in the figure. Figure 24 and Figure 25 The first transverse groove 116 is shown; the first transverse groove 116 is located between adjacent second sacrificial structures 153 along the Y-axis direction.

[0109] In this embodiment, the depth of the first transverse groove 116 along the X-axis direction can be controlled by the etching time; wherein, in order to avoid damage to the first sacrificial structure 152 when etching the first transverse groove 116, the depth of the first transverse groove 116 along the X-axis direction does not exceed the depth of the second sacrificial structure 153 along the X-axis direction.

[0110] In this embodiment, the first lateral groove 116 provides space for the subsequent deposition of the support structure 130 (such as silicon carbonitride), and the depth of the first lateral groove 116 along the X-axis defines the dimension of the support structure along the X-axis. It should be noted that the hard mask layer on the surface of the top layer structure is shown in the three-dimensional view.

[0111] Step S122, forming in the first transverse groove 116 as shown Figure 29 The support structure 130 shown.

[0112] Please refer to the following when implementing: Figure 26 and Figure 27 An initial support structure 130a is formed on the exposed surfaces of the first transverse groove 116 and the second etched groove 150; the initial support structure 130a fills the first transverse groove 116. Next, please refer to... Figure 28In the remaining second etched groove 150, the filling structure 131 is filled; the material of the filling structure 131 can be any suitable material such as polysilicon. Finally, please refer to... Figure 29 The filling structure 131 and the initial support structure 130a located in the second etching groove 150 are etched until the remaining initial support structure 130a at the bottom of the second etching groove 150 is fully exposed to the semiconductor pillar 161a. The remaining initial support structure 130a located in the first transverse groove 116 constitutes the support structure 130.

[0113] In this embodiment, the remaining initial support structure 130a on the surface of the substrate 110 constitutes the protective structure 140. In this embodiment, since the support structure 130 and the protective structure 140 are formed through the same initial support structure 130a, there is no need to add an additional step to form the protective structure 140, simplifying the process and improving production efficiency. Furthermore, by using the same material for the support structure 130 and the protective structure 140, and since the support structure 130 provides support during the formation of the capacitor structure (first electrode), the material of the support structure 130 is one that will not be damaged during etching. This ensures that the protective structure 140 will not be damaged during the formation of the capacitor structure. Thus, the capacitor structure and the substrate 110 can be completely isolated, effectively suppressing leakage paths.

[0114] In some embodiments, after forming the support structure 130, the method for forming the semiconductor structure 100 further includes steps S21 and S22.

[0115] Step S21, based on the second etched groove 150, remove the second sacrificial structure 153 to expose the... Figure 30 The first etched groove 153a is shown.

[0116] Step S22, in the first etched groove 153a, form as shown Figure 31 The third sacrificial structure 154 is shown; the third sacrificial structure 154 is made of the same material as the first sacrificial structure 152.

[0117] The etching selectivity ratio of the support structure 130 to any one of the first sacrificial structure 152, the second sacrificial structure 153, and the third sacrificial structure 154 is less than 1:2. For example, the etching selectivity ratio can be a value between (1:2), (1:3), (1:4), (1:10), (1:15), (1:20), or any combination thereof.

[0118] In this embodiment, the etching selectivity ratio of the support structure 130 to any one of the first sacrificial structure 152, the second sacrificial structure 153, and the third sacrificial structure 154 is less than 1:2. This means that the material of the support structure 130 has a lower etching rate than any one of the first sacrificial structure 152, the second sacrificial structure 153, and the third sacrificial structure 154 in the subsequent etching process. That is, under the same etching conditions, the etching rates of the first sacrificial structure 152, the second sacrificial structure 153, and the third sacrificial structure 154 are all faster than that of the material of the support structure 130. Thus, in the subsequent process steps that require the removal of the sacrificial structures, the support structure 130 can avoid etching, thereby ensuring the structural integrity of the support structure 130.

[0119] In the embodiments of this application, see Figure 32 The material of the support structure 130 can be silicon nitride (SiN), silicon carbide (SiC), or silicon carbonitride (SiCN), etc. Furthermore, when the material of the first sacrificial structure 152 (i.e., the first sub-sacrificial structure 152a and the second sub-sacrificial structure 152b) is silicon oxide, the material of the second sacrificial structure 153 is silicon nitride, and the material of the third sacrificial structure 154 is silicon oxide, the material of the support structure 130 can be silicon carbonitride. On the one hand, because silicon carbonitride has a lower etching selectivity rate than sacrificial materials such as silicon oxide and silicon-germanium, meaning that under the same etching conditions, silicon carbonitride is not easily etched, the subsequent support and protective structures can be protected from damage during the removal of the sacrificial structures. On the other hand, because silicon carbonitride has high hardness and high elastic modulus, the subsequently formed support structure can provide reliable mechanical support for the subsequently formed capacitor structure.

[0120] It should be noted that the specific value of the etching selectivity can be adjusted according to the actual process conditions, as long as the etching rate of the support structure 130 is lower than the etching rate of each sacrificial structure.

[0121] In this embodiment of the application, the method for forming the semiconductor structure further includes: removing the remaining filling structure 131.

[0122] In step S130, a capacitor structure 120 is formed between two adjacent support structures 130 along the Z-axis direction, located on the first region A and extending along the X-axis direction.

[0123] In this embodiment of the application, the capacitor structure 120 includes a first electrode 121, which is a cylindrical shape with its opening facing the second region B. The support structure 130 is located at the outer end of the first electrode 121; the outer end is the end facing the second region B.

[0124] In some embodiments, step S130 includes steps S131 to S134.

[0125] Step S131, based on the second etched groove 150, the semiconductor pillar 161a is etched laterally to form as shown. Figure 33 The second transverse groove 117 is shown.

[0126] In this embodiment, the semiconductor pillar 161a located in the first region A is laterally etched through the sidewall of the second etched groove 150 to form a second lateral groove 117 and an active pillar 161. The second lateral groove 117 provides a space for the subsequently formed first electrode 121. It is understood that the inner wall of the second lateral groove 117 is used to form the first electrode 121; therefore, the size of the first electrode 121 can be adjusted by adjusting the size of the second lateral groove 117.

[0127] In some embodiments, the dimension of the second transverse groove 117 along the Y-axis is larger than the dimension of the support structure 130 along the Y-axis; thus, a structure can be formed as follows: Figure 4 The structure shown not only increases the area of ​​the first electrode 121 but also avoids the support structure 130 occupying additional horizontal (i.e., Y-axis) space, thereby increasing the storage capacity of the capacitor structure 120.

[0128] In some embodiments, the dimension of the middle portion of the second transverse groove 117 in the Z-axis direction is greater than the dimension of the outer end portion C of the second transverse groove 117 in the Z-axis direction; thus, a shape such as Figure 5 The structure shown increases the area of ​​the first electrode 121, thereby increasing the storage capacity of the capacitor structure 120.

[0129] In the embodiments of this application, when forming such Figure 8 In the structure shown, the depth of the second transverse groove 117 along the X-axis direction can not exceed the depth of the second sub-sacrificial structure 152b along the X-axis direction (e.g., Figure 33 As shown in the figure, this allows the second electrode 123 to completely cover the sidewall of the first electrode 121, thereby increasing the area of ​​the capacitor structure and thus increasing the storage capacity.

[0130] In some other embodiments, when forming such Figure 7 In the structure shown, the depth of the second transverse groove 117 along the X-axis can exceed the depth of the second sub-sacrificial structure 152b along the X-axis, so that the subsequent first electrode 121 can be supported at its inner end by the subsequent isolation structure; that is, the first electrode 121 is supported at both ends along the X-axis, thereby improving the stability of the capacitor structure 120.

[0131] In this embodiment of the application, after forming the second lateral groove 117, the method for forming the semiconductor structure further includes: forming as shown in the figure. Figure 7 or Figure 8 The contact structure 181 shown is located on the side of the second transverse groove 117 near the active post 161; wherein, the contact structure 181 can be made of any one or more highly conductive materials such as metal silicide, which can reduce the contact resistance between the subsequent transistor and capacitor structure, thereby reducing the power consumption of the semiconductor structure.

[0132] Please refer to step S132. Figure 7 or Figure 8 The first electrode 121 is formed in the second transverse groove 117.

[0133] In step S133, the remaining first sacrificial structure 152 and third sacrificial structure 154 are removed, exposing the outer surface of the first electrode 121.

[0134] In this embodiment, the remaining first sacrificial structure 152 and third sacrificial structure 154 can be completely removed sequentially through one or more selective etching processes, exposing the outer surface of the first electrode 121. Since the etching selective rate of the support structure 130 is less than that of either the first sacrificial structure 152 or the third sacrificial structure 154, the support structure 130 will not be damaged when the first sacrificial structure 152 and the second sacrificial structure 153 are removed, thus improving the manufacturing yield.

[0135] In this embodiment, after removing the first sacrificial structure 152 and the third sacrificial structure 154, the outer end of the first electrode 121 along the X-axis is supported by the support structure 130, thereby preventing the first electrode 121 from bending or collapsing. Furthermore, because the outer end of the first electrode 121 is supported by the support structure 130, thus forming... Figure 8 The structure shown allows the depth of the third sacrificial structure 154 along the X-axis to exceed that of the first electrode 121 (i.e., the second transverse groove 117). This way, after removing each sacrificial structure, both the upper and lower surfaces of the first electrode 121 along the Z-axis can be fully exposed. This ensures that the first electrode 121 will not bend or collapse even if the end of the first electrode 121 away from the second region B is unsupported. At the same time, it increases the exposed area of ​​the first electrode 121 along the Z-axis, thereby increasing the area of ​​the capacitor structure 120 and increasing the storage capacity.

[0136] Please refer to step S134. Figure 7 or Figure 8 A dielectric layer 122 and a second electrode 123 are sequentially formed on the inner and outer surfaces exposed by the first electrode 121; wherein the second electrode 123 fills the second etched groove 150.

[0137] In this embodiment, the support structure 130 is located between the outer ends of adjacent first electrodes 121 along the Z-axis, such that at least a portion of the outer ends of the capacitor structure 120 in the Z-axis direction forms a single-sided capacitor (as shown by the dashed area), while the remaining area forms a double-sided capacitor. In this way, compared to a single-sided capacitor, this application can increase the effective area of ​​the capacitor structure 120 and improve the storage capacity. Compared to a double-sided capacitor, this application can support the capacitor structure 120 (i.e., the first electrode 121) through the support structure 130, preventing deformation caused by the large depth-to-width ratio of the capacitor structure 120, and significantly improving the mechanical stability of the capacitor structure.

[0138] It should be noted that, in the embodiments of this application, the second electrode 123 may be composed of one or more conductive materials, such as silicon nitride covering the surface of the dielectric layer 122 and tungsten filling the gaps between the silicon nitride.

[0139] In some embodiments, the method for forming the semiconductor structure 100 further includes steps S31 to S32.

[0140] Step S31, please refer to Figure 7 or Figure 8 On the surface of the first region A away from the second region B, a plurality of transistors 160 are formed extending along the X-axis and arranged in an array along the Y-axis and Z-axis directions; the source of the transistors 160 is connected to the first electrode 121 of the corresponding capacitor structure 120.

[0141] First, please refer to Figure 7 or Figure 8 On the surface of the first region A away from the second region B, a fourth etched groove (not shown) is formed that penetrates the remaining stacked structure. Based on the fourth etched groove (not shown), the remaining fourth sacrificial structure 113 is removed to form a fourth lateral groove (not shown). Next, based on the fourth lateral groove, the remaining active pillar 161 is thinned. Finally, a first isolation structure 182, a gate structure 162, and a first isolation structure 182 are sequentially formed in the fourth lateral groove along the X-axis direction.

[0142] In this embodiment, transistor 160 includes an active pillar 161 and a gate structure 162; wherein, the active pillar 161 extends along the X-axis direction. The gate structure 162 includes a gate dielectric layer (not shown) and a gate conductive layer (not shown) located on the surface of the middle portion (i.e., channel) of the active pillar 161; a plurality of gate conductive layers arranged along the Y-axis direction are interconnected to form a word line structure.

[0143] In this embodiment of the application, the method for forming a semiconductor structure further includes: forming a second isolation structure 183 located between adjacent transistors 160 along the Z-axis direction.

[0144] Step S32, please refer to Figure 7 or Figure 8 The method of forming the semiconductor structure 100 further includes: forming a plurality of bit line structures 170 arranged along the Y-axis direction and extending along the Z-axis direction; the bit line structures 170 are connected to the drains of a plurality of transistors 160 arranged along the Z-axis direction.

[0145] It should be noted that the order in which the various steps are formed is not limited in the embodiments of this application. For example, transistor 160 may be formed after the first electrode 121, or it may be formed after capacitor structure 120.

[0146] In this embodiment, multiple support structures 130 are first set on the first region A along the Y-axis and Z-axis directions, and then a capacitor structure 120 is formed between two adjacent support structures 130. Only the outer end C of the capacitor structure 120 (i.e. the first electrode 121) is supported by the support structure 130, thereby greatly increasing the effective area of ​​the capacitor structure 120, increasing the capacitance while preventing the capacitor structure 120 from deforming.

[0147] It is understood that, in the embodiments of this application, the above-described process method for controlling the size of the support structure by etching depth is merely an exemplary preferred embodiment and does not constitute a limitation of this application. Those skilled in the art can flexibly adjust the relevant process parameters according to the target design size of the support structure, the array arrangement density, and the etching process window to achieve control over the size of the support structure 130 along the X-axis direction.

[0148] This application also provides an electronic device. Figure 34 This is a schematic diagram of the structure of an electronic device 1 provided in an embodiment of this application, as shown below. Figure 34 As shown, the electronic device has a storage function, including a processor 2 and a memory 3 electrically connected to the processor. The memory device includes the aforementioned... Figures 1 to 8 The semiconductor structure 100 described in the text.

[0149] Electronic devices can be terminal devices, such as personal computers, mobile phones, tablets, consumer electronics (e.g., smart home appliances, autonomous vehicles, smart wearables such as smartwatches and smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, and also servers and data centers. The memory device can be, for example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or double data rate synchronous dynamic random access memory (DDRAM). SDRAM, DDRSDRAM, etc., are not specifically limited here. For DRAM chips, they can conform not only to DDR, DDR2, DDR3, DDR4, DDR5, and DDR6 memory specifications, but also to LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6 memory specifications, which are also not specifically limited here. The storage function in electronic device 1 can be implemented through these memory devices 3.

[0150] In some embodiments, the processor 2 and memory 3 can be two separate chips forming an independent memory. In other embodiments, the memory 3 and processor 2 can also be integrated into the same chip to form an embedded memory. This electronic device 1 is similar to the one described above. Figures 1 to 29 The described semiconductor structure 100 can solve the same technical problem and achieve the same expected results.

[0151] In the several embodiments provided in this application, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0152] The features disclosed in the several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0153] The above are merely some embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the above-described scope.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first region and a second region adjacent to each other along a first direction; Multiple capacitor structures are located on the first region, extending along the first direction and arranged in an array along the second and third directions; each capacitor structure includes a first electrode, which is a cylindrical shape with its opening facing away from the second region; the dimension of the middle portion of the first electrode along the third direction is larger than the dimension of the outer end portion of the first electrode along the third direction. Multiple support structures are respectively located between the outer ends of adjacent first electrodes along the third direction; the outer ends are the ends away from the second region; Wherein, the first direction and the second direction intersect and are parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

2. A semiconductor structure according to claim 1, characterized in that, The dimension of the first electrode along the second direction is greater than the dimension of the support structure along the second direction.

3. A semiconductor structure according to claim 1, characterized in that, The capacitor structure also includes: The dielectric layer and the second electrode are located, sequentially, on the inner surface of the first electrode and the outer surface of the middle portion of the first electrode.

4. A semiconductor structure according to claim 3, characterized in that, The second electrodes of the plurality of capacitor structures arranged along the third direction are interconnected as a single, integral structure; or... The second electrodes of the plurality of capacitor structures arranged along the third direction and the second direction are interconnected as an integral structure.

5. A semiconductor structure according to claim 1, characterized in that, The outer end of the first electrode does not extend beyond the support structure in the first direction.

6. A semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes: Multiple transistors are located on the second region, extending along the first direction and arranged in an array along the second direction and the third direction; the source of each transistor is electrically connected to the first electrode of the corresponding capacitor structure. Multiple bit line structures are arranged along the second direction and extend along the third direction; the multiple bit line structures are respectively electrically connected to the drains of multiple transistors arranged along the third direction.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region adjacent to each other along a first direction; In the first region, multiple support structures are formed in an array arranged along the second and third directions; Between two adjacent support structures along the third direction, a capacitor structure is formed on the first region and extending along the first direction; the capacitor structure includes a first electrode, which is a cylindrical shape with its opening facing away from the second region; the support structure is located at the outer end of the first electrode; the dimension of the middle part of the first electrode along the third direction is greater than the dimension of the outer end of the first electrode along the third direction; the outer end is the end away from the second region. Wherein, the first direction and the second direction intersect and are parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

8. The forming method according to claim 7, characterized in that, After providing the substrate, the method includes: A stacked structure is formed on the substrate; the stacked structure includes a plurality of semiconductor pillars extending along the first direction and arranged in an array along the second direction and the third direction, and a first sacrificial structure surrounding a first portion of the semiconductor pillars; the first portion is located in the first region; The first sacrificial structure is etched to form a first etched groove extending along the third direction; the first etched groove is located at the outer end of the semiconductor pillar; A second sacrificial structure is formed in the first etched groove, and the second sacrificial structure contacts the outer end of the semiconductor pillar.

9. The forming method according to claim 8, characterized in that, Before forming the second sacrificial structure, the method further includes: The first sacrificial structure is etched laterally, such that the first etched groove extends between the third-direction adjacent semiconductor pillars.

10. The forming method according to claim 8 or 9, characterized in that, The stacked structure has a second etched groove adjacent to the first region; the support structure is formed by the following steps: Based on the second etched groove, a portion of the first sacrificial structure is etched laterally to form a first lateral groove; the first lateral groove is located between adjacent second sacrificial structures along the second direction; The support structure is formed in the first transverse groove.

11. The forming method according to claim 10, characterized in that, After forming the support structure, the method further includes: Based on the second etched groove, the second sacrificial structure is removed, exposing the first etched groove; A third sacrificial structure is formed in the first etched groove; the third sacrificial structure is made of the same material as the first sacrificial structure. The etching selectivity ratio of the support structure to any one of the first sacrificial structure, the second sacrificial structure, and the third sacrificial structure is less than 1:

2.

12. The forming method according to claim 11, characterized in that, The capacitor structure is formed through the following steps: Based on the second etched groove, the first portion of the semiconductor pillar is removed to form a second transverse groove; The first electrode is formed in the second transverse groove; Remove the first sacrificial structure and the third sacrificial structure to expose the two side surfaces of the first electrode and the outer surface of the middle part of the first electrode; A dielectric layer and a second electrode are sequentially formed on the inner and outer surfaces exposed by the first electrode.

13. The forming method according to claim 12, characterized in that, The dimension of the second transverse groove along the second direction is larger than the dimension of the support structure along the second direction; and / or, The middle part of the second transverse groove is larger in the third direction than the outer end of the second transverse groove.

14. The forming method according to claim 8 or 9, characterized in that, Before forming the capacitor structure extending along the first direction, the method further includes: In the second region, a plurality of transistors are formed extending along the first direction and arranged in an array along the second direction and the third direction; the source of the transistor is electrically connected to the first electrode of the corresponding capacitor structure; A plurality of bit line structures are formed, arranged along the second direction and extending along the third direction; the bit line structures are electrically connected to the drains of a plurality of transistors arranged along the third direction.

15. An electronic device, characterized in that, include: processor; A memory coupled to the processor, wherein the memory comprises a semiconductor structure as described in any one of claims 1 to 6.

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